TABLE OF CONTENTS EURO-DAC 96 with EURO-VHDL 96

Welcome
Steering Committee Members EURO-DAC 96 with EURO-VHDL 96
Program Committee Members EURO-DAC 96
Program Committee Members EURO-VHDL 96
Reviewer's Board EURO-DAC 96 with EURO-VHDL 96

Session D-01 ANALOG AND MIXED MODE SIMULATION

Chair: Bernhard Klaassen, GMD, Sankt Augustin, Germany

The approaches presented in this session help to combine different levels of simulation: First, a hierarchical methodology for analogue behavioural modelling, followed by an approach combining timing and circuit simulation. The third paper presents a generalized coupling concept for analogue simulation.

A Hierarchical Approach to the Analog Behavioral Modeling of Neural Networks using HDL-A

M. Ahmed, H. Ragaie, H. Haddara

BRASIL: The Braunschweig Mixed-Mode-Simulator for Integrated Circuits

U. Bretthauer, E. Horneber

Generalized Coupling as a Way to Improve the Convergence in Relaxation-Based Solvers

V. Dmitriev-Zdorov

Session D-02 LOW POWER SYNTHESIS

Chair: Enrico Macii, Politecnico di Torino, Italy

This session presents two papers on techniques for low power analysis and synthesis. The first paper accounts for temporal and spatial correlations in estimating transition probabilities for sequential circuits. The second paper describes a state assignment technique for achieving low-power FSMs, given the input sequencies.

Power Analysis for Sequential Circuits at Logic Level

M. Senn, P. Schneider, B. Wurth

State Assignment for FSM Low Power Design

M. Koegst, G. Franke, K. Feske

Session D-03 DESIGN EXPERIENCE

Chair: Klaus D. Mueller-Glaser, ITIV Universität Karlsruhe, Germany

Experiences in methodologies and tools used for the design of electronic control units in automotive and robotic applications are presented. Issues are specification, system level modelling and simulation, HW/SW tradeoffs, Fuzzy vs. PID-control, analog ASIC design, commercial tool usage.

Specification and Design of Electronic Control Units

J. Bortolazzi, T. Hirth, T. Raith

Exploration of Hardware/Software Design Space through a Codesign of Robot Arm Controller

M. Abid, A. Changuel, A. Jerraya

Design of an Adaptive Motors Controller Based on Fuzzy Logic Using Behavioural Synthesis

A. Changuel, R. Rolland, A. Jerraya

Implementing Fuzzy Control Systems Using VHDL and Statecharts

V. Salapura, V. Hamann

A Top Down Mixed-Signal Design Methodology Using a Mixed-Signal Simulator and Analog HDL

T. Murayama, Y. Gendai

Session D-04 TIMING MODELING

Chair: Jacques Benkoski, EurEPIC Sarl, Gières, France

This session covers the evolving nature of the timing problems; what were previously second order effects such as glitches and interconnect must now be modeled. Asynchronous designs are also becoming more common and their timing problems must be addressed as well.

New Approach in Gate-Level Glitch Modelling

D. Rabe, W. Nebel

A New Concept for Accurate Modeling of VLSI Interconnections and its Application for Timing Simulation

B. Wunder, G. Lehmann, K. Müller-Glaser

Timing Verification for Asynchronous Design

R. Davies, J. Woods

Session D-05 DESIGN FLOW AND DESIGN MANAGEMENT

Chair: Ralph H.J.M. Otten, Delft University of Technology, The Netherlands

Starting from a novel approach for designing and implementing controllers targetted for structured data processing, design flows, design flow data management, design flow planning and control and design flow generation is discussed.

A System for Compiling and Debugging Structured Data Processing Controllers

A. Seawright, U. Holtmann, W. Meyer, B. Pangrle, R. Verbrugghe, J. Buck

A Graphical Data Management System for HDL-Based ASIC Design Projects

C. Mayer, H. Sahm, J. Pleickhardt

An Integrated Concept for Design Project Planning and Design Flow Control

M. Ryba, U Baitinger

Automatic Workflow Generation

V Shepelev, S Director

Session D-06 (PANEL) WHAT'S HOT IN LOW POWER DESIGN?

Chair: Enrico Macii, Politecnico di Torino, Italy

For today's electronic devices low-power dissipation is desirable, and for some special applications, power consumption is a critical issue. An integrated framework for low power design of digital systems must provide the user with tools for low power synthesis at different levels of abstractions; in particular, low power consumption needs to be targeted at the system, architectural, logic and physical levels. Besides synthesis algorithms, the availability of tools for accurately estimating power consumption of systems at different stages of the design process is essential. This panel will investigate the progress that has been made in this area in the last few years. Both the academic and the industrial point of views will be illustrated and discussed by designers and scientists active in this field.

Panelists:
Jordi Cortadella, Universidad Politecnica Catalunya, Barcelona, Spain
Giovanni de Micheli, Stanford University, CA, USA
Massoud Pedram, University of Southern California, Los Angeles, CA, USA
Jan Rabaey, University of California at Berkeley, CA, USA
Rob Roy, NEC C&C Research Laboratory, Princeton, NJ, USA
Kees van Berkel, Philips Research Laboratories, Eindhoven, The Netherlands

Session D-07 PARTITIONING

Chair: Klaus Buchenrieder, Siemens AG, München, Germany

This session is introduced with an invited talk which gives a comprehensive overview of the state of the art in HW/SW partitioning. After that, two research papers present partitioning approaches based on combinatorial optimization methods.

Synthesis from Mixed Specifications

V. Mooney, C. Coelho, T. Sakamoto, G. de Micheli

A System Level HW/SW Partitioning and Optimization Tool

M. Schwiegershausen, H. Kropp, P. Pirsch

A New HW/SW Partitioning Algorithm for Synthesizing the Highest Performance Pipelined ASIPs with Multiple Identical FUs

M. Imai, N. Binh, A. Shiomi

Session D-08 LOGIC AND FSM SYNTHESIS

Chair: Utz Baitinger, IPVR Universität Stuttgart, Germany

The first paper incorporates sequential optimization into hierarchical synthesis. The second one describes a controller synthesis technique from regular expressions describing protocol-intensive applications. The third paper combines both behavioural and spectral domains in boolean matching for technology mapping.

Automatic Structuring and Optimization of Hierarchical Designs

H. Eikerling, W. Rosenstiel

Controller Optimization for Protocol Intensive Applications

A. Crews, F. Brewer

Library Based Technology Mapping Using Multiple Domain Representations

J. Bullmann, E. Schubert, U. Kebschull, W. Rosenstiel

Session D-09 BDD OPTIMIZATION TECHNIQUES

Chair: Hans Eveking, Technische Universität Darmstadt, Germany

Two papers introduce compilation techniques and a new calculation method for boolean operations on OBDDs. In addition, decomposition and re-encoding procedures for the OBDD-based symbolic traversal of FSMs are presented.

Compilation of Optimized OBDD-Algorithms

S. Höreth

Incremental Re-encoding for Symbolic Traversal of Product Machines

S. Quer, G. Cabodi, P. Camurati, L. Lavagno, E. Sentovich, R. Brayton

MORE: An Alternative Implementation of BDD Packages by Multi-Operand Synthesis

A. Hett, R. Drechsler, B. Becker

Decomposed Symbolic Forward Traversals of Large Finite State Machines

S. Quer, G. Cabodi, P. Camurati

Session D-10 CODESIGN METHODOLOGY AND COSPECIFICATION

Chair: Klaus D. Müller-Glaser, ITIV Universität Karlsruhe, Germany

This session presents three papers on codesign approaches based on different specification formalisms. The first paper uses a combination of C, VHDL and a rules file, the second paper employs extended Statecharts, and the last paper is based on annotated task graphs.

COMET: A Hardware-Software Codesign Methodology

M. Knieser, C. Papachristou

Mapping Statechart Models onto an FPGA-Based ASIP Architecture

K. Buchenrieder, A. Pyttel, C. Veith

MILP Based Task Mapping for Heterogeneous Multiprocessor System

A. Bender

Session D-11 SYSTEM LEVEL DESIGN AND SYNTHESIS

Chair: Giovanni de Micheli, Stanford University, CA, USA

This session addresses system design issues for software and hardware. The first paper describes a technique for instruction set selection that can improve code quality for embedded DSPs. The second paper presents a system-level performance estimation technique that accounts for memories and pipelined functional units. The last paper introduces packaging constraints into the system synthesis process by presenting a hierarchical behavioural partitioning algorithm.

Instruction Selection for Embedded DSPs with Complex Instructions

R. Leupers, P. Marwedel

Rapid Performance Estimation for System Design

S. Narayan, D. Gajski

Hierarchical Behavioral Partitioning for Multicomponent Synthesis

N. Kumar, V. Srinivasan, R. Vemuri

Session D-12 NEW ASPECTS ON TESTING

Chair: Wilfried Daehn, SICAN GmbH, Hannover, Germany

This session addresses path delay fault testability, weighted random pattern testing, BIST, and the testable design of SC circuits.

Testable Path Delay Fault Cover for Sequential Circuits

A. Krstic, S. Chakradhar, K. Cheng

Efficient Random Testing with Global Weights

A. Kunzmann

Fault Tolerant and BIST Design of a FIFO Cell

F. Corno, P. Prinetto, M. Reorda

A Digital Method for Testing Embedded Switched Capacitor Filters

M. Robson, G. Russell

Session D-13 CODESIGN METHODOLOGY AND COSIMULATION

Chair: Ahmed Amine Jerraya, TIMA/INPG, Grenoble Cedex, France

This session combines a paper on the cosimulation of mechatronic systems and three papers on codesign methodology. In the papers on methodology emphasis is given to design reuse aspects, life-cycle aspects, and the role of simulation in Hardware/Software Codesign.

Hardware/Software-Cosimulation for Mechatronic System Design

G. Pelz, J. Bielefeld, G. Hess, G. Zimmer

CoWare - A Design Environment for Heterogeneous Hardware/Software Systems

K. Van Rompaey, D. Verkest, I. Bolsens, H. De Man

An Approach for Integrated Specification and Design of Real-Time Systems

Y. Tanurhan, S. Schmerler, H. Gölz, K. Müller-Glaser

An Integrated Approach to Engineering Computer Systems

D. Morris, D. Evans, P. Green

Session D-14 (Joint Panel EURO-DAC and EURO-VHDL) WHICH FORMAL VERIFICATION TECHNIQUE IS MORE APPLICABLE IN INDUSTRY TODAY - EQUIVALENCE CHECKING OR PROPERTY CHECKING?

Chair: Luc Claesen, IMEC, Leuven, Belgium

Growing system integration and complexity currently require extreme attention towards design correctness. Formal verification methods have evolved over the last few year into industrial application. This panel will explore the potentials and difficulties for industrial adoption of formal verification in design flows.

Panelists:
Pierre Ragon, Philips TRT Communication Systems, Le Plessis Robinson, France
Michael Payer, Siemens, Muenchen, Germany
Frederic Rocheteau, SGS Thomson INMOS Ltd., Almondsbury, UK
Simon Read, COMPASS Design Automation, Rochester, MN, USA
Dominique Borrione, TIMA/INPG, Grenoble Cedex, France
Gerry Musgrave, Abstract Hardware Ltd. and Brunel University of West London, Uxbridge, UK

Session D-15 KEY TECHNOLOGIES AND CAD OF MICROSYSTEMS

Chair: Karl-Heinz Diener, Fraunhofer Gesellschaft - Institut für Integrierte Schaltungen, Dresden, Germany

The microsystem technology opens new ways for the integration of different sensors and actuators together with electronic components (mostly for information processing) on silicon. The inherent integration process is aimed at setting up flexible, adaptive, and intelligent systems intended to be applied to new products. The design of Microsystems requires to become familiar with both the dedicated technology for production and also the sophisticated CAD tools and systems. The goal of this session is to inform on what is feasible with key technologies for Microsystems, and how to design microsystems. That will be presented by two invited talks based on several examples of latest applications .

Spotlights on Recent Developments in Microsystem Technology

S. Büttgenbach

CAD of Microsystems - A Challenge for Systems Engineering

K. Müller-Glaser

Session D-16 ASYNCHRONOUS SYNTHESIS AND STORAGE OPTIMIZATION

Chair: Jordi Cortadella, Universidad Politecnica Catalunya, Barcelona, Spain

This session contains two regular papers on asynchronous circuit synthesis and two short papers on techniques for storage optimization at the RT/logic and the behavioral level.

A Heuristic Covering Technique for Optimizing Average-Case Delay in the Technology Mapping of Asynchronous Burst-Mode Circuits

P. Beerel, K. Yun, W. Chou

Automatic Synthesis of Extended Burst-Mode Circuits Using Generalized C-Elements

K. Yun

Storage Optimization by Replacing Some Flip-Flops with Latches

T. Wu, Y. Lin

Assignment of Storage Values to Sequential Read-Write Memories

S. Gerez, E. Woutersen

Session D-17 MODELLING, SIMULATION OF MICROSYSTEMS AND MULTI LAYER ROUTING IN PCBS

Chair: Wolfgang Nebel, Carl-von-Ossietzky-Universität and OFFIS, Oldenburg, Germany

Because of their multi-disciplinary nature, the design of microsystems requires the using of CAD tools and systems. Modelling and simulation seem to be the crucial steps to coming up with right first designs. Two papers are addressed to that problem. Generally, the system integration realized by microsystems on silicon and PCBs, respectively, demands to pay most attention to achieving acceptable solutions of wiring the components necessary for creating systems. This problem will be tackled in the session, too.

Estimation of the Number of Routing Layers and Total Wirelength in a PCB through Wiring Distribution Analysis

I. Hom, J. Granacki

Describing Space-Continuous Models of Microelectromechanical Devices for Behavioural Simulation

Z. Mrcarica, D. Glozic, V. Litovski, H. Detter

Simulation and Design Optimization of Microsystems Based on Standard Simulators and Adaptive Search Techniques

S. Meinzer, A. Quinte, M. Gorges-Schleuter, W. Jakob, W. SüB, H. Eggert

Session D-18 TIMING ISSUES IN SYNTHESIS

Chair: Kurt J. Antreich, TU Muenchen, Germany

This session contains papers describing issues at the behavioural, RTL and logic levels. The first paper describes a clock optimization technique for pipelined implementations of design behaviours. The second paper addresses the problem of false paths in delay estimation at the RT-level. The third paper describes a timing optimization technique at the logic level that employs improved redundancy addition and removal.

Clock Optimization for High-Performance Pipelined Design

H. Juan, D. Gajski, S. Bakshi

False Path Exclusion in Delay Analysis of RTL-Based Datapath-Controller Designs

C. Papachristou, M. Nourani

Timing Optimization by an Improved Redundancy Addition and Removal Technique

L. Entrena , J. Espejo, E. Olías, J. Uceda

Session D-19 PHYSICAL DESIGN FOR DEEP SUBMICRON

Chair: Tokinori Kozawa, Semiconductor Technology Academic Research Center, Tokyo, Japan

There are many restrictions to design sub-micron LSI. To solve this difficulties designer expect to have good tradeoffs by generic methods. An invited paper reviews the problem of deep submicron LSI design. The second paper gives an interactive floor planner based on the generic algorithm. The third paper presents a clock router taking the capacitance caused by parallel and cross segments.

Physical Design CAD in Deep Sub-micron Era

T. Mitsuhashi, T. Aoki, M. Murakata, K. Yoshida

EXPLORER: An Interactive Floorplanner for Design Space Exploration

H. Esbensen, E. Kuh

A Practical Clock Router that Accounts for the Capacitance Derived from Parallel and Cross Segments

M. Seki, K. Kato, S. Kobayashi, K. Tsurusaki

Session D-20 ARCHITECTURAL SYNTHESIS TECHNIQUES

Chair: Manfred Glesner, Technische Universität Darmstadt, Germany

This session contains three papers addressing different aspects of architectural synthesis. The first paper presents a combined approach for functional pipelining, component selection and scheduling. The second paper describes a low-power module assignment technique for pipelined design. The last paper uses self- checking as a requirement for scheduling in architectural synthesis.

Component Selection in Resource Shared and Pipelined DSP Applications

S. Bakshi, D. Gajski, H. Juan

Module Assignment for Low Power

J. Chang, M. Pedram

A High-Level Synthesis Approach to Optimum Design of Self-Checking Circuits

A. Antola, V. Piuri, M. Sami

Session D-21 (PANEL) WHEN DO EDA TOOLS HIT THE SUBMICRON WALL?

Chair: Luke Collins, Electronic Times, London, UK

Panelists:
Jean-Marc Chateau, SGS Thomson Microelectronics, Grenoble Cedex, France
Moshe Steiner, Intel Israel Ltd., Haifa, Israel
Jacques Benkoski, EurEPIC, Gieres, France
Franck Poirot, Compass Design Automation, Sophia Antipolis, France

Session D-22 CAD FOR ANALOG CIRCUIT

Chair: Wolfram Glauert, University of Erlangen-Nürnberg, Erlangen, Germany

Since the constraints for analog LSI design are different from digital design, the conventional CAD for digital circuits cannot easily be applied to analog design. There are two papers charanging the difficulties of analog design. The first paper gives analog circuit partitioning dealing with analog specific constraints. The second paper presents and enumerative algorithm generating slicing placements.

Global Stacking for Analog Circuits

B. Arsintescu, S. Spânoche

TINA: Analog Placement Using Enumerative Techniques Capable of Optimizing both Area and Net Length

T. Abthoff, F. Johannes

Session V-01 ANALYSIS TOOLS

Chair: Serafin Olcoz, TGI S.A., Madrid, Spain

The two papers of this session deal with an emergent topic: the analysis and estimation of the quality of VHDL descriptions. Quality covers the areas of testability, reusability, maintainability and portability. The measurements of these features will allow to VHDL designers to move towards and engineering approach to VHDL-based design.

Software Methodologies for VHDL Code Static Analysis based on Flow Graphs

L. Baresi, C. Bolchini, D. Sciuto

A VHDL Reuse Workbench

G. Lehmann, B. Wunder, K. Müller-Glaser

Session V-02 BEYOND VHDL

Chair: Wolfgang Ecker, Siemens AG, München, Germany

Born in 1985 as version 7.2, VHDL should be alive at least until 2015 considering the lifespan of military products. Or is it possible that the other parent of VHDL - namely IEEE, determines the lifespan of VHDL? This and other questions about the future of VHDL should be answered in this session.

Beyond VHDL: Textual Formalisms, Visual Techniques, or Both?

F. Rammig

Object-Oriented Hardware Modelling -Where to apply and what are the objects?

W. Nebel, G. Schumacher

Hardware/Software Partitioning of VHDL System Specifications

P. Eles, Z. Peng, K. Kuchcinski, A. Doboli

Session V-03 (PANEL) WHAT ADVANTAGES CAN WE EXPECT FROM OBJECT ORIENTED EXTENSIONS TO VHDL?

Chair: Jean-Michel Bergé, France Telecom CNET, Meylan Cedex, France

Object Oriented techniques have proven to be successful in software engineering. The temptation is therefore great to apply them to the hardware domain. The current version of VHDL does not support Object Oriented Modeling and several proposals for extending the language in this direction have been published. An IEEE study group has also been created on this topic. This panel will try to answer the question above from both the accademic and user point of views.

Panelists:
David L. Barton, intermetrics, Inc., McLean, VA, USA
Wolfgang Ecker, Siemens AG, München, Germany
Wolfgang Nebel, Carl-von-Ossietzky Universität and OFFIS, Oldenburg, Germany
Serafin Olcoz, TGI, Madrid, Spain
Gregory D. Peterson, Wright Laboratory, WPAFB, OH, USA

Session V-04 FAULT MODELING AND DESIGN FOR TESTABILITY

Chair: Eugenio Villar, University de Cantabria, Santander, Spain

In this session, four papers addressing different aspects regarding the use of VHDL in fault modeling and desing for testability are included. The different techniques proposed aim to evaluate the design testability in the earlier stages of the design process thus reducing the design for testability costs of the whole design process.

BDD-Based Testability Estimation of VHDL Designs

F. Ferrandi, F. Fummi, E. Macii, M. Poncino, D. Sciuto

VHDL Fault Simulation for Defect-Oriented Test and Diagnosis of Digital ICs

F. Celeiro, L. Dias, J. Ferreira, M. Santos, J. Teixeira

Model Generation of Test Logic for Macrocell Based Designs

E. de la Torre, J. Calvo, J. Uceda

A Fault Model for VHDL Descriptions at the Register Transfer Level

T. Riesgo, J. Uceda

Session V-05 FORMAL METHODS

Chair: Werner Damm, Carl von Ossietzky Universität, Oldenburg, Germany

This session groups three complementary approaches towards the formal analysis of VHDL designs. The first paper provides a systematic approach allowing to characterize that subset of VHDL, whose behaviour can be faithfully abstracted to a synchronous finite-state machine. Suppose a design error has been detected, e.g. through model-checking, how do we then locate that part of the circuit responsible for the error ? This question is answered in the second paper of this session w.r.t. a fault-model for gate-level designs claimed to be typical for design errors. Ideally, designs are corrected by construction. A possible set up to systematically develop correct VHDL-code from logical specifications following the refinement paradigm is described in the last paper of this session.

The Maximal VHDL Subset with a Cycle-Level Abstraction

W. Baker, A. Newton

Automatic Diagnosis May Replace Simulation for Correcting Simple Design Errors

A. Wahba, D. Borrione

A Refinement Calculus for VHDL

P. Breuer, C. Delgado-Kloos, N. Martínez-Madrid, A. Marín, Luis Sánchez

Session V-06 MODELING METHODOLOGIES

Chair: Victor Berman, Cadence Design Systems Inc., Chelmsford, MA, USA

Analysis of Different Protocol Description Styles in VHDL for High-Level Synthesis

L. Pirmez, M. Rahmouni, P. Kission, A. Pedroza, A. Mesquita, A. Jerraya

Hardware Synthesis from Requirement Specifications

K. Feyerabend, R. Schlör

Modeling ASIC Memories in VHDL

E. Balaji, P. Krishnamurthy

Stepwise Refinement of Behavioral VHDL Specifications by Separation of Synchronization and Functionality

C. Schneider, W. Ecker

Session V-07 SYNTHESIS

Chair: Ahmed Amine Jerraya, TIMA/INPG, Grenoble Cedex, France

This session deals with three important issues in synthesis with VHDL: Parallel controlled synthesis, timing constraints management, and extending VHDL subsets for synthesis.

Synchronous Parallel Controller Synthesis from Behavioural Multiple-Process VHDL Description

K. Bilinski, E. Dagless, J. Mirkowski

Specification and Management of Timing Constraints in Behavioural VHDL

F. Curatelli, L. Mangeruca, M. Chirico

Towards Maximising the Use of Structural VHDL for Synthesis

K. O'Brien, A. Robert, S. Maginot

Session V-08 SYSTEM LEVEL DESIGN

Chair: Ronald Waxman, University of Virginia, Charlottesville, VA, USA

The underlying theme of this session is the power of VHDL to support many aspects of design at the highest levels of design abstraction. This range is exemplified by three papers. The range covers such diverse areas as asynchronous communication and hardware/software co-design, evaluation of fault tolerance and error detecting mechanisms, and specification modeling coupled with the design process.

Fault Behaviour Observation of a Microprocessor System through a VHDL Simulation-Based Fault Infection Experiment

A.M. Amendola, A. Benso, F. Corno, L. Impagliazzo, P. Marmo, P. Prinetto, M. Rebaudengo, M. Sonza Reorda,

System Design Using an Integrated Specification and Performance Modeling Methodology

A. Sarkar

An Extendable MIPS-I Processor Kernel in VHDL for Hardware/Software Co-Design

M. Gschwind, D. Maurer

Session V-09 VHDL AND MIXED SIGNAL DESIGN

Chair: Alain Vachoux, Swiss Federal Institute of Technology (EPFL), Lausanne, Switzerland

This session begins with an invited paper in the IEEE VHDL 1076.1 standard proposal to extend VHDL to handle analog and mixed-signal systems. At that time, a ballotable language reference manual will be available, The IEEE ballot process is planned to start before the end of year 1996. The second paper proposes interesting guidelines to enhance the usability of VHDL 1076.1 to describe mixed-signal designs. The third paper is more tool oriented as it proposes a new intermediate format able to represent mixed- signal descriptions in a consistent way.

VHDL 1076.1 - Analog and Mixed Signal Extensions to VHDL

E. Christen, K. Bakalar

Entity Overloading for Mixed-Signal Abstraction in VHDL

R. Shi

KIR - A Graph-Based Model for Description of Mixed Analog/ Digital Systems

C. Grimm, K. Waldschmidt

Session V-10 (PANEL) THE OPEN FORUM MODEL

Chair: Victor Berman, Cadence Design Systems Inc., Chelmsford, MA, USA