ABSTRACTS EURO-DAC 96 with EURO-VHDL 96

Session D-01 ANALOG AND MIXED MODE SIMULATION

Chair: Bernhard Klaassen, GMD, Sankt Augustin, Germany

The approaches presented in this session help to combine different levels of simulation: First, a hierarchical methodology for analogue behavioural modelling, followed by an approach combining timing and circuit simulation. The third paper presents a generalized coupling concept for analogue simulation.

A Hierarchical Approach to the Analog Behavioral Modeling of Neural Networks using HDL-A

M. Ahmed, H Ragaie, H. Haddara

A hierarchical methodology for analog behavioral modeling of the basic building blocks of neural networks is presented using HDL-A(1). This hierarchy is formed of three levels in order to satisfy the different requirements of the CAD tools which may incorporate the models. The presented models include all the non idealities present in the actual circuit in addition to being flexible and consuming shorter simulation time. This improvement in simulation time is verified through examples at both the circuit and system levels.

BRASIL: The Braunschweig Mixed-Mode-Simulator for Integrated Circuits

U. Bretthauer, E. Horneber

BRASIL consists of a timing simulator for digital MOS circuits coupled with an algorithm for circuit simulation. The timing simulation is based upon a fast macromodelling approach and the calculation of time-variant RC networks. The circuit simulator takes advantage out of structuring the system of nodal equations. With BRASIL a fast simulation of large circuits, with special regards to systems with the need of higher accuracy, is possible.

Generalized Coupling as a Way to Improve the Convergence in Relaxation-Based Solvers

V. Dmitriev-Zdorov

A new approach capable to improve the convergence of relaxation iterations is presented. The method is based on the use of generalized coupling patterns containing additional circuit elements. The parameters of such elements can freely be varied to control the convergence of iterations by suppressing local feedback in the decomposed circuit. In the case of time-domain circuit analysis by waveform relaxation method the adaptive strategy was formulated based on the dynamic estimation of input impedances of the parts in the decomposed circuit.

Session D-02 LOW POWER SYNTHESIS

Chair: Enrico Macii, Politecnico di Torino, Italy

This session presents two papers on techniques for low power analysis and synthesis. The first paper accounts for temporal and spatial correlations in estimating transition probabilities for sequential circuits. The second paper describes a state assignment technique for achieving low-power FSMs, given the input sequencies.

Power Analysis for Sequential Circuits at Logic Level

M. Senn, P. Schneider, B. Wurth

This paper introduces a novel technique to determine the transition probabilities of internal signals for sequential circuits. We account for temporal correlations of primary inputs and internal signals, sequential correlations, and spatial correlations of internal For this purpose, we exploit and combine concepts of unrolling, reconvergence analysis, decomposing packets of temporally correlated variables, and Markov chains. Experimental results demonstrate the high accuracy and efficiency of our technique.

State Assignment for FSM Low Power Design

M. Koegst, G. Franke, K. Feske

The paper concerns low power design of synchronous FSM and power estimation regarding a given input sequence. A novel and practical approach for state assignment is suggested by means of which the average rate of register switching is reduced. We achieved more realistic power estimates in comparison with the probabilistic approach. Experimental results demonstrate the effectiveness of the proposed approach.

Session D-03 DESIGN EXPERIENCE

Chair: Klaus D. Müller-Glaser, ITIV Universität Karlsruhe, Germany

Experiences in methodologies and tools used for the design of electronic control units in automotive and robotic applications are presented. Issues are specification, system level modelling and simulation, HW/SW tradeoffs, Fuzzy vs. PID-control, analog ASIC design, commercial tool usage.

Specification and Design of Electronic Control Units

J. Bortolazzi, T. Hirth, T. Raith,

Electronic control units (ECU) play a more and more important role in the development of road vehicles. Forecasts lead up to 25% of the total vehicle value in 2000. The increasing complexity and stringent quality and cost requirements mandate tremendous improvements in the specification and design process. This paper presents the cooperative activities at Daimler-Benz research and Mercedes-Benz development departments to install an optimized design process.

Exploration of Hardware/Software Design Space through a Codesign of Robot Arm Controller

M. Abid, A. Changuel, A. Jerraya

This paper deals with exploration of hardware/software design space. The analysis is illustrated using a design of robot arm controller. The controller makes use of an adaptive speed control in real-time. Several architectural solutions will be discussed with regard to their performance and cost. The goal is to select the best solution that satisfies the real-time constraints and minimizes the cost.

Design of an Adaptive Motors Controller Based on Fuzzy Logic Using Behavioural Synthesis

A. Changuel, R. Rolland, A. Jerraya

This paper combines two advanced technologies, High-level synthesis and Fuzzy control, for the design of an adaptive multiple motor speed controller. The obtained solution compares favourably with classic methods in terms of design quality. The use of Fuzzy control allows to implement an original architecture which is faster and smaller then classical solution based on PID. The use of High-level synthesis results in a drastic acceleration of the design process. This paper presents the adaptive motor control application, the Fuzzy control approach and the results of the design using high-level synthesis.

Implementing Fuzzy Control Systems Using VHDL and Statecharts

V. Salapura, V. Hamann

In this paper, we propose an approach for designing fuzzy controllers. To reduce design time, we employ two high-level design methods: VHDL and VHDL-based logic synthesis, and Statecharts with a VHDL backend for graphical design description. A fuzzifier and a defuzzifier parts of a fuzzy control system are captured in VHDL, as these parts perform complex arithmetical operations. A rule base of the controller is described in Statecharts, and then is translated into VHDL. A complete description of the system is assembled in VHDL, and is synthesized using VHDL-based logic synthesis. The efficiency of the generated hardware is explored for FPGA technology.

A Top Down Mixed-Signal Design Methodology Using a Mixed-Signal Simulator and Analog HDL

T. Murayama, Y. Gendai

We have applied a mixed-signal simulator and AHDL to the top-down design of industrial ICs. We report the design process from the system-level down to gate/transistor-level modeling and simulation applied to a real circuit. We have verified the robustness and effectiveness of our approach which resulted in shorter design process cycles and higher rates of success.

Session D-04 TIMING MODELING

Chair: Jacques Benkoski, EurEPIC Sarl, Gïres, France

This session covers the evolving nature of the timing problems; what were previously second order effects such as glitches and interconnect must now be modeled. Asynchronous designs are also becoming more common and their timing problems mus be addressed as well.

New Approach in Gate-Level Glitch Modelling

D. Rabe, W. Nebel

An enhanced gate-level glitch model for logic simulation is presented. This new approach can be used to enhance logic simulation accuracy and power estimation at little additional computation costs. The simulation algorithm is compatible with common event driven simulation models for glitch-free cases. Only if a possible glitch is detected the simulation is modified by our model. The model is based on common timing characterization data and a few additional constant values. The features of the model are enhanced scheduling of glitch events and prediction of glitch peak voltages, which are essential for precise power estimation.

A New Concept for Accurate Modeling of VLSI Interconnections and its Application for Timing Simulation

B. Wunder, G. Lehmann, K. Müller-Glaser

This paper presents a new concept for accurate modeling the timing behavior of VLSI interconnections using frequency domain methods and taking into consideration distributed parasitics as well as lumped elements and contact holes. A piecewise linear signal representation is used to catch the waveform dependencies of submicron structures. The models are applied in an analysis tool for clock trees and in a concept for accurate post-layout timing simulation.

Timing Verification for Asynchronous Design

R. Davies, J. Woods

This paper describes a technique for verifying timing conditions inherent in self-timed VLSI designs that make use of the micropipeline design strategy. By checking bundling constraints during simulations, design faults may be detected, whilst timing information extracted during the processing may be used to identify modules requiring optimisation. These analyses may be built around existing simulators.

Session D-05 DESIGN FLOW AND DESIGN MANAGEMENT

Chair: Ralph H.J.M. Otten, Delft University of Technology, The Netherlands

Starting from a novel approach for designing and implementing controllers targetted for structured data processing, design flows, design flow data management, design flow planning and control and design flow generation is discussed.

A System for Compiling and Debugging Structured Data Processing Controllers

A. Seawright, U. Holtmann, W. Meyer, B. Pangrle, R. Verbrugghe, J. Buck

This paper describes a system for designing and implementing controllers for structured data processing. A graphical input style describes the format of the data to be processed along with the necessary control actions. Advantages over FSM approaches include: 1) ease of design changes, 2) ease of debugging, and 3) a shorter design cycle.

A Graphical Data Management System for HDL-Based ASIC Design Projects

C. Mayer, H. Sahm, J. Pleickhardt

Efficient and secure project data management is a key requirement for todays HDL ASIC design projects. This paper introduces a RCS-based data management system, which focuses on the requirements of ASIC project teams. The project- and the user’s working directories are strictly separated, data transfer is explicitly triggered by checking-in or checking-out files. There are cumulative check-out operations available that consider hierarchical and logical dependencies between the files and generate script files for further data processing. The directory structures are configurable and transparent to the users, no proprietary or binary configuration files are involved. The entire data management functionality is accessible on command level as well as from a graphical user interface, which also serves as a convenient interface to third party tools.

An Integrated Concept for Design Project Planning and Design Flow Control

M. Ryba, U. Baitinger

This paper presents a novel approach supporting administrative tasks within the lifecycle of design projects. Based upon comprehensive models of design environments and design activities it combines techniques known from project management and mechanisms for design flow control. As a result it allows the planning, controlling and reviewing of design projects and supports algorithmic estimation of task durations and automatic computation of plan revisions.

Automatic Workflow Generation

V. Shepelev, S. Director

As the number and diversity of computer-aided VLSI design tools grows, there is an increasing interest in workflow management. In this paper we describe an enhancement to the task schema approach to workflow management that allows for the automatic generation of workflows. Such a capability can significantly enhance designer productivity. It has been implemented in the Dedal program.

Session D-06 (PANEL) WHAT'S HOT IN LOW POWER DESIGN?

Chair: Enrico Macii, Politecnico di Torino, Italy

For today's electronic devices low-power dissipation is desirable, and for some special applications, power consumption is a critical issue. An integrated framework for low power design of digital systems must provide the user with tools for low power synthesis at different levels of abstractions; in particular, low power consumption needs to be targeted at the system, architectural, logic and physical levels. Besides synthesis algorithms, the availability of tools for accurately estimating power consumption of systems at different stages of the design process is essential. This panel will investigate the progress that has been made in this area in the last few years. Both the academic and the industrial point of views will be illustrated and discussed by designers and scientists active in this field.

Panelists:
Jordi Cortadella, Universidad Politecnica Catalunya, Barcelona, Spain
Giovanni de Micheli, Stanford University, CA, USA
Massoud Pedram, University of Southern California, Los Angeles, CA, USA
Jan Rabaey, University of California at Berkeley, CA, USA
Rob Roy, NEC C&C Research Laboratory, Princeton, NJ, USA
Kees van Berkel, Philips Research Laboratories, Eindhoven, The Netherlands

Session D-07 PARTITIONING

Chair: Klaus Buchenrieder, Siemens AG, München, Germany

This session is introduced with an invited talk which gives a comprehensive overview of the state of the art in HW/SW partitioning. After that, two research papers present partitioning approaches based on combinatorial optimization methods.

Synthesis from Mixed Specifications

V. Mooney, C. Coelho, T. Sakamoto, G. de Micheli

We present a hardware synthesis system that accepts system-level specifications in both Verilog HDL and C. A synchronous semantics is assumed for both languages in order to guarantee a uniform underlying model. The rationale for mixed input specifications is to support hardware/software co-design by allowing the migration to hardware of system modules originally described in the C language. We discuss assumptions and limitations of the input description style, a high-level synthesis system, and the application of such a system to some design examples.

A System Level HW/SW Partitioning and Optimization Tool

M. Schwiegershausen, H. Kropp, P. Pirsch

This paper presents a system level HW/SW partitoning methodology and its implementation as CAD tool for the optimization of heterogeneous multiprocessor systems. Starting from modelling of the signal processing scheme and of the available processor resources, performance and expense measures are estimated for a finite set of processor modules. Based on these measurements, a numerical optimization can be carried out by using mixed integer linear programming as mathematical framework, leading to a heterogeneous system, which is optimal in terms of area expense and throughput rate.

A New HW/SW Partitioning Algorithm for Synthesizing the Highest Performance Pipelined ASIPs with Multiple Identical FUs

M. Imai, N. Binh, A. Shiomi

This paper introduces a new HW/SW partitioning algorithm for automatic synthesis of a pipelined CPU architecture with multiple identical functional units (MIFUs) of each type in designing ASIPs (Application Specific Integrated Processors). The partitioning problem is formalized as a combinatorial optimization problem that partitions the operations into hardware and software so that the performance of the designed ASIP is maximized under given gate count and power consumption constraints, regarding the optimal selection of needed FUs of each type. A branch-and-bound algorithm with proposed lower bound function is used to solve the formalized problem. The experimental results show that the proposed algorithm is found to be effective and efficient.

Session D-08 LOGIC AND FSM SYNTHESIS

Chair: Utz Baitinger, IPVR Universität Stuttgart, Germany

The first paper incorporates sequential optimization into hierarchical synthesis. The second one describes a controller synthesis technique from regular expressions describing protocol-intensive applications. The third paper combines both behavioural and spectral domains in boolean matching for technology mapping.

Automatic Structuring and Optimization of Hierarchical Designs

H. Eikerling, W. Rosenstiel

In this paper an approach for the optimization of digital synchronous designs is described. The optimization is done for smaller components which are the result of a partitioning process. The actual optimization is done on a graph which reflects the communication structure between the modules. Sequential don'’t care conditions are extracted and used for sequential optimization. As experimental results show, the robustness of the subsequent logic synthesis methods can be increased while achieving a significant gain in cost and power consumption. This is shown by applying the described methods to a set of benchmarks obtained from high-level synthesis.

Controller Optimization for Protocol Intensive Applications

A. Crews, F. Brewer

Applications implementing complex protocols tax the capabilities of conventional finite state machine synthesis techniques. In this paper, we present sequential optimization techniques whose complexity scales with the number of state bits rather than the number of states. These techniques create designs which are comparable or superior to those synthesized by conventional state-based optimization and assignment. Furthermore, they provide viable synthesis techniques for designs which are too large for synthesis with the conventional method.

Library Based Technology Mapping Using Multiple Domain Representations

J. Bullmann, E. Schubert, U. Kebschull, W. Rosenstiel

The use of signatures as efficient filters in boolean matching is a crucial step in technology mapping and/or formal verification. In this work we combine well known representations of boolean functions, the binary decision diagrams, with those in the spectral domain, the functional decision diagrams and the equivalence decision diagrams. We obtain signatures of Boolean functions and their variables, which are easy to compute but can reduce the problem of aliases through.

Session D-09 BDD OPTIMIZATION TECHNIQUES

Chair: Hans Eveking, Technische Universität Darmstadt, Germany

Two papers introduce compilation techniques and a new calculation method for boolean operations on OBDDs. In addition, decomposition and re-encoding procedures for the OBDD-based symbolic traversal of FSMs are presented.

Compilation of Optimized OBDD-Algorithms

S. Höreth

According to Bryant there exist basically two OBDD construction methods, namely Apply- and Compose- based approaches. In this paper we describe a compilation method that generates an optimized Apply-based OBDD-algorithm from a given combinational circuit description. The method is particularly useful in library-based synthesis- and verification environments. We also present a concise, machine independent measure for the efficiency of OBDD-construction methods. Experiments with our new method indicate a speedup of up to a factor 19 in the construction time for OBDDs while the maximum memory requirements are typically slightly smaller in comparison to conventional approaches.

Incremental Re-encoding for Symbolic Traversal of Product Machines

S. Quer, G. Cabodi, P. Camurati, L. Lavagno, E. Sentovich, R. Brayton

State space exploration of finite state machines is used to prove properties. The three paradigms for exploring reachable states, forward traversal, backward traversal and a combination of the two, reach their limits on large practical examples. Approximate techniques and combinational verification are far less expensive but these imply sufficient, not strictly necessary conditions. Extending the applicability of the purely combinational check can be achieved through state minimization, partitioning, and re-encoding the FSMs to factor out their differences. This paper focuses on re-encoding presenting an incremental approach to re-encoding for sequential verification. Experimental results demonstrate the effectiveness of this solution on medium-large circuits where other techniques may fail.

MORE: An Alternative Implementation of BDD Packages by Multi-Operand Synthesis

A. Hett, R. Drechsler, B. Becker

In this paper we present a new approach for the realization of a BDD package. This approach does not depend on recursive synthesis operations, i.e. the ternary If-Then-Else-operator (ITE), to perform manipulations of Boolean functions; instead our basic operation MORE is based on exchanges of neighbouring variables and existential quantification. It is capable of combining an arbitrary number of Boolean functions in parallel. We discuss the difference between MORE and ITE and give experimental results to show the advantages of our implementation approach with respect to size and runtime.

Decomposed Symbolic Forward Traversals of Large Finite State Machines

S. Quer, G. Cabodi, P. Camurati

BDD-based symbolic traversals are the state-of-the-art technique for reachability analysis of Finite State Machines. They are currently limited to medium-small circuits for two reasons: BDD peak size during image computation and BDD explosion for state space representation. Starting from these limits, this paper presents a technique that decomposes the search space decreasing the BDD peak size and the number of page faults during image computation. Results of intermediate computations and large BDDs are efficiently stored in the secondary memory. A decomposed traversal that allows exact explorations of state spaces is obtained. Experimental results show that this approach is particularly effective on the larger MCNC, ISCAS'89, and ISCAS'89-addendum circuits.

Session D-10 CODESIGN METHODOLOGY AND COSPECIFICATION

Chair: Klaus D. Müller-Glaser, ITIV Universität Karlsruhe, Germany

This session presents three papers on codesign approaches based on different specification formalisms. The first paper uses a combination of C, VHDL and a rules file, the second paper employs extended Statecharts, and the last paper is based on annotated task graphs.

COMET: A Hardware-Software Codesign Methodology

M. Knieser, C. Papachristou

COMET is a system-level C and VHDL hardware/software codesign methodology. This process is made possible through the use of a rules file which adds timing and area constraints to the C and VHDL descriptions that the languages do not support. The methodology of COMET is functional and has been tested. A neural network program has been implemented to perform automated hardware/software partitioning.

Mapping Statechart Models onto an FPGA-Based ASIP Architecture

K. Buchenrieder, A. Pyttel, C. Veith

In this paper, we describe a system to map hardware-software systems specified with statechart models on an ASIP architecture based on FPGAs. The architecture consists of a reusable CPU core with enhancements to execute the behavior of statecharts correctly. Our codesign system generates an application-specific hardware control block, an application-specific set of registers, and an instruction stream. The instruction stream consists of a static set of core instructions, and a set of custom instructions for performance enhancements. In contrast to previous approaches, the presented method supports extended statecharts. The system also assists designers during space/time tradeoff optimizations. The benefits of the approach are demonstrated with an industrial control application comparing two different timing schemes.

MILP Based Task Mapping for Heterogeneous Multiprocessor System

A. Bender

CAD-systems supporting hardware/software codesign map different tasks of an algorithm onto processors. Some of the processors are programmable and others are application specific. We propose a new MILP (mixed integer linear program) model that allows to determine a mapping optimizing a trade off function between execution time, processor and communication cost. The mapping also guarantees that all specified execution deadlines are met. We demonstrate the efficiency with practical examples.

Session D-11 SYSTEM LEVEL DESIGN AND SYNTHESIS

Chair: Giovanni de Micheli, Stanford University, CA, USA

This session addresses system design issues for software and hardware. The first paper describes a technique for instruction set selection that can improve code quality for embedded DSPs. The second paper presents a system-level performance estimation technique that accounts for memories and pipelined functional units. The last paper introduces packaging constraints into the system synthesis process by presenting a hierarchical behavioural partitioning algorithm.

Instruction Selection for Embedded DSPs with Complex Instructions

R. Leupers, P. Marwedel

We address the problem of instruction selection in code generation for embedded digital signal processors. Recent work has shown that this task can be efficiently solved by tree covering with dynamic programming, even in combination with the task of register allocation. However, performing instruction selection by tree covering only does not exploit available instruction-level parallelism, for instance in form of multiply-accumulate instructions or parallel data moves. In this paper we investigate how such complex instructions may affect detection of optimal tree covers, and we present a two-phase scheme for instruction selection which exploits available instruction-level parallelism. At the expense of higher compilation time, this technique may significantly increase the code quality compared to previous work, which is demonstrated for a widespread DSP.

Rapid Performance Estimation for System Design

S. Narayan, D. Gajski

The ability to gauge the effect of any design decision on system performance is important in the design process. Given a behavioral description and the functional-unit allocation, we describe a method for rapidly estimating the number of control steps required to implement the design. Extensions for pipelined functional units and multiport memory accesses are also presented. Using flow-analysis, we then show how process execution times and related performance metrics can be computed to aid design space exploration.

Hierarchical Behavioral Partitioning for Multicomponent Synthesis

N. Kumar, , V. Srinivasan, R. Vemuri

Packaging technology has tremendously improved over the last decade. Various packaging options such as ASICs, MCMs, boards, etc. should be well explored at early stages of the system-synthesis cycle. In this paper we present a hierarchical behavioral partitioning algorithm which partitions the input behavioral specificcation into a hierarchical structure and binds all elements of the structure to appropriate packages from a given package library. As an application to our partitioner, we integrated the partitioner with a high level synthesis tool to create an environment for multicomponent synthesis and hierarchical package design. We provide detailed partitioning algorithms and experimental results.

Session D-12 NEW ASPECTS ON TESTING

Chair: Wilfried Daehn, SICAN GmbH, Hannover, Germany

This session addresses path delay fault testability, weighted random pattern testing, BIST, and the testable design of SC circuits.

Testable Path Delay Fault Cover for Sequential Circuits

A. Krstic, K. Cheng, S. Chakradhar

We present an algorithm for identifying a set of faults that do not have to be targeted by a sequential delay fault test generator. These faults either cannot independently affect the performance of the circuit or no test can be generated for them. To find such faults, our methodology takes advantage of the sequential behavior of the circuit as well as of the information about uncontrollable signals in the sequential circuit. It can handle sequential circuits described as two- or multi-level netlists. The outcome of applying our methodology is smaller fault set and possibly smaller test set. We present experimental results on several ISCAS 89 benchmark circuits demonstrating that a large number of path delay faults in these circuits either cannot or does not have to be examined for delay defects.

Efficient Random Testing with Global Weights

A. Kunzmann

This paper describes a new and highly efficient approach for weighted random pattern generation. In contrast to the state-of-the-art approaches, where input specific weights are computed, the proposed method is based on the computation of global weights. This set of a very few weights (e.g., 4 or 8) is pattern oriented and therefore, with each weight the generation of the related random patterns is uniquely specified. Starting with a deterministic test pattern set and the inherent pattern specific weights, columns or rows can be inverted such that the initial weights are maximized in order to minimize the number of random patterns. Our experiments with the prototype system POWER-TEST (Pattern Oriented WEighted Random TESTing) show that very high fault coverage can be achieved with low computation and implementation effort at low self-test hardware costs.

Fault Tolerant and BIST Design of a FIFO Cell

F. Corno, P. Prinetto, M. Reorda

This paper presents a BIST design of a parametrized FIFO component. The component is currently being used in the standard library of Italtel, the main Italian telecom circuit maker. Design choices have been strongly influenced by industrial constraints imposed by the Italtel design flow. To achieve the desired fault coverage level for faults in the memory and in the control logic, traditional BIST schemes had to be combined with more advanced testing techniques. Different parts of the circuits are tested with different strategies and algorithms to account for their different nature: critical parts of the design, such as the FIFO control unit and the BIST controller, are tested with on-line test techniques. The final implementation shows that a high fault coverage is attained with an acceptable area overhead and no speed penalty.

A Digital Method for Testing Embedded Switched Capacitor Filters

M. Robson, G. Russell

The ever increasing integration of analogue and digital functions on the same IC has increased enormously the problem of testing these complex circuits. Many analogue functions are implemented using switched capacitor techniques whose inputs and outputs may be difficult to access. This paper describes a built in test technique for testing embedded SC filters. The technique proposed is called M–sequence testing and has the advantage that much of the test hardware required can be realised from registers in the digital part of the circuit.

Session D-13 CODESIGN METHODOLOGY AND COSIMULATION

Chair: Ahmed Amine Jerraya, TIMA/INPG, Grenoble Cedex, France

This session combines a paper on the cosimulation of mechatronic systems and three papers on codesign methodology. In the papers on methodology emphasis is given to design reuse aspects, life-cycle aspects, and the role of simulation in Hardware/Software Codesign.

Hardware/Software-Cosimulation for Mechatronic System Design

G. Pelz, J. Bielefeld, G. Hess, G. Zimmer

This paper is about a new electro-mechanical modeling paradigm based on hardware description languages which paves the way to mechatronical HW/SW-Cosimulation. The strategy is illustrated by an example from automotive system design: a processor-controlled wheel suspension following BMW's electronic damper control. Its suitability in function and performance is shown by system simulation.

CoWare - A Design Environment for Heterogeneous Hardware/Software Systems

K. Van Rompaey, D. Verkest, I. Bolsens, H. De Man

In this paper the design problems encountered when designing heterogeneous systems are studied and solutions to these problems are proposed. It will be shown why a single heterogeneous specification method ranging from concept to architecture is required and why it should cover issues as modularity, design for reuse, reuse of designs and reuse of design environments. A heterogeneous system design environment based on co-specification, co-simulation and co-synthesis is proposed and its application is illustrated by means of a spread spectrum based pager system.

An Approach for Integrated Specification and Design of Real-Time Systems

Y. Tanurhan, S. Schmerler, H. Gölz, K. Müller-Glaser

In this paper, a design methodology for the design of microelectronic systems which includes hardware and software for open-loop and closed-loop control will be presented. An integrated approach to specification and design, analysis and simulation of the overall system has been developed. This provides for a systematic, computer aided approach to requirements definition, specification and design as well as verification and validation of the results. As embedded systems often require real-time capabilities, the environment presented gives special consideration to these constraints. We give an example for concrete applications, which shows, how the design of real-time embedded systems is supported by the design methodology and environment.

An Integrated Approach to Engineering Computer Systems

D. Morris, D. Gareth Evans, P. Green

This paper describes MOOSE a full-lifecycle, model-based approach to the engineering of computer systems. It describes how early lifecycle models that represent the logical behaviour and architecture of a system can be transformed into representations that allow implementation source for both hardware and software to be synthesised.

Session D-14 (Joint Panel EURO-DAC and EURO-VHDL) WHICH FORMAL VERIFICATION TECHNIQUE IS MORE APPLICABLE IN INDUSTRY TODAY - EQUIVALENCE CHECKING OR PROPERTY CHECKING?

Chair: Luc Claesen, IMEC, Leuven, Belgium

Growing system integration and complexity currently require extreme attention towards design correctness. Formal verification methods have evolved over the last few year into industrial application. This panel will explore the potentials and difficulties for industrial adoption of formal verification in design flows.

Panelists:
Pierre Ragon, Philips TRT Communication Systems, Le Plessis Robinson, France
Michael Payer, Siemens, Muenchen, Germany
Frederic Rocheteau, SGS Thomson INMOS Ltd., Almondsbury, UK
Simon Read, COMPASS Design Automation, Rochester, MN, USA
Dominique Borrione, TIMA/INPG, Grenoble Cedex, France
Gerry Musgrave, Abstract Hardware Ltd. and Brunel University of West London, Uxbridge, UK

Session D-15 KEY TECHNOLOGIES AND CAD OF MICROSYSTEMS

Chair: Karl-Heinz Diener, Fraunhofer Gesellschaft - Institut für Integrierte Schaltungen, Dresden, Germany

The microsystem technology opens new ways for the integration of different sensors and actuators together with electronic components (mostly for information processing) on silicon. The inherent integration process is aimed at setting up flexible, adaptive, and intelligent systems intended to be applied to new products. The design of Microsystems requires to become familiar with both the dedicated technology for production and also the sophisticated CAD tools and systems. The goal of this session is to inform on what is feasible with key technologies for Microsystems, and how to design microsystems. That will be presented by two invited talks based on several examples of latest applications .

Spotlights on Recent Developments in Microsystem Technology

S. Büttgenbach

Microsystem technology introduces a new way of integration of sensors, actuators, and information processing components resulting in flexible, adaptive, and intelligent systems similar to those created by nature. This paper attempts to give a general idea of what is feasible with this technology. After a short introduction the key technologies for the fabrication of microsystems are described and illustrated by several examples of present-day applications.

CAD of Microsystems - A Challenge for Systems Engineering

K. Müller-Glaser

Designing, verifying and testing microsystems and microsystem-components will not be feasible without the intensive use of design methodologies and supporting computer aided design tools. Requirements Engineering at the beginning of a top down design flow results in formal specifications for the desired system and component behavior and a list of design constraints. These are the basis for documentation as well as for modeling, system simulation, parameterized component design and hardware/ software-codesign. Finite Element Analysis and simulations on various levels of abstraction are necessary to characterize parameterized functions (e.g. sensors and actuators built on different microtechnologies and materials) and generate macromodels in a bottom up design flow to verify each design step for component integration, system integration, packaging and interconnects, especially dealing with parasitics and cross sensitivities.

Session D-16 ASYNCHRONOUS SYNTHESIS AND STORAGE OPTIMIZATION

Chair: Jordi Cortadella, Universidad Politecnica Catalunya, Barcelona, Spain

This session contains two regular papers on asynchronous circuit synthesis and two short papers on techniques for storage optimization at the RT/logic and the behavioral level.

A Heuristic Covering Technique for Optimizing Average-Case Delay in the Technology Mapping of Asynchronous Burst-Mode Circuits

P. Beerel, K. Yun, W. Chou

This paper presents a covering technique for optimizing the average-case delay of asynchronous burst-mode control circuits during technology mapping. The specification and NAND-decomposed unmapped network of these circuits are first preprocessed using stochastic techniques to determine the relative frequency of occurrence of each state transition and the corresponding sensitized paths through the NAND-decomposed network. We minimize the sum of the implementation's cycle times of the state transitions, weighted by their relative frequencies, thereby optimizing for average-case performance. Our results demonstrate that a 10-15% improvement in performance can be achieved with run-times comparable to synchronous techniques.

Automatic Synthesis of Extended Burst-Mode Circuits Using Generalized C-Elements

K. Yun

This paper presents a new automatic synthesis technique for extended burst-mode circuits, a class of asynchronous circuits that allow multiple-input changes between state transitions and a choice of next states based on input signal levels. The target implementation is a pseudo-static asymmetric CMOS complex gate per each output, known as generalized C-element [3,12]. The synthesis algorithm generates hazard-free covers for set and reset functions of each output using Nowick and Dill's exact hazard-free logic minimization algorithm [14]. Each output circuit is formed by mapping its set and reset logic to N and P stacks of an asymmetric CMOS gate connected to a sustainer; long series stacks are decomposed into static gates followed by short stacks. A simple heuristic is used to ensure that no short circuit paths exist from Vdd to ground. The resulting circuits for small-to-medium size extended burst-mode specifications are 40% smaller and 30% faster than two-level circuits generated by the 3D synthesis tool [19] and significantly smaller and faster than complex-gate circuits generated by the method of Kudva et al [9].

Storage Optimization by Replacing Some Flip-Flops with Latches

T. Wu, Y. Lin

Conventionally, when a synchronous sequential circuit is synthesized, storage units are implemented in either edge-triggered flip-flops or level-sensitive latches, but not both, depending on the clocking scheme (one- or two-phase) used. We propose that, in the former case, some of the flip-flops can be replaced with latches. Since a latch is generally smaller, faster and less power-consuming than a flip-flop, this replacement leads to improvements in circuit area, performance and power consumption. Whether a flip-flop can be replaced with a latch depends on not only its structural context but also its temporal behavior. In this paper, we first present conditions under which a straightforward replacement can be made; then, we propose two retiming-based transformations that increase the number of replaceable flip-flops. We have implemented the proposed idea in a software called FF2Latch. Experimental results on a set of control-dominated circuits from the high-level synthesis benchmark set [1] show that a large number of the flip-flops can be replaced with latches. Up to 22% reduction in the circuit area and up to 73% reduction in the power consumption have been achieved.

Assignment of Storage Values to Sequential Read-Write Memories

S. Gerez, E. Woutersen

Sequential read-write memories (SRWMs) are RAMs without an address decoder. A shift register is used instead to point at subsequent memory locations. SRWMs consume less power than RAMs of the same size. Algorithms are presented to check whether a set of storage values fits in a single SRWM and to automatically map storage values in as few SRWMs as possible. Benchmark results show that good assignments can be obtained in spite of the limited addressing capabilities.

Session D-17 MODELLING, SIMULATION OF MICROSYSTEMS AND MULTI LAYER ROUTING IN PCBS

Chair: Wolfgang Nebel, Carl-von-Ossietzky-Universität and OFFIS, Oldenburg, Germany

Because of their multi-disciplinary nature, the design of microsystems requires the using of CAD tools and systems. Modelling and simulation seem to be the crucial steps to coming up with right first designs. Two papers are addressed to that problem. Generally, the system integration realized by microsystems on silicon and PCBs, respectively, demands to pay most attention to achieving acceptable solutions of wiring the components necessary for creating systems. This problem will be tackled in the session, too.

Estimation of the Number of Routing Layers and Total Wirelength in a PCB through Wiring Distribution Analysis

I. Hom, J. Granacki

This paper describes a model to estimate the number of routing layers and total wirelength for a printed circuit board given the netlist, partslist, placement and board form factor. The estimation model is based on analysis of the wiring distribution on the board. The wiring distribution consists of the net distribution and net segmentation. An algorithm is presented which determines the contribution of net distribution. A statistical model has been developed to estimate net segmentation as “wrong way” routes due to obstacles and congestion on a board. Routability estimations are substituted for the routing task while searching the design space, significantly reducing the design time since routing is the most time consuming design task. These estimation techniques have been successfully applied to the board estimations of several designs, including a multiprocessor printed circuit board and the results are presented here.

Describing Space-Continuous Models of Microelectromechanical Devices for Behavioural Simulation

Z. Mrcarica, D. Glozic, V. Litovski, H. Detter

Modern behavioural simulators and their hardware description languages enable description of time-continuous and time-discrete models. In this work, a modelling technique is developed for description of space-continuous models, where partial differential equations are used. A hierarchical library of partial differential equations and boundary conditions for microelectromechanical device modelling is created. Mechanically complex devices have been modelled for system-level simulation using this technique.

Simulation and Design Optimization of Microsystems Based on Standard Simulators and Adaptive Search Techniques

S. Meinzer, A. Quinte, M. Gorges-Schleuter, W. Jakob, W. SüB, H. Eggert

The concept of a partial automated design optimization and the improvement of a micropump as a first application is described. Starting with a parametrizable simulation model the parameter values are modified with evolutionary algorithms until the simulation results which describe the behaviour of the system satisfy the defined goals. As the quality of the optimization depends strongly on the quality of the simulation model we give an outlook on a concept for improving the simulation model or components of this model by using FEM-simulation results.

Session D-18 TIMING ISSUES IN SYNTHESIS

Chair: Kurt J. Antreich, TU Muenchen, Germany

This session contains papers describing issues at the behavioural, RTL and logic levels. The first paper describes a clock optimization technique for pipelined implementations of design behaviours. The second paper addresses the problem of false paths in delay estimation at the RT-level. The third paper describes a timing optimization technique at the logic level that employs improved redundancy addition and removal.

Clock Optimization for High-Performance Pipelined Design

H. Juan, D. Gajski, S. Bakshi

In order to reduce the design cost of pipelined systems, resources may be shared by operations within and across different pipe stages. In order to maximize resource sharing, a crucial decision is the selection of a clock period, since a bad choice can adversely affect the performance and cost of the design. In this paper, we present an algorithm to select a clock period that attempts to minimize design area while satisfying a given throughput constraint. Experimental results on several examples demonstrate the quality of our selection algorithm and the benefit of allowing resource sharing across pipe stages.

False Path Exclusion in Delay Analysis of RTL-Based Datapath-Controller Designs

M. Nourani, C. Papachristou

In this paper, we present an accurate delay estimation algorithm at the register transfer level. We introduce "resource binding" as an important source of false paths in a register transfer level structure. "Path mismatching" between two path segments may create another type of false paths when the datapath and controller interact. The existence and creation of such paths and their effect in delay analysis are discussed. We also introduce the Propagation Delay Graph (PDG), whose traversal, for delay analysis, is equivalent to the traversal of sensitizable paths in the datapath.

Timing Optimization by an Improved Redundancy Addition and Removal Technique

L. Entrena , J. Espejo, E. Olías, J. Uceda

Redundancy Addition and Removal (RAR) uses Automatic Test Pattern Generation (ATPG) techniques to identify logic optimization transforms. It has been applied successfully to combinational and sequential logic optimization and to layout-driven logic synthesis for FPGAs. In this paper we present an improved RAR technique that allows to identify new types of optimization transforms and it is more efficient because it reduces the number of ATPG runs required. Also, we apply the RAR method to timing optimization. The experimental results show that this improved RAR technique produces significant timing optimization with very little area cost.

Session D-19 PHYSICAL DESIGN FOR DEEP SUBMICRON

Chair: Tokinori Kozawa, Semiconductor Technology Academic Research Center, Tokyo, Japan

There are many restrictions to design sub-micron LSI. To solve this difficulties designer expect to have good tradeoffs by generic methods. An invited paper reviews the problem of deep submicron LSI design. The second paper gives an interactive floor planner based on the generic algorithm. The third paper presents a clock router taking the capacitance caused by parallel and cross segments.

Physical Design CAD in Deep Sub-micron Era

T. Mitsuhashi, T. Aoki, M. Murakata, K. Yoshida

In this paper, we will investigate the impacts of miniaturization of device dimensions that causes a paradigm shift in LSI design methodology. Major design issues in deep sub-micron LSIs, namely, wire delay, circuit complexity and power consumption will be discussed based on scaling theory. To resolve these issues, a concept called Layout Driven Synthesis and Optimization is introduced. Based on this concept, EDA programs including circuit optimizer, clock tree synthesis, technology mappers and so on, have been developed. Timing optimization and power minimization methods using the concept will be discussed in detail. Evaluation results obtained by proposed approach show superior performance and dramatic reduction of design period, and indicate validity of layout driven synthesis and optimization concept.

EXPLORER: An Interactive Floorplanner for Design Space Exploration

H. Esbensen, E. Kuh

An interactive floorplanner based on the genetic algorithm is presented. Layout area, aspect ratio, routing congestion and maximum path delay are optimized simultaneously. The design requirements are refined interactively as knowledge of the obtainable cost tradeoffs is gained and a set of feasible solutions representing alternative, good tradeoffs is generated. Experimental results illustrates the special features of the approach.

A Practical Clock Router that Accounts for the Capacitance Derived from Parallel and Cross Segments

M. Seki, K. Kato, S. Kobayashi, K. Tsurusaki

We propose a practical clock router that takes the capacitance caused by parallel and cross segments into account. In a conventional clock router that doesn't consider this capacitance, clock skew calculated by SPICE after layout was 220-650ps, which was 20-100 times greater than the reported skew of the router. In our router, skew in SPICE was reduced to 20-240 ps and only 2-4 times greater than our router's report.

Session D-20 ARCHITECTURAL SYNTHESIS TECHNIQUES

Chair: Manfred Glesner, Technische Universität Darmstadt, Germany

This session contains three papers addressing different aspects of architectural synthesis. The first paper presents a combined approach for functional pipelining, component selection and scheduling. The second paper describes a low-power module assignment technique for pipelined design. The last paper uses self- checking as a requirement for scheduling in architectural synthesis.

Component Selection in Resource Shared and Pipelined DSP Applications

S. Bakshi, D. Gajski, H. Juan

In general, high-performance DSP designs are heavily pipelined and, in order t o reduce the pipeline cost, these designs employ techniques such as component selection and resource sharing to select the appropriate number and type of components. In this paper, we present an algorithm to perform the three tasks of pipelining, resource sharing and component selection, so as to minimize design cost for a given throughput constraint. Experiments conducted on several examples demonstrate the superiority of performing all three tasks, rather than just a combination of any two of these tasks, as done in previously published algorithms.

Module Assignment for Low Power

J. Chang, M. Pedram

In this paper, we investigate the problem of minimizing the total power consumption during the binding of operations to functional units in a scheduled data path with functional pipelining and conditional branching for data intensive applications. We first present a technique to estimate the power consumption in a functionally pipelined data path and then formulate the power optimization problem as a max-cost multi-commodity flow problem and solve it optimally. Our proposed method can augment most high-level synthesis algorithms as a post-processing step for reducing power after the optimizations for area or speed have been completed. An average power savings of 28% has been observed after we apply our method to pipelined designs that have been optimized using conventional techniques.

A High-Level Synthesis Approach to Optimum Design of Self-Checking Circuits

A. Antola, V. Piuri, M. Sami

We present an innovative solution to design of self-checking systems implementing arithmetic algorithms. Rather than substituting self-checking units in system synthesized independently of self-checking requirements, we introduce self-checking in high-level synthesis as a requirement already for scheduling the DFG. Rules granting error detection allow optimum partitioning of the DFG; minimum-latency, resource-constrained scheduling is performed with the support of such partitioning so as to optimize the number of checkers as well as that of other resources.

Session D-21 (PANEL) WHEN DO EDA TOOLS HIT THE SUBMICRON WALL?

Chair: Luke Collins, Electronic Times, London, UK

Panelists:
Jean-Marc Chateau, SGS Thomson Microelectronics, Grenoble Cedex, France
Moshe Steiner, Intel Israel Ltd., Haifa, Israel
Jacques Benkoski, EurEPIC, Gieres, France
Franck Poirot, Compass Design Automation, Sophia Antipolis, France

Session D-22 CAD FOR ANALOG CIRCUIT

Chair: Wolfram Glauert, University of Erlangen-Nürnberg, Erlangen, Germany

Since the constraints for analog LSI design are different from digital design, the conventional CAD for digital circuits cannot easily be applied to analog design. There are two papers charanging the difficulties of analog design. The first paper gives analog circuit partitioning dealing with analog specific constraints. The second paper presents and enumerative algorithm generating slicing placements.

Global Stacking for Analog Circuits

B. Arsintescu, S. Spânoche

A flexible and efficient method for analog circuit partitioning and transistor stacking is presented. The method is based on a novel algorithm dealing with analog specific constraints and on a set of heuristics for stack generation using a pattern database. An enhanced set of stacks is obtained with respect to placement constraints. Experimental results show the effectiveness of the methods described.

TINA: Analog Placement Using Enumerative Techniques Capable of Optimizing both Area and Net Length

T. Abthoff, F. Johannes

In this paper a new enumerative algorithm called TINA is introduced that generates slicing placements optimal in both area and overall net length. It is designed to automate the task of placement for analog circuits given a set of modules with multiple realizations, a corresponding net list, and neighborhood relations. TINA reduces the overall net length to nearly one fifth compared to a net length unaware enumeration algorithm while using only 1.6% more area and twice the CPU-time. TINA is based on enhanced shape functions that are capable of carrying net length information. TINA can be used either as a fully automatic analog placement tool, or as an interactive tool for creating extremely dense placements from a loose placement provided by the designer to establish neighborhood relations. In the first case, another tool, e.g. PLACEBO, is used to compute neighborhood relations. TINA is able to handle all major analog constraints like clustering, framing, fixed orientations, fixed realizations, and symmetries

Session V-01 ANALYSIS TOOLS

Chair: Serafin Olcoz, TGI S.A., Madrid, Spain

The two papers of this session deal with an emergent topic: the analysis and estimation of the quality of VHDL descriptions. Quality covers the areas of testability, reusability, maintainability and portability. The measurements of these features will allow to VHDL designers to move towards and engineering approach to VHDL-based design.

Software Methodologies for VHDL Code Static Analysis based on Flow Graphs

L. Baresi, C. Bolchini, D. Sciuto

At a high level of abstraction, the VHDL specification of the functionalities that a circuit shall perform is given by defining the behavioral model. The similarity with procedural programming languages suggested to tailor some software analysis techniques to VHDL behavioral description analysis. The paper presents several analyses of the code, based on data flows, aimed at identifying significant properties of the final circuit from the synthesis and testability points of view.

A VHDL Reuse Workbench

G. Lehmann, B. Wunder, K. Müller-Glaser

An increasing productivity gap affects the progress of electronic system design. As an immediately available solution, the application of reuse techniques is widely recognized. This paper presents a reuse workbench for VHDL designs which covers the three basic requirements of a design with reuse process: availability , findability, and understandability. The latter is realized by a novel reverse engineering concept for VHDL designs. It is based on the intensive use of hypertext techniques and graphical code representations.

Session V-02 BEYOND VHDL

Chair: Wolfgang Ecker, Siemens AG, München, Germany

Born in 1985 as version 7.2, VHDL should be alive at least until 2015 considering the lifespan of military products. Or is it possible that the other parent of VHDL - namely IEEE, determines the lifespan of VHDL? This and other questions about the future of VHDL should be answered in this session.

Beyond VHDL: Textual Formalisms, Visual Techniques, or Both?

F. Rammig

Since a couple of years VHDL is the dominating Hard­ware Description Language. There are very good reasons for this and simply the existence of VHDL as standardized language had a major impact on the advance of high level design techniques. In this paper some ideas about specification and modelling techniques beyond VHDL curently carried out in the author' s research group are discussed. One approach is to integrate formal specification techniques like Evolving Algebras (EA) and Z into a VHDL­oriented design environment . Other approaches concentrate on the potential of visual modelling techniques. Here techniques based on Parallel Logic Programming like Pictorial Janus (PJ) or such ones based on higher order Petri Nets are under investigation.

Object-Oriented Hardware Modelling -Where to apply and what are the objects?

W. Nebel, G. Schumacher

The importance of reusability of hardware models for the necessary increase in design productivity will be explained for different modelling problems. Methods having previously been proven to be successful in software engineering will be analysed with respect to their applicability to hardware design. It will be shown that object-oriented modelling techniques do potentially increase design productivity, but that VHDL in its current version does not support object oriented modelling. Possible subjects to object-orientation will be discussed.

Hardware/Software Partitioning of VHDL System Specifications

P. Eles, Z. Peng, K. Kuchcinski, A. Doboli

This paper presents an approach for system level specification and hardware/software partitioning with VHDL. The implications of using VHDL as a specification language are discussed and a message passing mechanism is proposed for process interaction. We define the metric values for partitioning and develop a cost function that guides our heuristics towards performance optimization under hardware and software cost constraints. Experimental results are presented.

Session V-03 (PANEL) WHAT ADVANTAGES CAN WE EXPECT FROM OBJECT ORIENTED EXTENSIONS TO VHDL?

Chair: Jean-Michel Bergé, France Telecom CNET, Meylan Cedex, France

Object Oriented techniques have proven to be successful in software engineering. The temptation is therefore great to apply them to the hardware domain. The current version of VHDL does not support Object Oriented Modeling and several proposals for extending the language in this direction have been published. An IEEE study group has also been created on this topic. This panel will try to answer the question above from both the accademic and user point of views.

Panelists:
David L. Barton, intermetrics, Inc., McLean, VA, USA
Wolfgang Ecker, Siemens AG, München, Germany
Wolfgang Nebel, Carl-von-Ossietzky Universität and OFFIS, Oldenburg, Germany
Serafin Olcoz, TGI, Madrid, Spain
Gregory D. Peterson, Wright Laboratory, WPAFB, OH, USA

Session V-04 FAULT MODELING AND DESIGN FOR TESTABILITY

Chair: Eugenio Villar, University de Cantabria, Santander, Spain

In this session, four papers addressing different aspects regarding the use of VHDL in fault modeling and design for testability are included. The different techniques proposed aim to evaluate the design testability in the earlier stages of the design process thus reducing the design for testability costs fo the whole design process.

BDD-Based Testability Estimation of VHDL Designs

F. Ferrandi, F. Fummi, E. Macii, M. Poncino, D. Sciuto

In this paper we present a method, based on symbolic ATPG techniques, that allows the designer to predict the testability of of a control-oriented complex design specified as a set of interacting VHDL modules. Conversely from existing approaches, our method is purely functional, that is, it does not subsume the knowledge of a gate-level implementation of the system being analyzed. Therefore, it allows us to compute testability estimates with a high degree of accuracy for examples on which existing tools fail due to the enormous amount of information they have to handle when considering the structural implementation of the circuit under investigation. Preliminary experimental results demonstrate the effectiveness of the proposed technique.

VHDL Fault Simulation for Defect-Oriented Test and Diagnosis of Digital ICs

F. Celeiro, L. Dias, J. Ferreira, M. Santos, J. Teixeira

For high quality VLSI products, exhibiting very low escape rates, defect-oriented testing becomes mandatory. The design activity is more and more supported by hardware description languages, like VHDL; hence, the testing activity needs to follow this trend. In this paper, a VHDL-based methodology for test preparation of digital ICs is proposed, and a new set of tools for defect-oriented VHDL fault simulation are presented, using a commercial VHDL simulator. The proposed methodology is also shown to be effective in supporting realistic fault diagnosis. Simulation results for benchmark circuits are presented.

Model Generation of Test Logic for Macrocell Based Designs

E. de la Torre, J. Calvo, J. Uceda

This paper presents a set of tools for generation, simulation, evaluation and synthesis of VHDL models of test logic for macrocell based embedded microcontroller based systems. The generated models are described at behavioural level so they fit with system descriptions suited for fast simulation. An IEEE 1149.1 Boundary Scan implementation is used, providing manufacturing test, on line test and monitoring capabilities.

A Fault Model for VHDL Descriptions at the Register Transfer Level

T. Riesgo, J. Uceda

This paper presents a fault model for VHDL descriptions at the Register Transfer Level and its evaluation with respect to a logic level fault model (single-stuck-at). The proposed fault model may be used for early estimations of the fault coverage before the synthesis is made in the design process of an integrated circuit. The obtained results show a high correlation between the fault coverages achieved with the proposed fault model and logic fault models on a set of examples. The main contribution of this work is the proposal of a new fault model for VHDL/RT descriptions and the demonstration of its usefulness for estimating the achieved fault coverage with a set of test vectors in design phases previous to synthesis.

Session V-05 FORMAL METHODS

Chair: Werner Damm, Carl von Ossietzky Universität, Oldenburg, Germany

This session groups three complementary approaches towards the formal analysis of VHDL designs. The first paper provides a systematic approach allowing to characterize that subset of VHDL, whose behaviour can be faithfully abstracted to a synchronous finite-state machine. Suppose a design error has been detected, e.g. through model-checking, how do we then locate that part of the circuit responsible for the error ? This question is answered in the second paper of this session w.r.t. a fault-model for gate-level designs claimed to be typical for design errors. Ideally, designs are corrected by construction. A possible set up to systematically develop correct VHDL-code from logical specifications following the refinement paradigm is described in the last paper of this session.

The Maximal VHDL Subset with a Cycle-Level Abstraction

W. Baker, A. Newton

The maximal VHDL subset with a cycle-level abstraction is defined. This subset requires that the description have three semantic properties: responsiveness, modularity and causality, but full VHDL is neither modular nor causal. Synchronous VHDL is the responsive, modular and causal subset of VHDL. The compiler uses modularity-checking and causality-checking to identify admissible programs.

Automatic Diagnosis May Replace Simulation for Correcting Simple Design Errors

A. Wahba, D. Borrione

An automated tool for diagnosing simple design errors in VHDL descriptions is presented. The tool is tested on bench-mark circuits, and the results show that the error is localized precisely, after the applicationof a small number of specially generated test patterns. This tool is now integrated within the PREVAIL TM system, and is being tested on industrial circuits.

A Refinement Calculus for VHDL

P. Breuer, C. Delgado-Kloos, N. Martínez-Madrid, A. Marín, Luis Sánchez

A refinement calculus for the specification of real-time systems and their refinement to a VHDL behavioural description is set out here. The specification format is a logical triple with the lookof a Z or VDMschema. Choices from a short menu of refinement operations gradually convert an initial specification to VHDL code through a series of mixed mode intermediates. The calculus is complete in the sense that if there isacode of the VHDL subset considered here (unit-delay waits and signal assignments but no delta delays) satisfying the specification, then it can be obtained by applying some sequence of the refinement operations. The result is ``correct by construction".

Session V-06 MODELING METHODOLOGIES

Chair: Victor Berman, Cadence Design Systems Inc., Chelmsford, MA, USA

Analysis of Different Protocol Description Styles in VHDL for High-Level Synthesis

L. Pirmez, M. Rahmouni, P. Kission, A. Pedroza, A. Mesquita, A. Jerraya

When synthesizing control-flow dominated descriptions based on VHDL, different styles of semantically equivalent descriptions may differ significantly in quality. This paper discusses the effect of the input description on High-Level Synthesis when using VHDL. In order to show this effect, a high speed protocol based on the ISO reference protocol Abracadabra is used. Five VHDL descriptions styles of the same protocol have been synthesized using AMICAL, a VHDL based behavioral synthesis tool. Discussions of the different results leads to a VHDL based methodology for protocol modelling in order to produce efficient designs.

Hardware Synthesis from Requirement Specifications

K. Feyerabend, R. Schlör

This paper describes the theory and implementation of a novel system for hardware synthesis from requirement specifications expressed in a graphical specification language called Symbolic Timing Diagrams (STD). The system can be used together with an existing formal verification environment for VHDL leading to a novel methodology based on the combination of synthesis and formal verification. We show the feasibility of the approach and experimental results obtained with the system on the well known example of an industrial production cell, where both FPGA and ASIC hardware implementations were successfully synthesized.

Modeling ASIC Memories in VHDL

E. Balaji, P. Krishnamurthy

Memories are an important component in ASIC designs. With increasing design complexities, there is need to model memory devices with a high level of accuracy and simulation efficiency. This paper describes the functional/timing aspects of VHDL memory models, their implementation, and various issues involved. The paper also presents a generic interface package used in the development of memory models.

Stepwise Refinement of Behavioral VHDL Specifications by Separation of Synchronization and Functionality

C. Schneider, W. Ecker

We present a new method of behavioral modeling consisting of separation of synchronization and functionality. In this way incomplete specification and incremental refinement can be performed to reduce the modeling effort in early design stages. Compared to known methods our approach allows early cycle based analysis to select appropriate architectures and to perform parallel/serial trade-off. Due to the separation of synchronization and functionality the datapath can be developed independently of the controller and thus enables concurrent engineering. Another important characteristic is the reuse friendly architecture proposed in this paper.

Session V-07 SYNTHESIS

Chair: Ahmed Amine Jerraya, TIMA/INPG, Grenoble Cedex, France

This session deals with three important issues in synthesis with VHDL: Parallel controlled synthesis, timing constraints management, and extending VHDL subsets for synthesis.

Synchronous Parallel Controller Synthesis from Behavioural Multiple-Process VHDL Description

K. Bilinski, E. Dagless, J. Mirkowski

A unified framework and associated algorithms for a behavioural synthesis of parallel controllers from a multiple-process VHDL specification is presented. An extension to FSMs, based on Petri nets, is used asan internal representation of an concurrent system during the synthesis. The VHDL simulation cycle implications are explicitly implemented into the Petri net model. This model is next decomposed into a set of well formed sub-controllers and a state assignments is generated.

Specification and Management of Timing Constraints in Behavioural VHDL

F. Curatelli, L. Mangeruca, M. Chirico

In this paper a suitable way to specify and managetiming constraints in behavioral VHDL is described. The problem of timing semantics coherency is addressed and a suitable set of procedures is defined to add timing constraint specification in behavioral VHDL for system synthesis. Then, a proper semantics is described which is able to provide a powerful and flexible management of timing constraints.

Towards Maximising the Use of Structural VHDL for Synthesis

K. O'Brien, A. Robert, S. Maginot

In this paper we show that by performing some VHDL elaboration transformations before synthesis we can extend the synthesis subset to include complex structural and hierarchical statements. This in turn means that:

• Design, debug and simulation times are reduced.
• Designs are more accessible (readable, modifiable, portable, reusable)
• Design prototyping can be speeded up.

All of this can be achieved without the need to modify existing synthesis tools.

Session V-08 SYSTEM LEVEL DESIGN

Chair: Ronald Waxman, University of Virginia, Charlottesville, VA, USA

The underlying theme of this session is the power of VHDL to support many aspects of design at the highest levels of design abstraction. This range is exemplified by three papers. The range covers such diverse areas as asynchronous communication and hardware/software co-design, evaluation of fault tolerance and error detecting mechanisms, and specification modeling coupled with the design process.

Fault Behaviour Observation of a Microprocessor System through a VHDL Simulation-Based Fault Infection Experiment

A.M. Amendola, A. Benso, F. Corno, L. Impagliazzo, P. Marmo, P. Prinetto, M. Rebaudengo, M. Sonza Reorda

Evaluating and possibly improving the fault tolerance and error detecting mechanisms is becoming a key issue when designing safety-critical electronic systems. The proposed approach is based on simulation-based fault injection and allows the analysis of the system behavior when faults occur. The paper describes how a microprocessor board employed in an automated light-metro control system has been modeled in VHDL and a Fault Injection Environment has been set up using a commercial simulator. Preliminary results about the effectiveness of the hardware fault-detection mechanisms are also reported. Such results will address the activity of experimental evaluation in subsequent phases of the validation process.

System Design Using an Integrated Specification and Performance Modeling Methodology

A. Sarkar

A system-design methodology based on the synergistic integration of the specification modeling and the performance modeling design stages is presented. This synergy is supported by: 1) a novel technique that dynamically and automatically incorporates delay information into an executable specification from the corresponding performance model, and 2) a novel simulation-based algorithm that automatically checks conformance between the two models. VHDL is the primary means for integrating these two disparate design stages.

An Extendable MIPS-I Processor Kernel in VHDL for Hardware/Software Co-Design

M. Gschwind, D. Maurer

This paper discusses the design of a MIPS-I processor kernel using VHDL. The control structure of this processor is distributed, with a small controller in each pipeline stage controlling sequencing of operations and communication with adjacent pipeline stages. Instruction flow management is performed using asynchronous communication signals. Due to its high-level description and distributed control structure, the kernel can easily be extended. Thus, instruction set extension hardware/software co-evaluation can be performed efficiently using rapid prototyping.

Session V-09 VHDL AND MIXED SIGNAL DESIGN

Chair: Alain Vachoux, Swiss Federal Institute of Technology (EPFL), Lausanne, Switzerland

This session begins with an invited paper in the IEEE VHDL 1076.1 standard proposal to extend VHDL to handle analog and mixed-signal systems. At that time, a ballotable language reference manual will be available, The IEEE ballot process is planned to start before the end of year 1996. The second paper proposes interesting guidelines to enhance the usability of VHDL 1076.1 to describe mixed-signal designs. The third paper is more tool oriented as it proposes a new intermediate format able to represent mixed- signal descriptions in a consistent way.

VHDL 1076.1 - Analog and Mixed Signal Extensions to VHDL

E. Christen, K. Bakalar

This presentation provides an overview of the 1076.1 effort to extend the well established VHDL language to support the description and simulation of continuous and mixed continuous/discrete systems. It begins with a brief history of the effort. That is followed by an overview of the foundations: the design objectives, the base VHDL 1076 language, and the applicable mathematical theory. The body of the presentation describes the elements of the extended language. Each language element is described in the context of the 1076.1 language architecture and illustrated by a brief example. The presentation ends with selected examples illustrating the use of the language for analog and mixed-signal applications.

Entity Overloading for Mixed-Signal Abstraction in VHDL

R. Shi

In this paper we propose to extend VHDL with entity overloading. With a minimal change to existing VHDL, entity overloading provides a strong support for mixed-signal, mixed-level, and mixed-domain abstractions. It is particularly promising in resolving some issues in VHDL-A language design. Furthermore, we illustrate that entity overloading can be combined with certain modeling rules to achieve polymorphic netlist.

KIR - A Graph-Based Model for Description of Mixed Analog/ Digital Systems

C. Grimm, K. Waldschmidt

Systems can be described in different time models and on various levels of abstraction. We can distinguish between models in discrete-event, discrete and continuous time. Graph-based, formal models allow us to use either discrete event/discrete time models or continuous time models. The combined use of all three time models in one system is the main problem when modeling mixed analog/digital systems. In this paper, a graph-based model is presented that supports the use of all three time models in different parts of a graph. This allows digital, discrete-time systems to be modeled together with their analoga , physical environment.

Session V-10 (PANEL) THE OPEN FORUM MODEL

Chair: Victor Berman, Cadence Design Systems Inc., Chelmsford, MA, USA