ASP-DAC 2003 AUTHOR INDEX

[A] [B] [C] [D] [E] [F] [G] [H] [I] [J] [K] [L] [M] [N] [O] [P] [Q] [R] [S] [T] [U] [V] [W] [X] [Y] [Z]

A

Abadir, M.
8C-4 SLV/ATPG: an Automated Flow for Test Model Generation from Switch Level Custom Circuits [p. 769]
Abadir , M.S.
1D-2 Logic Verification Based on Diagnosis Techniques [p. 93]
3D-2 Enhanced Symbolic Simulation for Efficient Verification of Embedded Array Systems [p. 302]
Abbaspour, S.
1B-3 Calculating the Effective Capacitance for the RC Interconnect in VDSM Technologies [p. 43]
Abraham, J.A.
7C-1 Efficient Loop-back Testing of On-chip ADCs and DACs [p. 651]
Acar, E.
3C-2 Predicting Short Circuit Power from Timing Models [p. 277]
Agarwal, A.
3C-1 Statistical Delay Computation Considering Spatial Correlations [p. 271]
Aghaghiri, Y.
1A-1 BEAM: Bus Encoding Based on Instruction-Set-Aware Memories [p. 3]
Al-Khalili, A.
3B-1 Adaptive Wire Adjustment for Bounded Skew Clock Distribution Network [p. 243]
Al-Khalili, D.
3B-1 Adaptive Wire Adjustment for Bounded Skew Clock Distribution Network [p. 243]
Allstot, D.J.
9D-4 Parasitic-Aware Design and Optimization of a Fully Integrated CMOS Wideband Amplifier [p. 904]
Amano, H.
6D-9 MAPLE Chip: a Processing Element for a Static Scheduling Centric Multiprocessor [p. 575]
Anido M.L.
5C-3 Interactive Ray Tracing on Reconfigurable SIMD MorphoSys [p. 471]
Arai, M.
9C-3 A Seed Selection Procedure for LFSR-Based Random Pattern Generators [p. 869]
Arunachalam, R.
3C-2 Predicting Short Circuit Power from Timing Models [p. 277]
Asai, H.
2C-3 Behavioral Modeling of EM Devices by Selective Orthogonal Matrix Least-Squares Method [p. 184]

B

Bagherzadeh, N.
5C-3 Interactive Ray Tracing on Reconfigurable SIMD MorphoSys [p. 471]
7D-4s Topology Selection for Energy Minimization in Embedded Networks [p. 693]
Balasa, F.
8D-1 Using Red-Black Interval Trees in Device-Level Analog Placement with Symmetry Constraints [p. 777]
Bandyopadhyay, S.
9C-4s Efficient BIST Design for Sequential Machines Using FiF-FoF Values in Machines States [p. 875]
Banerjee, P.
5C-4 An Overview of a Compiler for Mapping MATLAB Programs onto FPGAs [p. 477]
Bao, H.
9B-2 UTACO: a Unified Timing and Congestion Optimizing Algorithm for Standard Cell Global Routing [p. 834]
Basu, S.
9C-4s Efficient BIST Design for Sequential Machines Using FiF-FoF Values in Machines States [p. 875]
Bellows, P.
5C-2 Applications of Adaptive Computing Systems for Signal Processing Challenges [p. 465]
Bengtsson, T.
2D-1 A BDD-based Fast Heuristic Algorithm for Disjoint Decomposition [p. 191]
Benini, L.
4D-1 Advanced Power Management Techniques: Going Beyond Intelligent Shutdown [p. 385]
Benjamin, M.
8A-1 Semi-Formal Test Generation and Resolving a Temporal Abstraction Problem in Practice: Industrial Application [p. 699]
Bhattacharyya, S.
4C-5 Logic Foundry: Rapid Prototyping of FPGA-based DSP Systems [p. 374]
Bianco, A.
5D-3s A Reconfigurable, Power-Scalable Rake Receiver IP for W-CDMA [p. 499]
Blaauw, D.
3C-1 Statistical Delay Computation Considering Spatial Correlations [p. 271]
Brayton, R. K.
9A-2 Don't Cares in Logic Minimization of Extended Finite State Machines [p. 809]

C

Cai, Y.
5A-6s A Buffer Planning Algorithm Based on Dead Space Redistribution [p. 435]
8B-5s A Path-based Timing-driven Quadratic Placement Algorithm [p. 745]
9B-2 UTACO: a Unified Timing and Congestion Optimizing Algorithm for Standard Cell Global Routing [p. 834]
9B-4s A Novel Timing-Driven Global Routing Algorithm Considering Coupling Effects for High Performance Circuit Design [p. 847]
Cao, A.
9A-4s Integer Linear Programming-Based Synthesis of Skewed Logic Circuits [p. 820]
Cao, H.
1B-2 A Fast and Accurate Method for Interconnect Current Calculation [p. 37]
Cao, Y.
6A-2 Quality-Driven Design by Bitwidth Optimization for Video Applications [p. 532]
Cesário, W.O.
3A-1 Combining Architecture Exploration and a Path to Implementation to Build a Complete SoC Design Flow from System Specification to RTL [p. 219]
Chakravarthy, K.K.
6D-6 Speech Encoding and Encryption in VLSI [p. 569]
Chandrakasan, A.
1B-5s Design Tools for 3-D Integrated Circuits [p. 53]
Chang, C.-C.
4A-2 Multi-level Placement for Large-Scale Mixed-Size IC Designs [p. 325]
7B-1 Optimality and Scalability Study of Existing Placement Algorithms [p. 621]
7B-3 Silicon Virtual Prototyping: The New Cockpit for Nanometer Chip Design [p. 635]
Chang, Y.-W.
5A-3s Noise-Aware Buffer Planning for Interconnect-Driven Floorplanning [p. 423]
5A-5s Simultaneous Floorplanning and Buffer Block Planning [p. 431]
9B-5s Graph Matching-Based Algorithms for Array-Based FPGA Segmentation Design and Routing [p. 851]
Chao, K.-Y.
5A-5s Simultaneous Floorplanning and Buffer Block Planning [p. 431]
Chen, C.C.-P.
7A-5 A Hierarchical Analysis Methodology for Chip-Level Power Delivery with Realizable Model Reduction [p. 614]
Chen, C.-H.
5D-7s An Effective SDRAM Power Mode Management Scheme for Performance and Energy Sensitive Embedded Systems [p. 515]
Chen, D.
1C-2 Energy Minimization of Real-time Tasks on Variable Voltage Processors with Transition Energy Overhead [p. 65]
Chen, D.-S.
4A-5s Non-slicing Floorplans with Boundary Constraints Using Generalized Polish Expression [p. 342]
Chen, F.-S.
1D-3 Algorithms for Compacting Error Traces [p. 99]
Chen, H.
9B-3 The Y-Architecture: Yet Another On-Chip Interconnect Solution [p. 840]
Chen, H.-M.
5A-4s Floorplanning with Power Supply Noise Avoidance [p. 427]
Chen, I-H.
6D-12 Low-Power Digital CDMA Receiver [p. 581]
Chen, J.
2B-4 Determination of Worst-Case Crosstalk Noise for Non-Switching Victims in GHz+ Interconnects [p. 162]
Chen, M.-C.
6D-1 Design and Implementation of a Video-Oriented Network-Interface-Card System [p. 559]
Chen, S.
5A-6s A Buffer Planning Algorithm Based on Dead Space Redistribution [p. 435]
8B-4s VLSI Module Placement with Pre-placed Modules and Considering Congestion Using Solution Space Smoothing [p. 741]
Chen, T.
6D-4 A 1.8 Million Transistor Test Chip in a 0.18 um CMOS for Package Models and I/O Characteristics Verification [p. 565]
Chen, W.
8B-3 Cross Talk Driven Placement [p. 735]
Chen, Y.-A.
1D-3 Algorithms for Compacting Error Traces [p. 99]
Chen, Z.
9D-1 Periodic Steady-State Analysis of Coupled ODE-AE-CGE Systems for MOS RF Autonomous Circuit Simulation [p. 885]
Cheng, C.-K.
3C-3 RCLK-VJ Network Reduction with Hurwitz Polynomial Approximation [p. 283]
5A-6s A Buffer Planning Algorithm Based on Dead Space Redistribution [p. 435]
9B-2 UTACO: a Unified Timing and Congestion Optimizing Algorithm for Standard Cell Global Routing [p. 834]
9B-3 The Y-Architecture: Yet Another On-Chip Interconnect Solution [p. 840]
Cheng, K.-T.
3D-2 Enhanced Symbolic Simulation for Efficient Verification of Embedded Array Systems [p. 302]
7C-4 Delta-sigma Modulator Based Mixed-signal BIST Architecture for SoC [p. 669]
8C-1 Experience in Critical Path Selection for Deep Sub-Micron Delay Test and Timing Validation [p. 751]
Cheng, S.-W.
6A-3 Arbitrary Long Digit Integer Sorter HW/SW Co-Design [p. 538]
Cherng, Y.-H.
5A-3s Noise-Aware Buffer Planning for Interconnect-Driven Floorplanning [p. 423]
Choi, K.
9D-4 Parasitic-Aware Design and Optimization of a Fully Integrated CMOS Wideband Amplifier [p. 904]
Choi, J.
2A-4 A Hardware/Software Partitioning Algorithm for SIMD Processor Cores [p. 135]
Choi, L.
5D-8s Branch Predictor Design and Performance Estimation for a High Performance Embedded Microprocessor [p. 519]
Chou, P. H.
7D-4s Topology Selection for Energy Minimization in Embedded Networks [p. 693]
Chowdhury, D.R.
9C-5s A New Design-for-Test Technique for Reducing SOC Test Time [p. 879]
Clarke, E.
3D-3s Hardware Verification Using ANSI-C Programs as a Reference [p. 308]
Cong, J.
4A-2 Multi-level Placement for Large-Scale Mixed-Size IC Designs [p. 325]
7B-1 Optimality and Scalability Study of Existing Placement Algorithms [p. 621]
Courtoy, M.
7B-3 Silicon Virtual Prototyping: The New Cockpit for Nanometer Chip Design [p. 635]

D

Dai, W.-J.
7B-3 Silicon Virtual Prototyping: The New Cockpit for Nanometer Chip Design [p. 635]
Daleby, A.
7D-2 A Comparison of the RTU Hardware RTOS with a Hardware/Software RTOS [p. 683]
Das, S.
1B-5s Design Tools for 3-D Integrated Circuits [p. 53]
Dassatti, A.
5D-3s A Reconfigurable, Power-Scalable Rake Receiver IP for W-CDMA [p. 499]
De Maeyer, J.
6D-13 Hardware Implementation of an EAN-13 Bar Code Decoder [p. 583]
Despande, C.
6D-4 A 1.8 Million Transistor Test Chip in a 0.18 um CMOS for Package Models and I/O Characteristics Verification [p. 565]
Devos, H.
6D-13 Hardware Implementation of an EAN-13 Bar Code Decoder [p. 583]
Dharmadeep, M.C.
2D-4s Synthesis of High Performance Low Power PTL Circuits [p. 209]
Dimaggio, R.
9D-2 A Frequency Separation Macromodel for System-Level Simulation of RF Circuits [p. 891]
Doerre, G.
7B-2 IBM's 50 Million Gate ASICs [p. 628]
Domigues, C.
7C-3 An Implementation of Memory-based On-chip Analogue Test Signal Generation [p. 663]
Dong, S.
5A-6s A Buffer Planning Algorithm Based on Dead Space Redistribution [p. 435]
8B-4s VLSI Module Placement with Pre-placed Modules and Considering Congestion Using Solution Space Smoothing [p. 741]
Doucet, F.J.
2A-1 Typing Abstractions and Management in a Component Framework [p. 115]
Du, H.
5C-3 Interactive Ray Tracing on Reconfigurable SIMD MorphoSys [p. 471]
Dubrova, E.
2D-1 A BDD-based Fast Heuristic Algorithm for Disjoint Decomposition [p. 191]
Dumitras, T.
3A-2 Towards On-Chip Fault-Tolerant Communication [p. 225]
Dushina, J.
8A-1 Semi-Formal Test Generation and Resolving a Temporal Abstraction Problem in Practice: Industrial Application [p. 699]
Dziri, M.A.
3A-1 Combining Architecture Exploration and a Path to Implementation to Build a Complete SoC Design Flow from System Specification to RTL [p. 219]

E

Eckerbert, D.
8A-4s A Deep Submicron Power Estimation Methodology Adaptable to Variations between Power Characterization and Estimation [p. 716]
Eriksson, H.
5D-5s Full-Custom vs. Standard-Cell Design Flow - an Adder Case Study [p. 507]

F

Fallah, F.
1A-1 BEAM: Bus Encoding Based on Instruction-Set-Aware Memories [p. 3]
2A-2 Event-Driven Observability Enhanced Coverage Analysis of C Programs for Functional Validation [p. 123]
Fan, H.
4C-3s On Improving FPGA Routability Applying Multi-level Switch Boxes [p. 366]
Feng, T.
3D-2 Enhanced Symbolic Simulation for Efficient Verification of Embedded Array Systems [p. 302]
Fernandez, M.
5C-3 Interactive Ray Tracing on Reconfigurable SIMD MorphoSys [p. 471]
French, M.
5C-2 Applications of Adaptive Computing Systems for Signal Processing Challenges [p. 465]
Fujibayashi, M.
6D-5 A Still Image Encoder Based on Adaptive Resolution Vector Quantization Employing Needless Calculation Elimination Architecture [p. 567]
Fujimori, K.
6D-16 Standard Cell Libraries with Various Driving Strength Cells for 0.13, 0.18 and 0.35um Technologies [p. 589]
Fujita, M.
1A-2 Irredundant Address Bus Encoding Techniques Based on Adaptive Codebooks for Low Power [p. 9]
2A-2 Event-Driven Observability Enhanced Coverage Analysis of C Programs for Functional Validation [p. 123]
2D-2 Logic Optimization for Asynchronous Speed Independent Controllers Using Transduction Method [p. 197]
Fujiyoshi, K.
4A-3 Selected Sequence-Pair: An Efficient Decodable Packing Representation in Linear Time using Sequence-Pair [p. 331]
Fukumoto, S.
9C-3 A Seed Selection Procedure for LFSR-Based Random Pattern Generators [p. 869]
Fukunaga, M.
8C-2 On Effective Criterion of Path Selection for Delay Testing [p. 757]

G

Gala, K.
3C-1 Statistical Delay Computation Considering Spatial Correlations [p. 271]
Gao, Y.
1B-2 A Fast and Accurate Method for Interconnect Current Calculation [p. 37]
Geist, D.
8A-1 Semi-Formal Test Generation and Resolving a Temporal Abstraction Problem in Practice: Industrial Application [p. 699]
Ghiasi, S.
4C-2 Optimal Reconfiguration Sequence Management [p. 359]
Ghosh, I.
2A-2 Event-Driven Observability Enhanced Coverage Analysis of C Programs for Functional Validation [p. 123]
Gu, J.
5A-6s A Buffer Planning Algorithm Based on Dead Space Redistribution [p. 435]
8B-4s VLSI Module Placement with Pre-placed Modules and Considering Congestion Using Solution Space Smoothing [p. 741]
9B-2 UTACO: a Unified Timing and Congestion Optimizing Algorithm for Standard Cell Global Routing [p. 834]
9B-4s A Novel Timing-Driven Global Routing Algorithm Considering Coupling Effects for High Performance Circuit Design [p. 847]
Gupta, P.
9C-1 Routing-Aware Scan Chain Ordering [p. 857]
Gupta, R.K.
2A-1 Typing Abstractions and Management in a Component Framework [p. 115]
Gyohten, T.
6D-17 A Nearest-Hamming-Distance Search Memory with Fully Parallel Mixed Digital-Analog Match Circuitry [p. 591]

H

Ha, S.
1A-4 Memory Access Pattern Analysis and Stream Cache Design for Multimedia Applications [p. 22]
Haid, J.
7A-1 Run-Time Energy Estimation in System-On-a-Chip Designs [p. 595]
Hamada, H.
5B-1 VCore Based Design Methodology [p. 441]
5B-2 Synthesis for SoC Architecture Using VCores [p. 446]
Hanamura, S.
5B-4 VCDS Tool Demonstration [p. 459]
Harada, M.
4D-3 Design Methodology of Low-Power CMOS RF-ICs [p. 394]
Haramiishi, H.
6D-11 The Design of PCI Bus Interface [p. 579]
Hashimoto, M.
2B-2 Accurate Prediction of the Impact of On-chip Inductance on Interconnect Delay using Electrical and Physical Parameter-based RSF [p. 149]
6D-16 Standard Cell Libraries with Various Driving Strength Cells for 0.13, 0.18 and 0.35um Technologies [p. 589]
Hatayama, K.
8C-3 DFT Timing Design Methodology for At-Speed BIST [p. 763]
Hattori, T.
4D-2 Design Technologies for Low Power Microprocessors [p. 390]
Haubelt, C.
6A-1 Accelerating Design Space Exploration Using Pareto-Front Arithmetics [p. 525]
Hayasaka, H.
6D-11 The Design of PCI Bus Interface [p. 579]
Hayes, J.P.
3D-1 Gate-Level Simulation of Quantum Circuits [p. 295]
He, L.
2B-4 Determination of Worst-Case Crosstalk Noise for Non-Switching Victims in GHz+ Interconnects [p. 162]
Hemmert, K.S.
5C-5 Issues in Debugging Highly Parallel FPGA-based Applications Derived from Source Code [p. 483]
Henkel, J.
1A-3 Multi-Parametric Improvements for Embedded Systems Using Code-Placement and Address Bus Coding [p. 15]
7A-2 SEA: Fast Power Estimation for Micro-Architectures [p. 600]
Henriksson, T.
5D-5s Full-Custom vs. Standard-Cell Design Flow - an Adder Case Study [p. 507]
6D-3 Implementation of Fast CRC Calculation [p. 563]
Hisamitsu, K.
2C-2 Temperature-Independence-Point Properties for 0.1um-Scale Pocket-Implant Technologies and the Impact on Circuit Design [p. 179]
Ho, C.-L.
8A-3s A Novel Approach for Digital Waveform Compression [p. 712]
Hong, X.
3B-3 BBE: Hierarchical Computation of 3-D Interconnect Capacitance with BEM Block Extraction [p. 255]
5A-6s A Buffer Planning Algorithm Based on Dead Space Redistribution [p. 435]
8B-1 Congestion Driven Incremental Placement Algorithm for Standard Cell Layout [p. 723]
8B-4s VLSI Module Placement with Pre-placed Modules and Considering Congestion Using Solution Space Smoothing [p. 741]
8B-5s A Path-based Timing-driven Quadratic Placement Algorithm [p. 745]
9B-2 UTACO: a Unified Timing and Congestion Optimizing Algorithm for Standard Cell Global Routing [p. 834]
9B-4s A Novel Timing-Driven Global Routing Algorithm Considering Coupling Effects for High Performance Circuit Design [p. 847]
Hong, Z.-W.
7D-3s Linux Kernel Customization for Embedded Systems by Using Call Graph Approach [p. 689]
Hosokawa, K.
4D-5s A Low Power CMOS Circuit with Variable Source Scheme (VSCMOS) [p. 404]
Hosokawa, T.
5B-1 VCore Based Design Methodology [p. 441]
Hou, W.
8B-5s A Path-based Timing-driven Quadratic Placement Algorithm [p. 745]
Hsiao, S.-F.
6D-1 Design and Implementation of a Video-Oriented Network-Interface-Card System [p. 559]
Hsu, C.-Y.
7A-4s An Efficient IP-Level Power Model for Complex Digital Circuits [p. 610]
Hu, J.
3A-3 Energy-Aware Mapping for Tile-based NoC Architectures under Performance Constraints [p. 233]
Hu, X.S.
1C-2 Energy Minimization of Real-time Tasks on Variable Voltage Processors with Transition Energy Overhead [p. 65]
1C-3 Register Aware Scheduling for Distributed Cache Clustered Architecture [p. 71]
7A-2 SEA: Fast Power Estimation for Micro-Architectures [p. 600]
Huang, C.-T.
5D-2s Design of a Scalable RSA and ECC Crypto-Processor [p. 495]
6D-2 A Highly Efficient AES Cipher Chip [p. 561]
Huang, D.
7B-3 Silicon Virtual Prototyping: The New Cockpit for Nanometer Chip Design [p. 635]
Huang, L.-D.
5A-4s Floorplanning with Power Supply Noise Avoidance [p. 427]
Hutchings, B.L.
5C-5 Issues in Debugging Highly Parallel FPGA-based Applications Derived from Source Code [p. 483]
Hwang, S.
7C-1 Efficient Loop-back Testing of On-chip ADCs and DACs [p. 651]

I

Ichino, K.
9C-3 A Seed Selection Procedure for LFSR-Based Random Pattern Generators [p. 869]
Iguchi, Y.
3D-4s Evaluation of Multiple-Output Logic Functions Using Decision Diagrams [p. 312]
Ingström, K.
7D-2 A Comparison of the RTU Hardware RTOS with a Hardware/Software RTOS [p. 683]
Iranli, A.
9A-1 Low Power Synthesis of Finite State Machines with Mixed D and T Flip-Flops [p. 803]
Iwai, K.
6D-9 MAPLE Chip: a Processing Element for a Static Scheduling Centric Multiprocessor [p. 575]
Iwasaki, K.
9C-3 A Seed Selection Procedure for LFSR-Based Random Pattern Generators [p. 869]

J

Jeong, W.
5D-4s Robust High-Performance Low-Power Carry Select Adder [p. 503]
Jerke, G.
8D-2 Current-Driven Wire Planning for Electromigration Avoidance in Analog Circuits [p. 783]
Jerraya, A.A.
3A-1 Combining Architecture Exploration and a Path to Implementation to Build a Complete SoC Design Flow from System Specification to RTL [p. 219]
Jiang, I.H.-R.
5A-5s Simultaneous Floorplanning and Buffer Block Planning [p. 431]
Jiang, Y.
9A-2 Don't Cares in Logic Minimization of Extended Finite State Machines [p. 809]
Jin, L.
4A-4s An Extended Representation of Q-sequence for Optimizing Channel-Adjacency and Routing-Cost [p. 338]
Jing, T.
9B-2 UTACO: a Unified Timing and Congestion Optimizing Algorithm for Standard Cell Global Routing [p. 834]
9B-4s A Novel Timing-Driven Global Routing Algorithm Considering Coupling Effects for High Performance Circuit Design [p. 847]
Jolly, S.
8C-4 SLV/ATPG: an Automated Flow for Test Model Generation from Switch Level Custom Circuits [p. 769]
Jou, J.-Y.
1D-5s An Automatic Interconnection Rectification Technique for SoC Design Integration [p. 108]
5A-5s Simultaneous Floorplanning and Buffer Block Planning [p. 431]
7A-4s An Efficient IP-Level Power Model for Complex Digital Circuits [p. 610]
Jou, S.-J.
6D-12 Low-Power Digital CDMA Receiver [p. 581]
8D-4 5Gbps Serial Link Transmitter with Pre-emphasis [p. 795]

K

Kaefer, G.
7A-1 Run-Time Energy Estimation in System-On-a-Chip Designs [p. 595]
Kahng, A.B.
9B-1 Highly Scalable Algorithms for Rectilinear and Octilinear Steiner Trees [p. 827]
9C-1 Routing-Aware Scan Chain Ordering [p. 857]
Kaitsu, Y.
5B-4 VCDS Tool Demonstration [p. 459]
Kajihara, S.
8C-2 On Effective Criterion of Path Selection for Delay Testing [p. 757]
Kajitani, Y.
4A-4s An Extended Representation of Q-sequence for Optimizing Channel-Adjacency and Routing-Cost [p. 338]
Kalla, P.
7A-2 SEA: Fast Power Estimation for Micro-Architectures [p. 600]
Kanamoto, T.
2B-2 Accurate Prediction of the Impact of On-chip Inductance on Interconnect Delay using Electrical and Physical Parameter-based RSF [p. 149]
Kang, C.-w.
2D-3 Technology Mapping for Low Leakage Power and High Speed with Hot-Carrier Effect Consideration [p. 203]
Kao, C.-C.
2D-5s A Technology Mapping Algorithm for Heterogeneous FPGAs [p. 213]
Katkoori, S.
4C-1 Efficient LUT-Based FPGA Technology Mapping for Power Minimization [p. 353]
Kato, Y.
6D-14 Error Correction Circuit using Difference-set Cyclic Code [p. 585]
Kawaguchi, A.
7D-1 New Paradigm from Requirement to Implementation - in Case of Software and Possibility of Applying to Hardware - (tentative) [p.677]
Kawakami, Y.
2B-2 Accurate Prediction of the Impact of On-chip Inductance on Interconnect Delay using Electrical and Physical Parameter-based RSF [p. 149]
Kawashima, M.
8C-3 DFT Timing Design Methodology for At-Speed BIST [p. 763]
Ker, N.-Y.
5D-7s An Effective SDRAM Power Mode Management Scheme for Performance and Energy Sensitive Embedded Systems [p. 515]
Kerner, S.
3A-2 Towards On-Chip Fault-Tolerant Communication [p. 225]
Kim, E.
9A-3s Performance Optimization of Synchronous Control Units for Datapaths with Variable Delay Arithmetic Units [p. 816]
Kim, I.-K.
5D-8s Branch Predictor Design and Performance Estimation for a High Performance Embedded Microprocessor [p. 519]
Kim, J.K.
2A-3 Trace-driven Rapid Pipeline Architecture Evaluation Scheme for ASIP Design [p. 129]
Kim, T.G.
2A-3 Trace-driven Rapid Pipeline Architecture Evaluation Scheme for ASIP Design [p. 129]
Kitamaru, D.
2C-2 Temperature-Independence-Point Properties for 0.1um-Scale Pocket-Implant Technologies and the Impact on Circuit Design [p. 179]
Kitaura, T.
2B-2 Accurate Prediction of the Impact of On-chip Inductance on Interconnect Delay using Electrical and Physical Parameter-based RSF [p. 149]
Klevin, T.
7D-2 A Comparison of the RTU Hardware RTOS with a Hardware/Software RTOS [p. 683]
Kobayashi, H.
2B-2 Accurate Prediction of the Impact of On-chip Inductance on Interconnect Delay using Electrical and Physical Parameter-based RSF [p. 149]
Kodama, C.
4A-3 Selected Sequence-Pair: An Efficient Decodable Packing Representation in Linear Time using Sequence-Pair [p. 331]
Kodate, J.
4D-3 Design Methodology of Low-Power CMOS RF-ICs [p. 394]
Koehl, J.
7B-2 IBM's 50 Million Gate ASICs [p. 628]
Koh, C.-K.
2B-3 A Metric for Analyzing Effective On-Chip Inductive Coupling [p. 156]
9A-4s Integer Linear Programming-Based Synthesis of Skewed Logic Circuits [p. 820]
Koide, T.
6D-17 A Nearest-Hamming-Distance Search Memory with Fully Parallel Mixed Digital-Analog Match Circuitry [p. 591]
Komatsu, S.
1A-2 Irredundant Address Bus Encoding Techniques Based on Adaptive Codebooks for Low Power [p. 9]
Kon, C.
6D-7 The Design of a i8080A Instruction Compatible Processor with Extended Memory Address [p. 571]
6D-8 The Design of a USB Device Controller IYOYOYO [p. 573]
Kotani, K.
6D-5 A Still Image Encoder Based on Adaptive Resolution Vector Quantization Employing Needless Calculation Elimination Architecture [p. 567]
Kouyama, T.
6D-8 The Design of a USB Device Controller IYOYOYO [p. 573]
Krishnamoorthy, K.
8D-1 Using Red-Black Interval Trees in Device-Level Analog Placement with Symmetry Constraints [p. 777]
Kroening, D.
3D-3s Hardware Verification Using ANSI-C Programs as a Reference [p. 308]
Krstic, A.
8C-1 Experience in Critical Path Selection for Deep Sub-Micron Delay Test and Timing Validation [p. 751]
Kumar, I.V.
6D-15 Design of a Digital CDMA Receiver [p. 587]
Kumashiro, S.
2C-2 Temperature-Independence-Point Properties for 0.1um-Scale Pocket-Implant Technologies and the Impact on Circuit Design [p. 179]
Kurokawa, A.
2B-1 Approximate Formulae Approach for Efficient Inductance Extraction [p. 143]
2B-2 Accurate Prediction of the Impact of On-chip Inductance on Interconnect Delay using Electrical and Physical Parameter-based RSF [p. 149]

L

Lackey, D.E.
7B-2 IBM's 50 Million Gate ASICs [p. 628]
Lai, F.
8A-3s A Novel Approach for Digital Waveform Compression [p. 712]
Lai, J.
9D-1 Periodic Steady-State Analysis of Coupled ODE-AE-CGE Systems for MOS RF Autonomous Circuit Simulation [p. 885]
Lai, M.
5A-4s Floorplanning with Power Supply Noise Avoidance [p. 427]
Lai, Y.-T.
2D-5s A Technology Mapping Algorithm for Heterogeneous FPGAs [p. 213]
Larsson-Edefors, P.
5D-5s Full-Custom vs. Standard-Cell Design Flow - an Adder Case Study [p. 507]
8A-4s A Deep Submicron Power Estimation Methodology Adaptable to Variations between Power Characterization and Estimation [p. 716]
Lee, C.-T.
7D-3s Linux Kernel Customization for Embedded Systems by Using Call Graph Approach [p. 689]
Lee, D.-I.
9A-3s Performance Optimization of Synchronous Control Units for Datapaths with Variable Delay Arithmetic Units [p. 816]
Lee, Junghee
1A-4 Memory Access Pattern Analysis and Stream Cache Design for Multimedia Applications [p. 22]
Lee, Jaehwan
7D-2 A Comparison of the RTU Hardware RTOS with a Hardware/Software RTOS [p. 683]
Lee, J.-G.
9A-3s Performance Optimization of Synchronous Control Units for Datapaths with Variable Delay Arithmetic Units [p. 816]
Lee, J.-J.
5D-1s Implementation of the Super-Systolic Array for Convolution [p. 491]
Lee, S.-H.
5D-8s Branch Predictor Design and Performance Estimation for a High Performance Embedded Microprocessor [p. 519]
Lee, Y.-M.
7A-5 A Hierarchical Analysis Methodology for Chip-Level Power Delivery with Realizable Model Reduction [p. 614]
Lekastas, H.
1A-3 Multi-Parametric Improvements for Embedded Systems Using Code-Placement and Address Bus Coding [p. 15]
Li, D.
7D-4s Topology Selection for Energy Minimization in Embedded Networks [p. 693]
Li, H.
4C-1 Efficient LUT-Based FPGA Technology Mapping for Power Minimization [p. 353]
Li, P.
9D-2 A Frequency Separation Macromodel for System-Level Simulation of RF Circuits [p. 891]
9D-3 Nonlinear Distortion Analysis via Linear-Centric Models [p. 897] [p. 897]
Li, S.-M.
5A-3s Noise-Aware Buffer Planning for Interconnect-Driven Floorplanning [p. 423]
Li, X.
9D-2 A Frequency Separation Macromodel for System-Level Simulation of RF Circuits [p. 891]
Li, Z.
8B-1 Congestion Driven Incremental Placement Algorithm for Standard Cell Layout [p. 723]
Lienig, J.
8D-2 Current-Driven Wire Planning for Electromigration Avoidance in Analog Circuits [p. 783]
Lin, C.-H.
8D-4 5Gbps Serial Link Transmitter with Pre-emphasis [p. 795]
Lin, C.-T.
4A-5s Non-slicing Floorplans with Boundary Constraints Using Generalized Polish Expression [p. 342]
Lin, Jai-Ming
9B-5s Graph Matching-Based Algorithms for Array-Based FPGA Segmentation Design and Routing [p. 851]
Lin, Jim-Min
7D-3s Linux Kernel Customization for Embedded Systems by Using Call Graph Approach [p. 689]
Lin, T.-F.
6D-2 A Highly Efficient AES Cipher Chip [p. 561]
Lindh, L.
7D-2 A Comparison of the RTU Hardware RTOS with a Hardware/Software RTOS [p. 683]
Liu, C.-N.J.
7A-4s An Efficient IP-Level Power Model for Complex Digital Circuits [p. 610]
Liu, D.
6D-3 Implementation of Fast CRC Calculation [p. 563]
Liu, I.-M.
5A-4s Floorplanning with Power Supply Noise Avoidance [p. 427]
Liu, Jian
1D-4s Transaction-based Waveform Analysis for IP Selection [p. 104]
Liu, Jianguo
3B-4 Improving Boundary Element Methods for Parasitic Extraction [p. 261]
Liu, Jiping
4C-3s On Improving FPGA Routability Applying Multi-level Switch Boxes [p. 366]
Liu, J.-J.
8C-1 Experience in Critical Path Selection for Deep Sub-Micron Delay Test and Timing Validation [p. 751]
Liu, J.-S.
6D-12 Low-Power Digital CDMA Receiver [p. 581]
Liu, X.
7A-3s HyPE: Hybrid Power Estimation for IP-Based Programmable Systems [p. 606]
Lou, J.
8B-3 Cross Talk Driven Placement [p. 735]
Lu, T.
3B-3 BBE: Hierarchical Computation of 3-D Interconnect Capacitance with BEM Block Extraction [p. 255]

M

Ma, Y.
5A-6s A Buffer Planning Algorithm Based on Dead Space Redistribution [p. 435]
Mak, W.-K.
4C-1 Efficient LUT-Based FPGA Technology Mapping for Power Minimization [p. 353]
Mándoiu, I.I.
9B-1 Highly Scalable Algorithms for Rectilinear and Octilinear Steiner Trees [p. 827]
Mantik, S.
9C-1 Routing-Aware Scan Chain Ordering [p. 857]
Marculescu, R.
3A-2 Towards On-Chip Fault-Tolerant Communication [p. 225]
3A-3 Energy-Aware Mapping for Tile-based NoC Architectures under Performance Constraints [p. 233]
Markov, I.L.
3D-1 Gate-Level Simulation of Quantum Circuits [p. 295]
Martina, M.
5D-3s A Reconfigurable, Power-Scalable Rake Receiver IP for W-CDMA [p. 499]
Martinelli, A.
2D-1 A BDD-based Fast Heuristic Algorithm for Disjoint Decomposition [p. 191]
Maruvada, S.C.
8D-1 Using Red-Black Interval Trees in Device-Level Analog Placement with Symmetry Constraints [p. 777]
Marwedel, P.
1C-4 Data Partitioning for Maximal Scratchpad Usage [p. 77]
Masuda, H.
2B-1 Approximate Formulae Approach for Efficient Inductance Extraction [p. 143]
Matsushita, Y.
1B-4s Reduction of Crosstalk Noise by Optimizing 3-D Configuration of Routing Grid [p. 49]
Matsuura, M.
3D-4s Evaluation of Multiple-Output Logic Functions Using Decision Diagrams [p. 312]
Mattausch, H.J.
2C-2 Temperature-Independence-Point Properties for 0.1um-Scale Pocket-Implant Technologies and the Impact on Circuit Design [p. 179]
6D-17 A Nearest-Hamming-Distance Search Memory with Fully Parallel Mixed Digital-Analog Match Circuitry [p. 591]
Maulik, U.
9C-4s Efficient BIST Design for Sequential Machines Using FiF-FoF Values in Machines States [p. 875]
McDougall, T.
8C-4 SLV/ATPG: an Automated Flow for Test Model Generation from Switch Level Custom Circuits [p. 769]
Mchaalia, S.
8A-3s A Novel Approach for Digital Waveform Compression [p. 712]
Meeus, W.
6D-13 Hardware Implementation of an EAN-13 Bar Code Decoder [p. 583]
Mehrotra, A.
7B-4 Design Flow and Methodology for 50M gate ASIC [p. 640]
Mir, S.
7C-3 An Implementation of Memory-based On-chip Analogue Test Signal Generation [p. 663]
Miura-Mattausch, M.
2C-2 Temperature-Independence-Point Properties for 0.1um-Scale Pocket-Implant Technologies and the Impact on Circuit Design [p. 179]
Miyaoka, Y.
2A-4 A Hardware/Software Partitioning Algorithm for SIMD Processor Cores [p. 135]
Mneimneh, M.
1D-1 SAT-based Sequential Depth Computation [p. 87]
Mochizuki, K.
6D-5 A Still Image Encoder Based on Adaptive Resolution Vector Quantization Employing Needless Calculation Elimination Architecture [p. 567]
Molino, A.
5D-3s A Reconfigurable, Power-Scalable Rake Receiver IP for W-CDMA [p. 499]
Mooney III, V. J.
7D-2 A Comparison of the RTU Hardware RTOS with a Hardware/Software RTOS [p. 683]
Morita, T.
6D-14 Error Correction Circuit using Difference-set Cyclic Code [p. 585]
Morizawa, R. K.
5B-2 Synthesis for SoC Architecture Using VCores [p. 446]
5B-4 VCDS Tool Demonstration [p. 459]
Munoz, J.
5C-1 DARPA's Adaptive Computing Systems Program [p. 464]
Muraoka, M.
5B-1 VCore Based Design Methodology [p. 441]
5B-2 Synthesis for SoC Architecture Using VCores [p. 446]
5B-3 VCore Based Platform for SoC Design [p. 453]
5B-4 VCDS Tool Demonstration [p. 459]

N

Nakajima,459] K.
4C-5 Logic Foundry: Rapid Prototyping of FPGA-based DSP Systems [p. 374]
Nakamura, H.
2D-2 Logic Optimization for Asynchronous Speed Independent Controllers Using Transduction Method [p. 197]
9A-3s Performance Optimization of Synchronous Control Units for Datapaths with Variable Delay Arithmetic Units [p. 816]
Nakano, K.
4C-4s An Image Retrieval System Using FPGAs [p. 370]
Nakayama, N.
2C-2 Temperature-Independence-Point Properties for 0.1um-Scale Pocket-Implant Technologies and the Impact on Circuit Design [p. 179]
Nakayama, T.
6D-5 A Still Image Encoder Based on Adaptive Resolution Vector Quantization Employing Needless Calculation Elimination Architecture [p. 567]
Nano, H.
6D-8 The Design of a USB Device Controller IYOYOYO [p. 573]
Nanya, T.
2D-2 Logic Optimization for Asynchronous Speed Independent Controllers Using Transduction Method [p. 197]
9A-3s Performance Optimization of Synchronous Control Units for Datapaths with Variable Delay Arithmetic Units [p. 816]
Naroska, E.
8A-3s A Novel Approach for Digital Waveform Compression [p. 712]
Nassif, S.R.
3C-2 Predicting Short Circuit Power from Timing Models [p. 277]
Nekili, M.
3B-1 Adaptive Wire Adjustment for Bounded Skew Clock Distribution Network [p. 243]
Nishi, H.
5B-1 VCore Based Design Methodology [p. 441]
5B-2 Synthesis for SoC Architecture Using VCores [p. 446]
Nomoto, K.
8C-3 DFT Timing Design Methodology for At-Speed BIST [p. 763]
Nozawa, T.
6D-5 A Still Image Encoder Based on Adaptive Resolution Vector Quantization Employing Needless Calculation Elimination Architecture [p. 567]

O

Ogawa, R.
6D-9 MAPLE Chip: a Processing Element for a Static Scheduling Centric Multiprocessor [p. 575]
Ohmi, T.
6D-5 A Still Image Encoder Based on Adaptive Resolution Vector Quantization Employing Needless Calculation Elimination Architecture [p. 567]
Ohtsuki, T.
2A-4 A Hardware/Software Partitioning Algorithm for SIMD Processor Cores [p. 135]
Oka, H.
2B-2 Accurate Prediction of the Impact of On-chip Inductance on Interconnect Delay using Electrical and Physical Parameter-based RSF [p. 149]
Okada, K.
1B-1 A Statistical Gate Delay Model for Intra-chip and Inter-chip Variabilities [p. 31]
Ong, C.-K.
7C-4 Delta-sigma Modulator Based Mixed-signal BIST Architecture for SoC [p. 669]
Onishi, Y.
5B-1 VCore Based Design Methodology [p. 441]
5B-3 VCore Based Platform for SoC Design [p. 453]
Onodera, H.
1B-1 A Statistical Gate Delay Model for Intra-chip and Inter-chip Variabilities [p. 31]
6D-16 Standard Cell Libraries with Various Driving Strength Cells for 0.13, 0.18 and 0.35um Technologies [p. 589]
Oshima, Y.
6C-1 Legal Protection for Semiconductor Intellectual Property (IP) [p. 551]

P

Pal, A.
2D-4s Synthesis of High Performance Low Power PTL Circuits [p. 209]
Pan, S.-R.
9B-5s Graph Matching-Based Algorithms for Array-Based FPGA Segmentation Design and Routing [p. 851]
Panda, R.
3C-1 Statistical Delay Computation Considering Spatial Correlations [p. 271]
Pandey, M.
3D-2 Enhanced Symbolic Simulation for Efficient Verification of Embedded Array Systems [p. 302]
Papaefthymiou, M.C.
7A-3s HyPE: Hybrid Power Estimation for IP-Based Programmable Systems [p. 606] [p. 606]
Parameswaran, S.
1A-3 Multi-Parametric Improvements for Embedded Systems Using Code-Placement and Address Bus Coding [p. 15]
Parashkevov, A.N.
8C-4 SLV/ATPG: an Automated Flow for Test Model Generation from Switch Level Custom Circuits [p. 769]
Park, C.
1A-4 Memory Access Pattern Analysis and Stream Cache Design for Multimedia Applications [p. 22]
Park, J.
9D-4 Parasitic-Aware Design and Optimization of a Fully Integrated CMOS Wideband Amplifier [p. 904]
Parker, R.
5C-2 Applications of Adaptive Computing Systems for Signal Processing Challenges [p. 465]
Pedram, M.
1A-1 BEAM: Bus Encoding Based on Instruction-Set-Aware Memories [p. 3]
1B-3 Calculating the Effective Capacitance for the RC Interconnect in VDSM Technologies [p. 43]
2D-3 Technology Mapping for Low Leakage Power and High Speed with Hot-Carrier Effect Consideration [p. 203]
9A-1 Low Power Synthesis of Finite State Machines with Mixed D and T Flip-Flops [p. 803]
Pileggi L.
9D-2 A Frequency Separation Macromodel for System-Level Simulation of RF Circuits [p. 891]
9D-3 Nonlinear Distortion Analysis via Linear-Centric Models [p. 897]
Potkonjak, M.
1C-1 An On-line Approach for Power Minimization in QoS Sensitive Systems [p. 59]
Pyron, C.
8C-4 SLV/ATPG: an Automated Flow for Test Model Generation from Switch Level Custom Circuits [p. 769]

Q

Qi, X.
8B-4s VLSI Module Placement with Pre-placed Modules and Considering Congestion Using Solution Space Smoothing [p. 741]
Qin, Z.
3C-3 RCLK-VJ Network Reduction with Hurwitz Polynomial Approximation [p. 283]
Qu, G.
1C-1 An On-line Approach for Power Minimization in QoS Sensitive Systems [p. 59]

R

Rajagopalan, M.
3D-1 Gate-Level Simulation of Quantum Circuits [p. 295]
Rao, C.V.G.
9C-5s A New Design-for-Test Technique for Reducing SOC Test Time [p. 879]
Reif, R.
1B-5s Design Tools for 3-D Integrated Circuits [p. 53]
Ren, J.
9D-1 Periodic Steady-State Analysis of Coupled ODE-AE-CGE Systems for MOS RF Autonomous Circuit Simulation [p. 885]
Rezvani, P.
9A-1 Low Power Synthesis of Finite State Machines with Mixed D and T Flip-Flops [p. 803]
Roh, J.
7C-1 Efficient Loop-back Testing of On-chip ADCs and DACs [p. 651]
Rolíndez, L.
7C-3 An Implementation of Memory-based On-chip Analogue Test Signal Generation [p. 663]
Roy, K.
2B-3 A Metric for Analyzing Effective On-Chip Inductive Coupling [p. 156]
5D-4s Robust High-Performance Low-Power Carry Select Adder [p. 503]
9A-4s Integer Linear Programming-Based Synthesis of Skewed Logic Circuits [p. 820]
Roy, Sumit
3B-2 Power Minimization by Clock Root Gating [p. 249]
Roy, S.
9C-4s Efficient BIST Design for Sequential Machines Using FiF-FoF Values in Machines States [p. 875]
Ruan, S.-J.
8A-3s A Novel Approach for Digital Waveform Compression [p. 712]
Rufer, L.
7C-3 An Implementation of Memory-based On-chip Analogue Test Signal Generation [p. 663]

S

Saaied, H.
3B-1 Adaptive Wire Adjustment for Bounded Skew Clock Distribution Network [p. 243]
Sakiyama, K.
6D-10 Finding the Best System Design Flow for a High Speed JPEG Encoder [p. 577]
Saito, H.
2D-2 Logic Optimization for Asynchronous Speed Independent Controllers Using Transduction Method [p. 197]
9A-3s Performance Optimization of Synchronous Control Units for Datapaths with Variable Delay Arithmetic Units [p. 816]
Sakai, A.
1B-4s Reduction of Crosstalk Noise by Optimizing 3-D Configuration of Routing Grid [p. 49]
Sakallah, K.
1D-1 SAT-based Sequential Depth Computation [p. 87]
Sakanushi, K.
4A-4s An Extended Representation of Q-sequence for Optimizing Channel-Adjacency and Routing-Cost [p. 338]
Sakiyama, K.
6D-10 Finding the Best System Design Flow for a High Speed JPEG Encoder [p. 577]
Samanta, D.
2D-4s Synthesis of High Performance Low Power PTL Circuits [p. 209]
Samet, F.
3A-1 Combining Architecture Exploration and a Path to Implementation to Build a Complete SoC Design Flow from System Specification to RTL [p. 219]
Sanchez-Elez, M.
5C-3 Interactive Ray Tracing on Reconfigurable SIMD MorphoSys [p. 471]
Sarrafzadeh, M.
4C-2 Optimal Reconfiguration Sequence Management [p. 359]
Sasao, T.
3D-4s Evaluation of Multiple-Output Logic Functions Using Decision Diagrams [p. 312]
Sato, M.
8C-3 DFT Timing Design Methodology for At-Speed BIST [p. 763]
Sato, T.
2B-1 Approximate Formulae Approach for Efficient Inductance Extraction [p. 143]
2B-2 Accurate Prediction of the Impact of On-chip Inductance on Interconnect Delay using Electrical and Physical Parameter-based RSF [p. 149]
Sato, Y.
8C-3 DFT Timing Design Methodology for At-Speed BIST [p. 763]
Schaumont, P.
6D-10 Finding the Best System Design Flow for a High Speed JPEG Encoder [p. 577]
Schott, B.
5C-2 Applications of Adaptive Computing Systems for Signal Processing Challenges [p. 465]
Schwiegelshohn, U.
8A-3s A Novel Approach for Digital Waveform Compression [p. 712]
Sha, E.
1C-3 Register Aware Scheduling for Distributed Cache Clustered Architecture [p. 71]
Sham, C.-w.
5A-2 Interconnect-Driven Floorplanning by Searching Alternative Packings [p. 417]
Shao, M.
1B-2 A Fast and Accurate Method for Interconnect Current Calculation [p. 37]
Shi, C.-J.R.
8D-3 Efficient DDD-based Term Generation Algorithm for Analog Circuit Behavioral Modeling [p. 789]
Shi, W.
3B-4 Improving Boundary Element Methods for Parasitic Extraction [p. 261]
Shi, Y.
9C-2 Multiple Test Set Generation Method for LFSR-Based BIST [p. 863]
Shimizu, N.
6D-7 The Design of a i8080A Instruction Compatible Processor with Extended Memory Address [p. 571]
6D-8 The Design of a USB Device Controller IYOYOYO [p. 573]
6D-11 The Design of PCI Bus Interface [p. 579]
Shinsha, T.
5B-4 VCDS Tool Demonstration [p. 459]
Shragowitz, E.
1D-4s Transaction-based Waveform Analysis for IP Selection [p. 104]
Shukla, S.K.
2A-1 Typing Abstractions and Management in a Component Framework [p. 115]
Sikdar, B.K.
9C-4s Efficient BIST Design for Sequential Machines Using FiF-FoF Values in Machines States [p. 875]
Sirisantana, N.
9A-4s Integer Linear Programming-Based Synthesis of Skewed Logic Circuits [p. 820]
Smith, A.
1D-2 Logic Verification Based on Diagnosis Techniques [p. 93]
Soda, Y.
6D-17 A Nearest-Hamming-Distance Search Memory with Fully Parallel Mixed Digital-Analog Match Circuitry [p. 591]
Song, G.-Y.
5D-1s Implementation of the Super-Systolic Array for Convolution [p. 491]
Spivey, G.
4C-5 Logic Foundry: Rapid Prototyping of FPGA-based DSP Systems [p. 374]
Srinivas, M.B.
6D-6 Speech Encoding and Encryption in VLSI [p. 569]
6D-15 Design of a Digital CDMA Receiver [p. 587]
Srivastava, A.
4D-4s Minimizing Total Power by Simultaneous Vdd/Vth Assignment [p. 400]
Steger, C.
7A-1 Run-Time Energy Estimation in System-On-a-Chip Designs [p. 595]
Steinke, S.
1C-4 Data Partitioning for Maximal Scratchpad Usage [p. 77]
Stroobandt, D.
6D-13 Hardware Implementation of an EAN-13 Bar Code Decoder [p. 583]
Su, C.
7C-2 A Novel LCD Driver Testing Technique Using Logic Test Channel [p. 657]
Su, C.-P.
5D-2s Design of a Scalable RSA and ECC Crypto-Processor [p. 495]
6D-2 A Highly Efficient AES Cipher Chip [p. 561]
Sugawa, S.
6D-5 A Still Image Encoder Based on Adaptive Resolution Vector Quantization Employing Needless Calculation Elimination Architecture [p. 567]
Sun, M.-C.
5D-2s Design of a Scalable RSA and ECC Crypto-Processor [p. 495]
Sundareswaran, S.
3C-1 Statistical Delay Computation Considering Spatial Correlations [p. 271]
Suzuki, M.
2C-3 Behavioral Modeling of EM Devices by Selective Orthogonal Matrix Least-Squares Method [p. 184]
Svensson, C.
5D-5s Full-Custom vs. Standard-Cell Design Flow - an Adder Case Study [p. 507]
Sylvester, D.
4D-4s Minimizing Total Power by Simultaneous Vdd/Vth Assignment [p. 400]
Sze, C.N.
8B-2 Performance-Driven Multi-Level Clustering for Combinational Circuits [p. 729]

T

Tabrizi, N.
5C-3 Interactive Ray Tracing on Reconfigurable SIMD MorphoSys [p. 471]
Tachikake, K.
2A-4 A Hardware/Software Partitioning Algorithm for SIMD Processor Cores [p. 135]
Tada, T.
5B-1 VCore Based Design Methodology [p. 441]
Takamichi, E.
4C-4s An Image Retrieval System Using FPGAs [p. 370]
Takeoka, S.
8C-2 On Effective Criterion of Path Selection for Delay Testing [p. 757]
Tan, S.X.-D.
8D-3 Efficient DDD-based Term Generation Algorithm for Analog Circuit Behavioral Modeling [p. 789]
Tanaka, K.
5B-4 VCDS Tool Demonstration [p. 459]
Tanaka, M.
2C-2 Temperature-Independence-Point Properties for 0.1um-Scale Pocket-Implant Technologies and the Impact on Circuit Design [p. 179]
Tanji, Y.
2C-3 Behavioral Modeling of EM Devices by Selective Orthogonal Matrix Least-Squares Method [p. 184]
Tayu, S.
4A-1 A Simulated Annealing Approach with Sequence-Pair Encoding Using a Penalty Function for the Placement Problem with Boundary Constraints [p. 319]
Teich, J.
6A-1 Accelerating Design Space Exploration Using Pareto-Front Arithmetics [p. 525]
Tiwari, A.
8A-2 Scan-chain Based Watch-points for Efficient Run-Time Debugging and Verification of FPGA Designs [p. 705]
Togawa, N.
2A-4 A Hardware/Software Partitioning Algorithm for SIMD Processor Cores [p. 135]
Tomko, K.A.
8A-2 Scan-chain Based Watch-points for Efficient Run-Time Debugging and Verification of FPGA Designs [p. 705]
Trivedi, Y.
7B-4 Design Flow and Methodology for 50M gate ASIC [p. 640]
Tsai, Y.-C.
6D-12 Low-Power Digital CDMA Receiver [p. 581]
Tseng, I.
7C-2 A Novel LCD Driver Testing Technique Using Logic Test Channel [p. 657]
Tsubaki, N.
5B-3 VCore Based Platform for SoC Design [p. 453]
Tsukahara, T.
4D-3 Design Methodology of Low-Power CMOS RF-ICs [p. 394]
Tsutsumida, K.
8C-3 DFT Timing Design Methodology for At-Speed BIST [p. 763]
Tung, S.-W.
1D-5s An Automatic Interconnection Rectification Technique for SoC Design Integration [p. 108]

U

Ueno, H.
2C-2 Temperature-Independence-Point Properties for 0.1um-Scale Pocket-Implant Technologies and the Impact on Circuit Design [p. 179]
Ugajin, M.
4D-3 Design Methodology of Low-Power CMOS RF-ICs [p. 394]
Utsuki, M.
5B-3 VCore Based Platform for SoC Design [p. 453]

V

Vacca, F.
5D-3s A Reconfigurable, Power-Scalable Rake Receiver IP for W-CDMA [p. 499]
van Ginneken, L.
7B-4 Design Flow and Methodology for 50M gate ASIC [p. 640]
Veneris, A.
1D-2 Logic Verification Based on Diagnosis Techniques [p. 93]
Verbauwhede, I.M.
6D-10 Finding the Best System Design Flow for a High Speed JPEG Encoder [p. 577]
Verma, M.
1C-4 Data Partitioning for Maximal Scratchpad Usage [p. 77]
Verplaetse, P.
6D-13 Hardware Implementation of an EAN-13 Bar Code Decoder [p. 583]
Viamontes, G.F.
3D-1 Gate-Level Simulation of Quantum Circuits [p. 295]

W

Wagner, F.R.
3A-1 Combining Architecture Exploration and a Path to Implementation to Build a Complete SoC Design Flow from System Specification to RTL [p. 219]
Wang, A.
2C-1 Recent Developments in ESD Protection for RF ICs [p. 171]
Wang, Chih-Hu
7C-2 A Novel LCD Driver Testing Technique Using Logic Test Channel [p. 657]
Wang, Chun-Hong
8D-4 5Gbps Serial Link Transmitter with Pre-emphasis [p. 795]
Wang, C.-Y.
1D-5s An Automatic Interconnection Rectification Technique for SoC Design Integration [p. 108]
Wang, J.
5D-6s A 500-MHz Low-Power Five-Port CMOS Register File [p. 511]
Wang, L.-C.
3D-2 Enhanced Symbolic Simulation for Efficient Verification of Embedded Array Systems [p. 302]
7C-4 Delta-sigma Modulator Based Mixed-signal BIST Architecture for SoC [p. 669]
8C-1 Experience in Critical Path Selection for Deep Sub-Micron Delay Test and Timing Validation [p. 751]
Wang, Q.
3B-2 Power Minimization by Clock Root Gating [p. 249]
Wang, R.
8B-4s VLSI Module Placement with Pre-placed Modules and Considering Congestion Using Solution Space Smoothing [p. 741]
Wang, T.-C.
8B-2 Performance-Driven Multi-Level Clustering for Combinational Circuits [p. 729]
Wang, W.-J.
7C-2 A Novel LCD Driver Testing Technique Using Logic Test Channel [p. 657]
Wang, Y.-W.
4A-5s Non-slicing Floorplans with Boundary Constraints Using Generalized Polish Expression [p. 342]
Wang, Zeyi
3B-3 BBE: Hierarchical Computation of 3-D Interconnect Capacitance with BEM Block Extraction [p. 255]
Wang, Zhong
1C-3 Register Aware Scheduling for Distributed Cache Clustered Architecture [p. 71]
Watanabe, K.
5B-4 VCDS Tool Demonstration [p. 459]
Watanabe, K.-i.
9C-3 A Seed Selection Procedure for LFSR-Based Random Pattern Generators [p. 869]
Watanabe, T.
2C-3 Behavioral Modeling of EM Devices by Selective Orthogonal Matrix Least-Squares Method [p. 184]
Weiss, R.
7A-1 Run-Time Energy Estimation in System-On-a-Chip Designs [p. 595]
Wing, O.
9D-1 Periodic Steady-State Analysis of Coupled ODE-AE-CGE Systems for MOS RF Autonomous Circuit Simulation [p. 885]
Wong, D.F.
1B-2 A Fast and Accurate Method for Interconnect Current Calculation [p. 37]
5A-4s Floorplanning with Power Supply Noise Avoidance [p. 427]
Wong, J. L.
1C-1 An On-line Approach for Power Minimization in QoS Sensitive Systems [p. 59]
Wong, K.W.C.
5A-1 Fast Buffer Planning and Congestion Optimization in Interconnect-driven Floorplanning [p. 411]
Wu, C.-W.
5D-2s Design of a Scalable RSA and ECC Crypto-Processor [p. 495]
6D-2 A Highly Efficient AES Cipher Chip [p. 561]
Wu, W.
8B-1 Congestion Driven Incremental Placement Algorithm for Standard Cell Layout [p. 723] [p. 723]
8B-5s A Path-based Timing-driven Quadratic Placement Algorithm [p. 745]
Wu, X.
9D-1 Periodic Steady-State Analysis of Coupled ODE-AE-CGE Systems for MOS RF Autonomous Circuit Simulation [p. 885]
Wu, Y.-L.
4C-3s On Improving FPGA Routability Applying Multi-level Switch Boxes [p. 366]

X

Xie, M.
7B-1 Optimality and Scalability Study of Existing Placement Algorithms [p. 621]
Xu, J.
9B-2 UTACO: a Unified Timing and Congestion Optimizing Algorithm for Standard Cell Global Routing [p. 834]
9B-4s A Novel Timing-Driven Global Routing Algorithm Considering Coupling Effects for High Performance Circuit Design [p. 847]
Xu, Y.
9D-2 A Frequency Separation Macromodel for System-Level Simulation of RF Circuits [p. 891]

Y

Yamada, T.
1B-4s Reduction of Crosstalk Noise by Optimizing 3-D Configuration of Routing Grid [p. 49]
Yamagishi, A.
4D-3 Design Methodology of Low-Power CMOS RF-ICs [p. 394]
Yamaguchi, T.
2C-2 Temperature-Independence-Point Properties for 0.1um-Scale Pocket-Implant Technologies and the Impact on Circuit Design [p. 179]
Yamaoka, K.
1B-1 A Statistical Gate Delay Model for Intra-chip and Inter-chip Variabilities [p. 31]
Yamashita, K.
2C-2 Temperature-Independence-Point Properties for 0.1um-Scale Pocket-Implant Technologies and the Impact on Circuit Design [p. 179]
Yan, S.
3B-4 Improving Boundary Element Methods for Parasitic Extraction [p. 261]
Yanagisawa, M.
2A-4 A Hardware/Software Partitioning Algorithm for SIMD Processor Cores [p. 135]
Yang, C.-H.
6D-1 Design and Implementation of a Video-Oriented Network-Interface-Card System [p. 559]
Yano, Y.
6D-17 A Nearest-Hamming-Distance Search Memory with Fully Parallel Mixed Digital-Analog Match Circuitry [p. 591]
Yao, B.
9B-3 The Y-Architecture: Yet Another On-Chip Interconnect Solution [p. 840]
Yasuda, T.
4D-5s A Low Power CMOS Circuit with Variable Source Scheme (VSCMOS) [p. 404]
Yasufuku, K.
6D-9 MAPLE Chip: a Processing Element for a Static Scheduling Centric Multiprocessor [p. 575]
Yasuura, H.
1B-4s Reduction of Crosstalk Noise by Optimizing 3-D Configuration of Routing Grid [p. 49]
6A-2 Quality-Driven Design by Bitwidth Optimization for Video Applications [p. 532]
Yokota, H.
5B-2 Synthesis for SoC Architecture Using VCores [p. 446]
Yoshida, K.
5B-1 VCore Based Design Methodology [p. 441]
Yoshimura, S.
8C-2 On Effective Criterion of Path Selection for Delay Testing [p. 757]
Young, E.F.Y.
5A-1 Fast Buffer Planning and Congestion Optimization in Interconnect-driven Floorplanning [p. 411]
5A-2 Interconnect-Driven Floorplanning by Searching Alternative Packings [p. 417]
Yu, H.-s.
7C-1 Efficient Loop-back Testing of On-chip ADCs and DACs [p. 651]
Yuan, L.-P.
1B-2 A Fast and Accurate Method for Interconnect Current Calculation [p. 37]
Yuan, X.
4A-2 Multi-level Placement for Large-Scale Mixed-Size IC Designs [p. 325]

Z

Zelikovsky, A.Z.
9B-1 Highly Scalable Algorithms for Rectilinear and Octilinear Steiner Trees [p. 827]
Zeng, J.
8C-4 SLV/ATPG: an Automated Flow for Test Model Generation from Switch Level Custom Circuits [p. 769]
Zhang, Q.
5D-6s A 500-MHz Low-Power Five-Port CMOS Register File [p. 511]
9D-1 Periodic Steady-State Analysis of Coupled ODE-AE-CGE Systems for MOS RF Autonomous Circuit Simulation [p. 885]
Zhang, Y.
1C-2 Energy Minimization of Real-time Tasks on Variable Voltage Processors with Transition Energy Overhead [p. 65]
Zhang, Z.
9C-2 Multiple Test Set Generation Method for LFSR-Based BIST [p. 863]
Zhao, M.
3C-1 Statistical Delay Computation Considering Spatial Correlations [p. 271]
Zhong, G.
2B-3 A Metric for Analyzing Effective On-Chip Inductive Coupling [p. 156]
Zhou, F.
9B-3 The Y-Architecture: Yet Another On-Chip Interconnect Solution [p. 840]
Zhou, H.
5A-2 Interconnect-Driven Floorplanning by Searching Alternative Packings [p. 417]
Zhu, J.
8C-4 SLV/ATPG: an Automated Flow for Test Model Generation from Switch Level Custom Circuits [p. 769]
Zhuang, C.
4A-4s An Extended Representation of Q-sequence for Optimizing Channel-Adjacency and Routing-Cost [p. 338]
Zolotov, V.
3C-1 Statistical Delay Computation Considering Spatial Correlations [p. 271]