TABLE OF CONTENTS DAC '95

Executive Committee
General Chair's Welcome
Technical Program Committee
ACM Awards/Fellows and IEEE Fellows
1995 Best Paper Award
Design Automation Conference Scholarship Awards
Reviewers
1995 Keynote Address--A. Richard Newton

*Best Paper Award Candidate

Session 1 Panel: Executive Perspective on the Future of the EDA Industry and Design Technology

Session 2 Design of UltraSPARC

2.1 A Fast and Flexible Performance Simulator for Micro-Architecture Trade-off Analysis on UltraSPARC(TM)-I
Marc Tremblay, Guillermo Maturana, Atsushi Inoue, Les Kohn

2.2 System Design Methodology of UltraSPARC(TM)-I
Lawrence Yang, David Gao, Jamshid Mostoufi, Raju Joshi, Paul Loewenstein

2.3 UltraSPARC(TM)™-I Emulation
James Gateley, Miriam Blatt, Dennis Chen, Scott Cooke, Piyush Desai, Manjunath Doreswamy, Mark Elgood, Gary Feierbach, , Tim Goldsbury, Dale Greenley, Raju Joshi, Mike Khosraviani, Robert Kwong, Manish Motwani, Chitresh Narasimhaiah, Sam J. Nicolino Jr., Tooru Ozeki, Gary Peterson, Chris Salzmann, Nasser Shayesteh, Jeffrey Whitman, Pak Wong

2.4 CAD Methodology for the Design of UltraSPARC(TM)-I Microprocessor at Sun Microsystems Inc.
A.Cao, A.Adalal, J.Bauman, P.Delisle, P.Dedood, P.Donehue, M.Dell'Oca Khouja, T.Doan, M.Doreswamy, P.Ferolito, O.Geva, D.Greenhill, S.Gopaladhine, J.Irwin, L.Lev, J.MacDonald, M.Ma, S.Mitra, P.Patel, A.Prabhu, R.Puranik, S.Rozanski, N.Ross, P.Saggurti, S.Simovich, R.Sunder, B.Sur, W.Vercruysse, M.Wong, P.Yip, R.Yu, J.Zhou, G.Zyner

Session 3 Power Considerations in Synthesis

3.1 Computing the Maximum Power Cycles of a Sequential Circuit
Srilatha Manne, Abelardo Pardo, R. Iris Bahar, Gary D. Hachtel, Fabio Somenzi, Enrico Macii, Massimo Poncino

3.2 Register Allocation and Binding for Low Power
Jui-Ming Chang, Massoud Pedram

3.3 Memory Segmentation to Exploit Sleep Mode Operation
Amir H. Farrahi, Gustavo E. Téllez, Majid Sarrafzadeh

3.4 Power-Profiler: Optimizing ASICs Power Consumption at the Behavioral Level
Raul San Martin, John P. Knight

Session 4 Technology and Layout Dependent Synthesis

4.1 Boolean Matching for Incompletely Specified Functions*
Kuo-Hua Wang, TingTing Hwang

4.2 Functional Multiple-Output Decomposition: Theory and an Implicit Algorithm*
Bernd Wurth, Klaus Eckl, Kurt Antreich

4.3 A Method for Finding Good Ashenhurst Decompositions and Its Application to FPGA Synthesis
Ted Stanion, Carl Sechen

4.4 Lambda Set Selection in Roth-Karp Decomposition for LUT-Based FPGA Technology Mapping
Wen-Zen Shen, Juinn-Dar Huang, Shih-Min Chao

4.5 Minimizing the Routing Cost during Logic Extraction
Hirendu Vaishnav, Massoud Pedram

Session 5 Issues in EDA Frameworks

5.1 Requirements-Based Design Evaluation
Stephen T. Frezza, Steven P. Levitan, Panos K. Chrysanthis

5.2 Incorporating Design Schedule Management into a Flow Management System
Eric W. Johnson, Jay B. Brockman

5.3 Generating ECAD Framework Code from Abstract Models
Joachim Altmeyer, Bernd Schürmann, Martin Schütze

5.4 Tool Integration and Construction Using Generated Graph-Based Design Representations
Ansgar Bredenfeld, Raul Camposano

Session 6 Panel: Managing Design Change - Lessons Learned

Session 7 Scheduling and Retiming in Architectural Synthesis

7.1Scheduling Using Behavioral Templates*
Tai Ly, David Knapp, Ron Miller, Don MacMillen

7.2 Rephasing: A Transformation Technique for the Manipulation of Timing Constraints*
Miodrag Potkonjak, Mani Srivastava

7.3 Optimal ILP-Based Approach for Throughput Optimization Using Simultaneous Algorithm/Architecture Matching and Retiming
Y.G. DeCastelo-Vide-e-Souza, M. Potkonjak Alice C. Parker

Session 8 Delay Test and Diagnosis

8.1 Fast Identification of Robust Dependent Path Delay Faults
U. Sparmann, D. Luxenburger, K.-T. Cheng, S.M. Reddy

8.2 On Synthesis-for-Testability of Combinational Logic Circuits
Irith Pomeranz, Sudhakar M. Reddy

8.3 Rapid Diagnostic Fault Simulation of Stuck-at Faults in Sequential Circuits Using Compact Lists
Srikanth Venkataraman, Ismed Hartanto, W. Kent Fuchs, Elizabeth M. Rudnick, Sreejit Chakravarty, Janak H. Patel

Session 9 Discrete-Event Simulation

9.1 Tutorial: Parallel Logic Simulation of VLSI Systems
Roger D. Chamberlain

9.2 Asynchronous, Distributed Event Driven Simulation Algorithm for Execution of VHDL on Parallel Processors
Peter A. Walker, Sumit Ghosh

9.3 A General Method for Compiling Event-Driven Simulations
Robert S. French, Monica S. Lam, Jeremy R. Levitt, Kunle Olukotun

Session 10 Panel: Power Minimization in IC Design

Session 11 Storage Synthesis and Optimization

11.1 A Transformation-Based Approach for Storage Optimization
Wei-Kai Cheng, Youn-Long Lin

11.2 Register Minimization beyond Sharing among Variables
Tsung-Yi Wu, Youn-Long Lin

11.3 Constrained Register Allocation in Bus Architectures
Elof Frank, Salil Raje, Majid Sarrafzadeh

Session 12 Retiming and Sequential ATPG

12.1 On Test Set Preservation of Retimed Circuits
Aiman El-Maleh, Thomas Marchok, Janusz Rajski, Wojciech Maly

12.2 Combining Deterministic and Genetic Approaches for Sequential Circuit Test Generation
Elizabeth M. Rudnick, Janak H. Patel

12.3 Partial Scan with Pre-selected Scan Signals
Peichen Pan, C. L. Liu

Session 13 Partitioning and Placement

13.1 Spectral Partitioning: The More Eigenvectors, the Better*
Charles J. Alpert, So-Zen Yao

13.2 Multi-way Partitioning for Minimum Delay for Look-Up Table Based FPGAs
Prashant Sawkar, Donald Thomas

13.3 Performance-Driven Partitioning Using a Replication Graph Approach
Lung-Tien Liu, Ming-Ter Kuo, Chung-Kuan Cheng, Te C. Hu

13.4 Timing Driven Placement for Large Standard Cell Circuits
William Swartz, Carl Sechen

13.5 Quantified Suboptimality of VLSI Layout Heuristics
Lars W. Hagen, Dennis J.-H. Huang, Andrew B. Kahng

Session 14 Design Case Studies

14.1 Concurrent Design Methodology and Configuration Management of the SIEMENS EWSD - CCS7E Processor System Simulation
Thomas W. Albrecht

14.2 Digital Receiver Design Using VHDL Generation from Data Flow Graphs*
Peter Zepter, Thorsten Grötker, Heinrich Meyr

14.3 Logic Verification Methodology for PowerPC™ Microprocessors
Charles H. Malley, Max Dieudonné

Session 15 Panel: University-Industry Ties: How Can They Be Improved?

Session 16 Low Power Design

16.1 Tutorial: A Survey of Optimization Techniques Targeting Low Power VLSI Circuits
Srinivas Devadas, Sharad Malik

16.2 Logic Extraction and Factorization for Low Power
Sasan Iman, Massoud Pedram

16.3 Timed Shannon Circuits: A Power-Efficient Design Style and Synthesis Tool
Luciano Lavagno, Patrick C. McGeer, Alexander Saldanha, Alberto L. Sangiovanni-Vincentelli

Session 17 Extraction and Module Generation

17.1 The Aurora RAM Compiler
Ajay Chandna, C. David Kibler, Richard B. Brown, Mark Roberts, Karem A. Sakallah

17.2 Automatic Layout Synthesis of Leaf Cells
Sanjay Rekhi, J. Donald Trotter, Daniel H. Linder

17.3 Delayed Frontal Solution for Finite-Element Based Resistance Extraction
N.P. van der Meijs, A.J. van Genderen

Session 18 Advanced Methods in Practice

18.1 Test Program Generation for Functional Verification of PowerPC Processors in IBM*
Aharon Aharon, Dave Goodman, Moshe Levinger, Yossi Lichtenstein, Yossi Malka, Charlotte Metzger, Moshe Molcho, Gil Shurek

18.2Behavioral Synthesis Methodology for HDL-Based Specification and Validation*
D. Knapp, T. Ly, D. MacMillen, R. Miller

18.3 Design-Flow and Synthesis for ASICs: A Case Study
Massimo Bombana, Patrizia Cavalloro, Salvatore Conigliaro, Roger B. Hughes, Gerry Musgrave, Giuseppe Zaza

18.4 Model Checking in Industrial Hardware Design
Jörg Bormann, Jörg Lohse, Michael Payer, Gerd Venzl

Session 19 Sequential Logic Synthesis

19.1 DELAY: An Efficient Tool for Retiming with Realistic Delay Modeling*
Kumar N. Lalgudi, Marios C. Papaefthymiou

19.2 A Fresh Look at Retiming Via Clock Skew Optimization
Rahul B. Deokar, Sachin S. Sapatnekar

19.3 The Validity of Retiming Sequential Circuits
Vigyan Singhal, Carl Pixley, Richard L. Rudell, Robert K. Brayton

19.4 Retiming Synchronous Circuitry with Imprecise Delays
I. Karkowski, R.H.J.M. Otten

19.5 A Fast State Assignment Procedure for Large FSMs
Shihming Liu, Massoud Pedram, Alvin M. Despain

Session 20 Fault Modeling and Simulation

20.1 Software Accelerated Functional Fault Simulation for Data-Path Architectures
M. Kassab, N. Mukherjee, J. Rajski, J. Tyszer

20.2 Symbolic Fault Simulation for Sequential Circuits and the Multiple Observation Time Test Strategy
R. Krieger, B. Becker, M. Keim

20.3 Accurate and Efficient Fault Simulation of Realistic CMOS Network Breaks
Haluk Konuk, F. Joel Ferguson, Tracy Larrabee

20.4 Analysis of Switch-Level Faults by Symbolic Simulation
Lluís Ribas-Xirgo, Jordi Carrabina-Bordoll

Session 21 CAD for Interconnect

21.1 Transmission Line Synthesis
Byron Krauter, Rohini Gupta, John Willis, Lawrence T. Pileggi

21.2 The Elmore Delay as a Bound for RC Trees with Generalized Input Signals
Rohini Gupta, Byron Krauter, Bogdan Tutuianu, John Willis, Lawrence T. Pileggi

21.3 Delay Analysis of the Distributed RC Line
Vasant B. Rao

21.4 Efficient Reduced-Order Modeling of Frequency-Dependent Coupling Inductances Associated with 3-D Interconnect Structures
L. Miguel Silveira, Matton Kamon, Jacob White

21.5 Performance Driven Global Routing and Wiring Rule Generation for High Speed PCBs and MCMs
Sharad Mehrotra, Paul Franzon, Michael Steer

Session 22 Tutorial: ASIC Prototyping

Session 23 Datapath Synthesis and Modeling

23.1 Symbolic Modeling and Evaluation of Data Paths*
Chuck Monahan, Forrest Brewer

23.2 Data Path Allocation for Synthesizing RTL Designs with Low BIST Area Overhead
Ishwar Parulkar, Sandeep Gupta, Melvin A. Breuer

23.3 Deriving Efficient Area and Delay Estimates by Modeling Layout Tools
Donald S. Gelosh, Dorothy E. Setliff

Session 24 Learning and Counterexamples in Formal Verification

24.1 Efficient OBDD-Based Boolean Manipulation in CAD beyond Current Limits
Jochen Bern, Christoph Meinel, Anna Slobodová

24.2 Novel Verification Framework Combining Structural and OBDD Methods in a Synthesis Environment
Subodh M. Reddy, Wolfgang Kunz, Dhiraj K. Pradhan

24.3 Advanced Verification Techniques Based on Learning
Jawahar Jain, Rajarshi Mukherjee, Masahiro Fujita

24.4 Efficient Generation of Counterexamples and Witnesses in Symbolic Model Checking
E. M. Clarke, O. Grumberg, K. L. McMillan, X. Zhao

Session 25 Analog CAD

25.1 DARWIN: CMOS Opamp Synthesis by Means of a Genetic Algorithm*
Wim Kruiskamp, Domine Leenaerts

25.2 Mixed-Signal Switching Noise Analysis Using Voronoi-Tessellated Substrate Macromodels
Ivan L. Wemple, Andrew T. Yang

25.3 Direct Performance-Driven Placement of Mismatch-Sensitive Analog Circuits
K. Lampaert, G. Gielen, W. Sansen

25.4 System-Level Design for Test of Fully Differential Analog Circuits
Bapiraju Vinnakota, Ramesh Harjani, Nicholas J. Stessman

Session 26 Panel: DOS, Windows, UNIX: EDA and the OS Wars

Session 27 Software Analysis and Synthesis

27.1 Performance Analysis of Embedded Software Using Implicit Path Enumeration
Yau-Tsun Steven Li, Sharad Malik

27.2Interval Scheduling: Fine-Grained Code Scheduling for Embedded Systems
Pai Chou, Gaetano Borriello

27.3 Interfacing Incompatible Protocols Using Interface Process Generation
Sanjiv Narayan, Daniel D. Gajski

Session 28 Electrical Simulation

28.1 Reduced-Order Modeling of Large Linear Subcircuits via a Block Lanczos Algorithm*
Peter Feldmann, R. W. Freund

28.2 Efficient Steady-State Analysis Based on Matrix-Free Krylov-Subspace Methods
Ricardo Telichevesky, Kenneth S. Kundert, Jacob K. White

28.3 Transient Simulations of Three-Dimensional Integrated Circuit Interconnect Using a Mixed Surface-Volume Approach
Mike Chou, Tom Korsmeyer, Jacob White

Session 29 Optimization of Clock and Power Distribution

29.1 Buffer Insertion and Sizing under Process Variations for Low Power Clock Distribution*
Joe G. Xi, Wayne W.-M. Dai

29.2 Power Optimal Buffered Clock Tree Design
Ashok Vittal, Malgorzata Marek-Sadowska

29.3 Power Distribution Topology Design
Ashok Vittal, Malgorzata Marek-Sadowska

29.4 On the Bounded-Skew Clock and Steiner Routing Problems
Dennis J.-H. Huang, Andrew B. Kahng, Chung-Wen Albert Tsao

Session 30 Concurrent Engineering

30.1 Benchmarking an Interdisciplinary Concurrent Design Methodology for Electronic/Mechanical Systems*
Asim Smailagic, Daniel P. Siewiorek, Drew Anderson, Chris Kasabach, Tom Martin, John Stivoric

30.2 A Methodology for HW-SW Codesign in ATM
Giovanni Mancini, Dave Yurach, Spiros Boucouris

30.3 Accelerating Concurrent Hardware Design with Behavioural Modelling and System Simulation
Allan Silburt, Ian Perryman, Janick Bergeron, Stacy Nichols, Mario Dufresne, Greg Ward

Session 31 Panel: The ESDA Landscape: Who Will Dominate?

Session 32 Formal Verification of Arithmetic Circuits

32.1 Verification of Arithmetic Circuits with Binary Moment Diagrams*
Randal E. Bryant, Yirng-An Chen

32.2Residue BDD and Its Application to the Verification of Arithmetic Circuits
Shinji Kimura

32.3 Equivalence Checking of Datapaths Based on Canonical Arithmetic Expressions
Zheng Zhou, Wayne Burleson

Session 33 Routing for FPGAs

33.1 On Optimal Board-Level Routing for FPGA-Based Logic Emulation
Wai-Kei Mak, D.F. Wong

33.2 A Performance and Routability Driven Router for FPGAs Considering Path Delays
Yuh-Sheng Lee, Allen C.-H. Wu

33.3 New Performance-Driven FPGA Routing Algorithms
Michael J. Alexander, Gabriel Robins

33.4 Orthogonal Greedy Coupling - A New Optimization Approach to 2-D FPGA Routing
Yu-Liang Wu, Malgorzata Marek-Sadowska

33.5 Effects of FPGA Architecture on FPGA Routing
Stephen Trimberger

Session 34 EDA and the WWW

34.1 The Case for Design Using the World Wide Web
Mário J. Silva, Randy H. Katz

Panel: The Impact of the World Wide Web on Electronic Design and EDA
Panelists: Jeff Allison, Jeff Angwin, Bob Dahlberg, Steven Levitan, Rob Rodin, Alex Silbey

Session 35 Code Generation for Embedded Systems

35.1 Synthesis of Software Programs for Embedded Control Applications
Massimiliano Chiodo, Paolo Giusto, Attila Jurecska, Luciano Lavagno, Harry Hsieh, Kei Suzuki, Alberto L. Sangiovanni-Vincentelli, Ellen Sentovich

35.2 Conflict Modelling and Instruction Scheduling in Code Generation for In-House DSP Cores*
Adwin H. Timmer, Marino T.J. Strik, Jef L. van Meerbergen, Jochen A.G. Jess

35.3 Code Optimization Techniques for Embedded DSP Microprocessors
Stan Liao, Srinivas Devadas, Kurt Keutzer, Steve Tjiang, Albert Wang

35.4 Retargetable Self-Test Program Generation Using Constraint Logic Programming
Ulrich Bieker, Peter Marwedel

Session 36 Switching Activity and Power Analysis

36.1 Tutorial: Feedback, Correlation, and Delay Concerns in the Power Estimation of VLSI Circuits
Farid N. Najm

36.2 Accurate Estimation of Combinational Circuit Activity
Huzefa Mehta, Manjit Borah, Robert Michael Owens, Mary Jane Irwin

36.3 Extreme Delay Sensitivity and the Worst-Case Switching Activity in VLSI Circuits
Farid N. Najm, Michael Y. Zhang

36.4 Efficient Power Estimation for Highly Correlated Input Streams
Radu Marculescu, Diana Marculescu, Massoud Pedram

36.5 Power Estimation in Sequential Circuits*
Farid N. Najm, Shashank Goel, Ibrahim N. Hajj

Session 37 Combinational Logic Synthesis

37.1 New Ideas for Solving Covering Problems
Olivier Coudert, Jean Christophe Madre

37.2 Logic Synthesis for Engineering Change
Chih-chang Lin, Kuang-Chien Chen, Shih-Chieh Chang, Malgorzata Marek-Sadowska, Kwang-Ting Cheng

37.3 A Partitioning-Based Logic Optimization Method for Large Scale Circuits with Boolean Matrix
Yuichi Nakamura, Takeshi Yoshimura

37.4 Multi-Level Logic Minimization Based on Multi-Signal Implications
Masayuki Yuguchi, Yuichi Nakamura, Kazutoshi Wakabayashi, Tomoyuki Fujita

37.5 An Efficient Algorithm for Local Don'’t Care Sets Calculation
Shih-Chieh Chang, Malgorzata Marek-Sadowska, Kwang-Ting Cheng

37.6 Logic Clause Analysis for Delay Optimization
Bernhard Rohfleisch, Bernd Wurth, Kurt Antreich

Session 38 Panel: Deep Submicron Design Challenges

Session 39 Complexity Measures for VHDL

39.1 Tutorial: Productivity Issues in High-Level Design: Are Tools Solving the Real Problems?
Reinaldo A. Bergamaschi

39.2 Information Models of VHDL
Cristian A. Giumale, Hilary J. Kahn

39.3 Measures of Syntactic Complexity for Modeling Behavioral VHDL
Neal S. Stollon, John D. Provence

Session 40 Timing Analysis and Optimization

40.1 Simultaneous Gate and Interconnect Sizing for Circuit-Level Delay Optimization
Noel Menezes, Satyamurthy Pullela, Lawrence T. Pileggi

40.2 An Algorithm for Incremental Timing Analysis
Jin-fuw Lee, Donald T. Tang

40.3 An Assigned Probability Technique to Derive Realistic Worst-Case Timing Models of Digital Standard Cells
Alessandro Dal Fabbro, Bruno Franzini, Luigi Croce, Carlo Guardiani

40.4 Automatic Clock Abstraction from Sequential Circuits
Samir Jain, Randal E. Bryant, Alok Jain

Session 41 Asynchronous Synthesis

41.1 Hierarchical Optimization of Asynchronous Circuits
Bill Lin, Gjalt De Jong, Tilman Kolks

41.2 Externally Hazard-Free Implementations of Asynchronous Circuits
Milton Sawasaki, Chantal Ykman-Couvreur, Bill Lin

41.3 A Design and Validation System for Asynchronous Circuits
Peter Vanbekbergen, Albert Wang, Kurt Keutzer