ICCAD 2001 Table of Contents

Sessions: [1A] [1B] [1C] [1D] [2A] [2B] [3A] [3B] [3C] [3D] [Panel] [4A] [4B] [4C] [4D] [5A] [5B] [6A] [6B] [6C] [6D] [7A] [7B] [7C] [7D] [8A] [8B] [8C] [8D] [9A] [9B] [9C] [9D] [10A] [10B] [10C] [11A]

Foreword
Conference Committee
Technical Program Committee
Reviewers
Keynote
Tutorial 1: Electrical-Integrity Design and Verification for Digital and Mixed-Signal Systems-On-A-Chip
Tutorial 2: Boolean Satisfiability Solving and Its Application in Equivalence and Model Checking
Tutorial 3: Low-Power/Low-Energy Embedded Software: What, Why and How?
Tutorial 4: Optimization Strategies for Physical Synthesis and Timing Closure

Session 1A: Dynamic Verification

Moderators: Jay Lawrence, Cadence Design Systems, Inc., Chelmsford, MA
Kunle Olokotun, Stanford University, Stanford, CA
1A.1 Static Scheduling of Multi-Domain Memories For Functional Verification [p. 2]
Murali Kudlugi, Charles Selvidge, Russell Tessier

1A.2 A Simulation-Based Method for the Verification of Shared Memory in Multiprocessor Systems [p. 10]
Scott A. Taylor, Carl Ramey, Craig Barner, David Asher

1A.3 Predicting the Performance of Synchronous Discrete Event Simulation Systems [p. 18]
Jinsheng Xu, Moon Jung Chung

Session 1B: System-Level Exploration and Design

Moderators: Yanbing Li, Synopsys, Inc., Mountain View, CA
Xiaobo (Sharon) Hu, University of Notre Dame, Notre Dame, IN
1B.1System-Level Exploration for Pareto-Optimal Configurations in Parameterized Systems-on-a-Chip [p. 25]
Tony D. Givargis, Frank Vahid, Joerg Henkel

1B.2 System Level Design with Spade: an M-JPEG Case Study [p. 31]
Paul Lieverse, Todor Stefanov, Pieter van der Wolf, Ed F. Deprettere

1B.3 NetBench: A Benchmarking Suite for Network Processors [p. 39]
Gokhan Memik, William H. Mangione-Smith, Wendong Hu

Session 1C: Interconnect Planning

Moderators: Robi Dutta, Synopsys, Inc., Mountain View, CA
Chung-Kuan Cheng, University of California at San Diego, La Jolla, CA
1C.1 Analysis of Substrate Thermal Gradient Effects on Optimal Buffer Insertion [p. 44]
Amir H. Ajami, Kaustav Banerjee, Massoud Pedram

1C.2 A New Algorithm for Routing Tree Construction with Buffer Insertion and Wire Sizing under Obstacle Constraints [p. 49]
Xiaoping Tang, Ruiqi Tian, Hua Xiang, D.F. Wong

1C.3 Bus Encoding to Prevent Crosstalk Delay [p. 57]
Bret M. Victor, Kurt Keutzer

Session 1D: Analog Macromodeling

Moderators: Rob A. Rutenbar, Carnegie Mellon University, Pittsburgh, PA
Henry Chang, Cadence Design Systems, Inc., San Jose, CA
1D.1 Behavioral Modeling of Analog Circuits by Wavelet Collocation Method [p. 65]
Xin Li, Xuan Zeng, Dian Zhou, Xieting Ling

1D.2 Simulation-Based Automatic Generation of Signomial and Posynomial Performance Models for Analog Integrated Circuit Sizing [p. 70]
Walter Daems, Georges Gielen, Willy Sansen

1D.3 Power Grid Transient Simulation in Linear Time Based on Transmission-Line-Modeling Alternating-Direction-Implicit Method [p. 75]
Yu-Min Lee, Charlie Chung-Ping Chen

Session 2A: Embedded Tutorial: Platform-Based Designs

Moderator: Ellen M. Sentovich, Cadence Berkeley Labs., Berkeley, CA

Session 2B: Embedded Tutorial: VLSI Microsystems: The Power of Many

Moderator: Matton Kamon, Conventor, Inc., Cambridge, MA

Session 3A: Sequential Synthesis

Moderators: Hamid Savoj, Magma Design Automation, Inc., Cupertino, CA
Diana Marculescu, Carnegie Mellon University, Pittsburgh, PA
3A.1 Sequential SPFDs [p. 84]
Subarnarekha Sinha, Andreas Kuehlmann, Robert K. Brayton

3A.2 On the Optimization Power of Redundancy Addition and Removal Techniques for Sequential Circuits [p. 91]
Enrique San Mill‡n, Luis Entrena, JosŽ Alberto Espejo

3A.3 Placement Driven Retiming with a Coupled Edge Timing Model [p. 95]
Ingmar Neumann, Wolfgang Kunz

3A.4 Solution of Parallel Language Equations for Logic Synthesis [p. 103]
Nina Yevtushenko, Tiziano Villa, Robert K. Brayton, Alex Petrenko, Alberto L. Sangiovanni-Vincentell

Session 3B: Compiler Techniques in System Level Design

Moderators: Radu Marculescu, Carnegie Mellon University, Pittsburgh, PA
Grant Martin, Cadence Design Systems, Inc., San Jose, CA
3B.1 CALiBeR: A Software Pipelining Algorithm for Clustered Embedded VLIW Processors [p. 112]
Cagdas Akturan, Margarida F. Jacome

3B.2 Software-Assisted Cache Replacement Mechanisms for Embedded Systems [p. 119]
Prabhat Jain, Srinivas Devadas, Daniel Engels, Larry Rudolph

3B.3 Instruction Generation for Hybrid Reconfigurable Systems [p. 127]
Ryan Kastner, Seda Ogrenci-Memik, Elaheh Bozorgzadeh, Majid Sarrafzadeh

Session 3C: Routing Architecture and Techniques for FPGAs

Moderators: Majid Sarrafzadeh, University of California, Los Angeles, CA
Rajeev Jayaraman, Xilinx, Inc., San Jose, CA
3C.1 Interconnect Resource-Aware Placement for Hierarchical FPGAs [p. 132]
Amit Singh, Ganapathy Parthasarathy, Malgorzata Marek-Sadowsk

3C.2 A Router for Symmetrical FPGAs Based on Exact Routing Density Evaluation [p. 137]
Nak-Woong Eum, Taewhan Kim, Chong Min Kyung

3C.3 A Search-Based Bump-and-Refit Approach to Incremental Routing for ECO Applications in FPGAs [p. 144]
Vinay Verma, Shantanu S. Dutt

Session 3D: Interconnect Performance and Reliability Optimization

Moderators: David D. Ling, IBM Corp. TJ Watson Research Center, Yorktown Heights, NY
Ken Kundert, Cadence Design Systems, Inc., San Jose, CA

3D.1 Area Minimization of Power Distribution Network Using Efficient Nonlinear Programming Techniques [p. 153]
Xiaohai Wu, Xianlong Hong, Yici Cai, C.K. Cheng, Jun Gu, Wayne Dai

3D.2 Coupled Analysis of Electromigration Reliability and Performance in ULSI Signal Nets [p. 158]
Kaustav Banerjee, Amit Mehrotra

3D.3 Compact Modeling and SPICE-Based Simulation for Electrothermal Analysis of Multilevel ULSI Interconnects [p. 165]
TingYen Chiang, Kaustav Banerjee, Krishna C. Saraswat

Panel:

Moderator: Andreas Kuehlmann, Cadence Berkeley Laboratories, Berkeley, CA
Panelists: Robert W. Dutton, Paul Franzon, Seth C. Goldstein, Philip Luekes, Eric Parker, Thomas N. Theis
Will Nanotechnology Change the Way We Design and Verify Systems? [p. 174]

Session 4A: Circuit Structure in Fromal Verification

Moderators: Masahiro Fujita, University of Tokyo, Tokyo, Japan
Vigyan Singal, Tempus Fujit, Berkeley, CA
4A.1 Min-Area Retiming on Dynamic Circuit Structures [p. 176]
Jason Baumgartner, Andreas Kuehlmann

4A.2 Verification of Integer Multipliers on the Arithmetic Bit Level [p. 183]
Dominik A. Stoffel, Wolfgang Kunz

4A.3 Induction-Based Gate-Level Verification of Multipliers [p. 190]
Ying-Tsai Chang, Kwang-Ting(Tim) Cheng

Session 4B: System Level Power and Performance Modeling`

Moderators: Wayne Wolf, Mediaworks Technology, Schaumberg, IL
Preeti Panda, Synopsys, Inc., Mountain View, CA
4B.1 An Assembly-Level Execution-Time Model for Pipelined Architectures [p. 195]
Giovanni Beltrame, Carlo Brandolese, William Fornaciari, Fabio Salice, Donatella Sciuto, Vito Trianni

4B.2 Improving Memory Energy Using Access Pattern Classification [p. 201]
Mahut T. Kandemir, Ugur Sezer, Victor Delaluz

4B.3 System-Level Power/Performance Analysis of Portable Multimedia Systems Communicating over Wireless Channels [p. 207]
Radu Marculescu, Amit Nandi, Luciano Lavagno, Alberto Sangiovanni-Vincentelli

Session 4C: Topics in Physical Synthesis

Moderators: Andrew B. Kahng, University of California at San Diego, La Jolla, CA
Malgorzata Marek-Sadowska, University of California, Santa Barbara, CA
4C.1 Congestion Aware Layout Driven Logic Synthesis [p. 216]
Thomas Kutzschebauch, Leon Stok

4C.2 Addressing the Timing Closure Problem by Integrating Logic Optimization and Placement [p. 224]
Wilsin Gosti, Sunil Khatri, Alberto Sangiovanni-Vincentelli

4C.3 An Algorithm for Simultaneous Pin Assignment and Routing [p. 232]
Hua Xiang, Xiaoping Tang, D.F. Wong

Session 4D: Model Order Reduction

Moderators: Eli Chiprout, Intel Corp., Chandler, AZ
Andreas C. Cangellaris, University of Illinois, Urbana, IL
4D.1 Techniques for Including Dielectrics when Extracting Passive Low-Order Models of High Speed Interconnect [p. 240]
Luca Daniel, Alberto Sangiovanni-Vincentelli, Jacob K. White

4D.2 A Convex Programming Approach to Positive Real Rational Approximation [p. 245]
Carlos P. Coelho, Joel R. Phillips, Luis M. Silveira

4D.3 A Trajectory Piecewise-Linear Approach to Model Order Reduction and Fast Simulation of Nonlinear Circuits and Micromachined Devices [p. 252]
Michal Rewienski, Jacob K. White

Session 5A: Embedded Tutorial: Embedded Software and Systems

Moderators: Rolf Ernst, Technical University of Braunschweig, Braunschweig, Germany
Francky Catthoor, IMEC, Leuven, Belgium
5A.1 Low Power System Scheduling and Synthesis [p. 259]
Niraj K. Jha

5A.3 Integral Design Representations for Embedded Systems [p. 264]
Lothar Thiele

5A.4 Optimisation Problems for Dynamic Concurrent Task-Based Systems [p. 265]
D. Verkest, P. Yang, C. Wong, P. Marchal

Session 5B: Embedded Tutorial: CAD Solutions and Outstanding Challenges for Mixed-Signal and RF IC Design [p. 270)

Moderator: Georges Gielen, Katholieke University, Leuven, Belgium
Domine Leenaerts, Rob A. Rutenbar, Georges Gielen

Session 6A: BDDs and SAT

Moderators: Alan J. Hu, University of British Columbia, Vancouver, BC, Canada
Rajeev Ranjan, Real Intent, Santa Clara, CA
6A.1 Efficient Conflict Driven Learning in Boolean Satisfiability Solver [p. 279]
Lintao Zhang, Conor Madigan, Matthew Moskewicz, Sharad Malik

6A.2 Partition-Based Decision Heuristics for Image Computation Using SAT and BDDs [p. 286]
Aarti Gupta, Zijiang Yang, Pranav N. Ashar, Lintao Zhang, Sharad Malik

6A.3 Non-linear Quantification Scheduling in Image Computation [p. 293]
Pankaj Chauhan, Edmund M. Clarke, Somesh Jha, Jim Kukula, Tom Shiple, Helmut Veith, Dong Wang

Session 6B: Convergence of Abstractions in High-Level Synthesis

Moderators: Sandeep Shukla, University of California, Irvine, CA
Francky Catthoor, IMEC, Leuven, Belgium
6B.1 Symbolic Algebra and Timing Driven Data-flow Synthesis [p. 300]
Armita Peymandoust, Giovanni De Micheli

6B.2 Application-Driven Processor Design Exploration for Power-Performance Trade-off Analysis [p. 306]
Diana Marculescu, Anoop Iyer

6B.3 A System for Synthesizing Optimized FPGA Hardware from MATLAB [p. 314]
Malay Haldar, Anshuman Nayak, Alok Choudhary, Prith Banerjee

6B.4 Behavior-to-Placed RTL Synthesis with Performance-Driven Placement [p. 320]
Daehong Kim, Jinyong Jung, Sunghyun Lee, Jinhwan Jeon, Kiyoung Choi

Session 6C: Signal Integrity and Clock Design

Moderators: Cheng-Kok Koh, Purdue University, West Lafayette, IN
Tong Gao, Monterey Design Systems, Inc., Sunnyvale, CA
6C.1 Formulae and Applications of Interconnect Estimation Considering Shield Insertion and Net Ordering [p. 327]
James D.Z Ma, Lei He

6C.2 Hybrid Structured Clock Network Construction [p. 333]
Haihua Su, Sachin Sapatnekar

6C.3 CASh: A Novel "Clock as Shield" Design Methodology for Noise Immune Precharge-Evaluate Logic [p. 337]
Yonghee Im, Kaushik Roy

Session 6D: Analog Synthesis

Moderators: Koen Lampaert, Mindspeed Technology, Newport Beach, CA Henry Chang, Cadence Design Systems, Inc., San Jose, CA
6D.1 The Sizing Rules Method for Analog Integrated Circuit Design [p. 343]
Helmut E. Graeb, Stephan Zizala, Josef Eckmueller, Kurt Antreich

6D.2 ASF: A Practical Simulation-Based Methodology for the Synthesis of Custom Analog Circuits [p. 350]
Michael J. Krasnicki, Rodney Phelps, James R. Hellums, Mark McClung, Rob A. Rutenbar, L. Richard Carley

6D.3 A Layout-Aware Synthesis Methodology for RF Circuits [p. 358]
Peter J. Vancorenland, Geert Van der Plas, Michiel Steyaert, Georges Gielen, Willy Sansen

Session 7A: Manufacturing Test: Stuck-at to Crosstalk

Moderators: Sujit Dey, University of California at San Diego, La Jolla, CA
Yervant Zorian, LogicVision, Inc., San Jose, CA
7A.1 On Identifying Don't Care Inputs of Test Patterns for Combinational Circuits [p. 364]
Seiji Kajihara, Kohei Miyase

7A.2 REDI: An Efficient Fault Oriented Procedure to Identify Redundant Faults in Combinational Logic Circuits [p. 370]
Chen Wang, Irith Pomeranz, Sudhakar M. Reddy

7A.3 Crosstalk Fault Detection by Dynamic Idd [p. 375]
Xiaoyun Sun, Seonki Kim, Bapiraju Vinnakota

Session 7B: Architecture Oriented Scheduling

Moderators: Miodrag Potkonjak, University of California, Los Angeles, CA
Kazutoshi Wakabayashi, NEC Corp., Kawasaki, Japan
7B.1 Color Permutation: An Iterative Algorithm for Memory Packing [p. 380]
Jianwen Zhu, Edward S. Rogers, Sr.

7B.2 Constraint Satisfaction for Relative Location Assignment and Scheduling [p. 384]
Carlos Alba-Pinto, Bart Mesman, Jochen Jess

7B.3 A Super-Scheduler for Embedded Reconfigurable Systems [p. 391]
S. Ogrenci Memik, E. Bozorgzadeh, R. Kastner, M. Sarrafzade

Session 7C: New Techniques in Routing

Moderators: Jo Dale Carothers, University of Arizona, Tucson, AZ
Amir H. Farrahi, IBM Corp. TJ Watson Research Center, Yorktown Heights, NY
7C.1 Multilevel Approach to Full-Chip Gridless Routing [p. 396]
Jason Cong, Jie Fang, Yan Zhang

7C.2 A Force-Directed Maze Router [p. 404]
Fan Mo, Abdallah Tabbara, Robert K. Brayton

7C.3 Minimum-Buffered Routing of Non-Critical Nets for Slew Rate and Reliability Control [p. 408]
Charles Alpert, Andrew B. Kahng, Bao Liu, Ion Mandoiu, Alexander Zelikovsky

Session 7D: Issues in Substrate Coupling

Moderators: Mattan Kamon, Coventor, Inc., Cambridge, MA
Kenneth L. Shepard, Columbia University, New York, NY
7D.1 Highly Accurate Fast Methods for Extraction and Sparsification of Substrate Coupling Based on Low-Rank Approximation [p. 417]
Joe Kanapka, Jacob White

7D.2 Fast 3-D Inductance Extraction in Lossy Multi-Layer Substrate [p. 424]
Minqing Liu, Tiejun Yu, Wayne W.-M. Dai

7D.3 Simulation Approaches for Strongly Coupled Interconnect Systems [p. 430]
Joel R. Phillips, L. Miguel Silveira

Session 8A: Combinational Optimization

Moderators: Olivier Coudert, Monterey Design Systems, Inc., Sunnyvale, CA
Tiziano Villa, Parades Labs., Rome, Italy
8A.1 BOOM ö A Heuristic Boolean Minimizer [p. 439]
Jan Hlavicka, Petr Fiser

8A.2 Faster SAT and Smaller BDDs via Common Function Structure [p. 443]
Fadi A. Aloul, Igor L. Markov, Karem A. Sakallah

8A.3 Recursive Bipartitioning of BDDs for Performance Driven Synthesis of Pass Transistor Logic Circuits [p. 449]
Rupesh S. Shelar, Sachin S. Sapatnekar

8A.4 A Probabilistic Constructive Approach to Optimization Problems [p. 453]
Jennifer L. Wong, Farinzaz Koushanfar, Seapahn Meguerdichian, Miodrag Potkonjak

Session 8B: Real Time Scheduling and Performance Analysis

Moderators: Pai Chou, University of California, Irvine, CA
Luciano Lavagno, Cadence Berkeley Labs., Berkeley, CA
8B.1 Energy Efficient Real-Time Scheduling [p. 458]
Amit Sinha, Anantha P. Chandrakasan

8B.2 Efficient Performance Estimation for General Real-Time Task Systems [p. 464]
Hongchao (Stephanie) Liu, Xiaobo (Sharon) Hu

8B.3 Stars in VCC: Complementing Simulation with Worst-Case Analysis [p. 471]
Felice Balarin

Session 8C: Power Analysis

Moderators: Anirudh Devgan, IBM Corp., Austin, TX
Carlo Guardini, PDF Solutions, San Jose, CA
8C.1 Multigrid-Like Technique for Power Grid Analysis [p. 480]
Joseph N. Kozhaya, Sani R. Nassif, Farid N. Najm

8C.2 An Analytical High-Level Battery Model for Use in Energy Management of Portable Electronic Systems [p. 488]
Daler N. Rakhmatov, Sarma B.K. Vrudhula

8C.3 Power-Delay Modeling of Dynamic CMOS Gates for Circuit Optimization [p. 494]
J.L. Rossello, Jaume Segura

Session 8D: Timing and Noise Analysis

Moderators: Tim Burks, Magma Design Automation, Inc., Cupertino, CA
Florentin Dartu, Intel Corp., Hillsboro, OR
8D.1 A Symbolic Simulation-Based Methodology for Generating Black-Box Timing Models of Custom Macrocells [p. 501]
Clayton McDonald, Randal E. Bryant

8D.2 On the Signal Bounding Problem in Timing Analysis [p. 507]
Jin-Fuw Lee, D.L. Ostapko, Jeffery Soreff, C.K. Wong

8D.3 False-Noise Analysis using Logic Implications [p. 515]
Alexey Glebov, Sergey Gavrilov, David Blaauw, Supamas Sirichotiyakul, Chanhee Oh, Vladimir Zolotov

Session 9A: System Level Test and Reliability

Moderators: Bapi Vinnakota, University of Minnesota, Minneapolis, MN
Seiji Kajihara, Kyushu Institute of Technology, Iizuka, Japan
9A.1 The Design and Optimization of SOC Test Solutions [p. 523]
Erik Larsson, Zebo Peng, Gunnar Carlsson

9A.2 Accurate CMOS Bridge Fault Modeling with Neural Network-Based VHDL Saboteurs [p. 531]
Don Shaw, Dhamin Al-Khalili, C™me Rozon

9A.3 Algorithm Level Re-Computing - A Register Transfer Level Concurrent Error Detection Technique [p. 537]
Kaijie Wu, Ramesh Karri

Session 9B: Power Issues in High Level Synthesis

Moderators: Sridevan Parameswaran, The University of New South Wales, Kensington, Australia
Nikil Dutt, University of California, Irvine, CA
9B.1 Transient Power Management Through High Level Synthesis [p. 545]
Vijay Raghunathan, Srivaths Ravi, Anand Raghunatha, Ganesh Lakshminarayana

9B.2 An Integrated Data Path Optimization for Low Power Based on Network Flow Method [p. 553]
Chun-Gi Lyuh, Taewhan Kim, C.L. Liu

9B.3 What is the Limit of Energy Saving by Dynamic Voltage Scaling? [p. 560]
Gang Qu

Session 9C: Advances in Placement

Moderators: Jason Cong, University of California, Los Angeles, CA
Patrick Groeneveld, Magma Design Automation, Inc., Cupertino, CA
9C.1 Local Search for Final Placement in VLSI Design [p. 565]
Oluf Faroe, David Pisinger, Martin Zachariase

9C.2 Congestion Reduction During Placement Based on Integer Programming [p. 573]
Xiaojian Yang, Ryan Kastner, Majid Sarrafzadeh

9C.3 Direct Transistor-Level Layout for Digital Blocks [p. 577]
Prakash Gopalakrishnan, Rob A. Rutenbar

Session 9D: Interconnect Analysis and Extraction

Moderators: Dennis M. Sylvester, University of Michigan, Ann Arbor, MI
Mustafa Celik, Monterey Design Systems, Inc., Sunnyvale, CA
9D.1 Model Reduction of Variable-Geometry Interconnects using Variational Spectrally-Weighted Balanced Truncation [p. 586]
Payam Heydari, Massoud Pedram

9D.2 Improving the Robustness of a Surface Integral Formulation for Wideband Impendance Extraction of 3D Structures [p. 592]
Zhenhai Zhu, Jingfang Huang, Ben Song, Jacob White

9D.3 Practical Considerations in RLCK Crosstalk Analysis for Digital Integrated Circuits [p. 598]
Steven C. Chan, K.L. Shepard

Session 10A: Don't Care Optimization and Boolean Matching

Moderators: Yuji Kukimoto, Silicon Perspective Corp., Santa Clara, CA
Prabhakar Kudva, IBM Corp. TJ Watson Research Center, Yorktown Heights, NY
10A.1 Single-Pass Redundancy Addition and Removal[p. 606]
Chih-Wei (Jim) Chang, Malgorzata Marek-Sadowska

10A.2 Efficient Canonical Form for Boolean Matching of Complex Functions in Large Libraries [p. 610]
Jovanka Ciric, Carl Sechen

10A.3 Compatible Observability Donât Cares Revisited [p. 618]
R.K. Brayton

Session 10B: Power Saving Techniques for Embedded Processors

Moderators: Preeti Panda, Synopsys, Inc., Mountain View, CA
Tony Givargis, University of California, Irvine, CA
10B.1 A Methodology for the Design of Application Specific Instruction Set Processors (ASIP) using the Machine Description Language LISA [p. 625]
Andreas Hoffmann, Oliver Schliebusch, Achim Nohl, Gunner Braun, Oliver Wahlen, Heinrich Meyr

10B.2 Area and Power Reduction of Embedded DSP Systems using Instruction Compression and Re-Configurable Encoding [p. 631]
Subash G. Chandar, Mahesh Mehendale, R. Govindarajan

10B.3 I-CoPES: Fast Instruction Code Placement for Embedded Systems to Improve Performance and Energy Efficiency [p. 635]
Sri Parameswaran, Jšrg Henkel

Session 10C: Embedded Tutorial: IC Power Distribution Challenges

Moderator: Farid Najm, University of Toronto, Toronto, ON, Canada
10C.1 IC Power Distribution Challenges [p. 643]
Sudhakar Bobba, Tyler Thorp, Kathirgamar Aingaran, Dean Liu

10C.2 Challenges in Power-Ground Integrity [p. 651]
Shen Lin, Norman Chang

Session 11A: Panel: Automatic Hierarchical Design: Fantasy or Reality?

Moderator: Rob A. Rutenbar, Carnegie Mellon University, Pittsburgh, PA
Panelists: Olivier Coudert, Patrick Groeneveld, Juergen Koehl, Scott Peterson, Vivek Raghavan, Naresh Soni
11A.1 Automatic Hierarchical Design: Fantasy or Reality? [p. 656]