TABLE OF CONTENTS ASP-DAC '95

Sessions
[1A] [1B] [1C] [2A] [2B] [2C] [3A] [3B] [3C] [4A] [4B] [4C] [5A] [5B] [5C] [6A] [6B] [6C] [7A] [7B] [7C] [8A] [8B] [8C] [9A] [9B] [9C]

Advisory Board
Organizing Committee
Steering Committee
General Chair's Message
ASP-DAC '95 Program Committee
ASP-DAC '95 Program Committee Chair's Message
ASP-DAC '95 Best Paper Candidates
Keynote Address I - Atsushi Asada
Keynote Address II - Jim Meadlock
Keynote Address III - John Darringer

Session [A-1A] Design Methodologies for Low Power

Chair: Massoud Pedram (Univ. of South California, USA)
Co-Chair: Hidetoshi Onodera (Kyoto Univ., Japan)

A-1A.1 Transistor Reordering Rules for Power Reduction in CMOS Gates
Wen-Zen Shen, Jiing-Yuan Lin (National Chiao Tung Univ., Taiwan), Fong-Wen Wang (Telecommunication Laboratories, MTC, Taiwan)

A-1A.2 Power Reduction by Gate Sizing with Path-Oriented Slack Calculation
How-Rern Lin and TingTing Hwang(Tsing Hua Univ., Taiwan)

A-1A.3 Current and Charge Estimation in CMOS Circuits
Sanjay Dhar, Dave J. Gurney (Mentor Graphics Corp., USA)

Session [A-1B] Design Methodology for Processor and Telecommunication Systems

Chair: Winfried Hahn (Univ. of Passau, Germany)
Co-Chair: Yoshio Takamine (Hitachi Ltd., Japan)

A-1B.1 Auriga2: A 4.7 Million-Transistor CISC Microprocessor
J. P. Tual, M. Thill, C. Bernard, H. N. Nguyen, F. Mottini, M. Moreau, P. Vallet (BULL S. A., France)

A-1B.2 Automatic Design for Bit-Serial MSPA Architecture
Hiroaki Kunieda, Yusong Liao, Dongju Li, Kazuhito Ito, (Tokyo Inst. of Technology, Japan, Saitama University, Saitama)

A-1B.3 Stoht --- An SDL-to-Hardware Translator
Ivanil S. Bonatti, Renato J. O. Figueiredo (Univ. of Campinas, Brazil)

A-1B.4 Enhancing a VHDL Based Design Methodology with Application Specific Data Abstraction
Lars Lindqvist (NKT Electronik A/S and Danmarks Tekniske Univ., Denmark)

Session [A-1C] PANEL: Design Automation 2000---Challenges for Gigabit-Era

Moderator: Richard K. Wallace, Editor-in-Chief, EE Times
Panelists: Joseph B. Costello (CEO, Cadence), Jeffrey H. Edson (VP, Intergraph), Aart deGeus (CEO, Synopsys), Alan J. Hanover (CEO, Viewlogic), Jinya Katsube (VP, Zuken), Walden C. Rhines (CEO, Mentor)

Session [A-2A] High Level Synthesis (1)

Chair: Daniel D. Gajski (Univ. of California at Irvine, USA)
Co-Chair: Tadatoshi Ishii (Toshiba Corp., Japan)

A-2A.1 A Scheduling Algorithm for Synthesis of Bus-Partitioned Architectures
Vasily G. Moshnyaga, Fumiaki Ohbayashi, Keikichi Tamaru (Kyoto Univ., Japan)

A-2A.2 Reclocking for High-Level Synthesis
Pradip Jha, Nikil Dutt (Univ. of California, Irvine, USA), Sri Parameswaran (Univ. of Queensland, Australia)

A-2A.3 Synthesis of False Loop Free Circuits
Shih Hsu Huang, Ta-Yung Liu, Yu-Chin Hsu (Univ. of California, Riverside, USA), Yen-Jen Oyang (National Taiwan Univ., Taiwan)

A-2A.4 High-Level Synthesis Scheduling and Allocation Using Genetic Algorithms
M. J. M. Heijligers, L. J. M. Cluitmans, J. A. G. Jess (Eindhoven Univ. of Technology, The Netherlands)

Session [A-2B] Design Abstractions and Environments

Chair: Graham R. Hellestrand (Univ. of New South Wales, Australia)
Co-Chair: Masatoshi Sekine (Toshiba Corp., Japan)

A-2B.1 A Framework for the Analysis and Design of Algorithms for a Class of VLSI-CAD Optimization Problems
C. -J. Shi, (Univ. of Iowa, USA), J. A. Brzozowski (Univ. of Waterloo, Canada)

A-2B.2 Generic Fuzzy Logic CAD Development Tool
Eric Q. Kang, Eugene Shragowitz (Univ. of Minnesota, USA)

A-2B.3 A Hardware/Software Codesign Method for Pipelined Instruction Set Processor Using Adaptive Database
Nguyen Ngoc Binh, Masaharu Imai, Akichika Shiomi, (Toyohashi Univ. of Technology, Japan), Nobuyuki Hikichi, (Software Research Associates, Inc., Japan)

A-2B.4 EMPAR: An Interactive Synthesis Environment for Hardware Emulations
Tsing-Gen Lee, Wen-Jong Fang, Allen C.-H. Wu (Tsing Hua Univ., Taiwan)

Session [A-2C] System-Level Design Automation Activities in Korea (1)

Chair: Chong-Min Kyung, KAIST, Korea

A-2C.1 A Scheduling Algorithm for Multiport Memory Minimization in Datapath Synthesis
Hae-Dong Lee, Sun-Young Hwang (Sogang Univ., Korea)

A-2C.2 An Integrated Hardware-Software Cosimulation Environment for Heterogeneous Systems Prototyping
Yongjoo Kim, Kyuseok Kim, Youngsoo Shin, Taekyoon Ahn, Wonyong Sung, Kiyoung Choi, Soonhoi Ha (Seoul National Univ., Korea)

A-2C.3 A CSIC Implementation with POCSAG Decoder and Microcontroller for Paging Applications
J.Y. Lim , G. Kim (PANTECH Co., Ltd., Korea), I.S. O (Univ. of Inchon, Korea), J.H. Cho, Y.J. Kim, H.Y. Kim (PANTECH Co., Ltd., Korea)

A-2C.4 Performance-Driven Circuit Partitioning for Prototyping by Using Multiple FPGA Chips
Chunghee Kim, Hyunchul Shin (Hanyang Univ., Korea), Younguk Yu (Seodu Logic Inc., Korea)

Session [A-3A] Partition and Floorplan

Chair: Chung-Kuan Cheng (Univ. of California, San Diego, USA)
Co-Chair: Kazuhiro Ueda (Shibaura Inst. of Technology, Japan)

A-3A.1 A New System Partitioning Method under Performance and Physical Constraints for Multi-Chip Modules
Yoshinori Katsura, Tetsushi Koide, Shin'ichi Wakabayashi (Hiroshima Univ., Japan), Noriyoshi Yoshida (Hiroshima City Univ., Japan)

A-3A.2 A Robust Min-Cut Improvement Algorithm Based on Dynamic Look-Ahead Weighting
Katsunori Tani (NEC, Japan)

A-3A.3 Timing Influenced General-Cell Genetic Floorplanner
Sadiq M. Sait, Habib Youssef, Shahid K. Tanvir, and Muhammad S. T. Benten (King Fahd Univ. of Petroleum and Minerals, Saudi Arabia)

Session [A-3B] Embedded System Design

Chair: Akihiko Yamada (Tokyo Metropolitan Univ., Japan)
Co-Chair: Jun Sato (Tsuruoka National College of Technology, Japan)

A-3B.1 Power Analysis of a 32-bit Embedded Microcontroller
Vivek Tiwari (Princeton Univ., USA), Mike Tien-Chien Lee (Fujitsu Labs. of America, USA)

A-3B.2 Assessing the Feasibility of Interface Designs before their Implementation
Marco A. Escalante, Nikitas J. Dimopoulos (Univ. of Victoria, Canada)

A-3B.3 A Hardware-Software Co-simulator for Embedded System Design and Debugging
A. Ghosh, M. Bershteyn, R. Casley, C. Chien, A. Jain, M. Lipsie, D. Tarrodaychik, O. Yamamoto (Mitsubishi Electric Research Laboratories, Inc., USA)

Session [A-3C] System-Level Design Automation Activities in Korea (2)

Chair: Chong-Min Kyung, KAIST, Korea

A-3C.1 Integrated Interconnect Circuit Modeling for VLSI Design
Won-Young Jung, Ghun-Up Cha, Young-Bae Kim, Jun-Ho Baek, Choon-Kyung Kim (LG Semiconductor Inc., Korea)

A-3C.2 Architectural Simulation for a Programmable DSP Chip Set
Jong Tae Lee, Jaemin Kim, and Jae Cheol Son (Samsung Electronics Co., Ltd., Korea)

A-3C.3 System-Level Verification of CDMA Modem ASIC
GyeongLyong Park, KyungHi Chang, Jaeseok Kim, and Kyungsoo Kim (ETRI, Korea)

A-3C.4 A Digital Audio Signal Processor for Cellular Phone Application
Jeongsik Yang, Chanhong Park, Beomsup Kim (KAIST, Korea)

Session [A-4A] Routing

Chair: Jason Cong (Univ. of California, Los Angeles, USA)
Co-Chair: Takashi Mitsuhashi (Toshiba Corp., Japan)

A-4A.1 Region Definition and Ordering Assignment with the Minimization of the Number of Switchboxes
Jin-Tai Yan (National Chiao Tung Univ., Taiwan)

A-4A.2 A Three-Layer Over-the-Cell Multi-Channel Routing Method for a New Cell Model
Masahiro Tsuchiya, Tetsushi Koide, Shin'ichi Wakabayashi (Hiroshima Univ., Japan), Noriyoshi Yoshida (Hiroshima City Univ., Japan)

A-4A.3 Pin Assignment and Routing on a Single-Layer Pin Grid Array
Man-Fai Yu, Wayne Wei-Ming Dai (Univ. of California, Santa Cruz, USA)

Session [A-4B] Design for Testability

Chair: Yervant Zorian (AT&T, USA)
Co-Chair: Kiyoshi Furuya (Chuo Univ., Japan)

A-4B.1 Design for Testability Using Register-Transfer Level Partial Scan Selection
Akira Motohara, Sadami Takeoka, Toshinori Hosokawa, Mitsuyasu Ohta, Yuji Takai, Michihiro Matsumoto, Michiaki Muraoka (Matsushita Electric Industrial Co., Ltd., Japan)

A-4B.2 A Built-In Self Test Scheme for VLSI
T. Raju Damarla (GEO Centers, Inc, USA), Wei Su, Gerald T. Michael (US Army Research Labs, USA), Moon J. Chung (Michigan State Univ., USA), Charles E. Stroud (Univ. of Kentucky, USA)

A-4B.3 BIST with Negligible Aliasing through Random Cover Circuits
T. Bogue, H. Jürgensen (Univ. of Western Ontario, Canada), M. Gössel (Univ. of Potsdam, Germany)

Session [A-4C] Logic Synthesis of Sequential Circuits

Chair: Sunil D. Sherlekar (Indian Inst. of Technology, India)
Co-Chair: Ryuichi Takahashi (Hiroshima City Univ., Japan)

A-4C.1 Implicit Prime Compatible Generation for Minimizing Incompletely Specified Finite State Machines
Hiroyuki Higuchi, Yusuke Matsunaga (Fujitsu Laboratories Ltd., Japan)

A-4C.2 Logic Optimization by an Improved Sequential Redundancy Addition and Removal Technique
Uwe Gläser (Schloss Birlinghoven, Germany), Kwang-Ting Cheng (Univ. of California, Santa Barbara, USA)

A-4C.3 On Hazard-Free Implementation of Speed-Independent Circuits
Alex Kondratyev, Michael Kishinevsky (Univ. of Aizu, Japan), Alex Yakovlev (Univ. of Newcastle upon Tyne, UK)

Session [A-5A] Technology-Driven Physical Synthesis

Chair: Hon-Wai Leong (National Univ. of Singapore)
Co-Chair: Shin'ichi Wakabayashi (Hiroshima Univ.)

A-5A.1 Extending Pitchmatching Algorithms to Layouts with Multiple Grid Constraints
Hiroshi Miyashita (NTT, Japan)

A-5A.2 A New Layout Synthesis for Leaf Cell Design
Masahiro Fukui, Noriko Shinomiya, Toshiro Akino (Matsushita Electric Industrial Co., Ltd., Japan)

A-5A.3 A Layout Approach to Monolithic Microwave IC
Akira Nagao, Chiyoshi Yoshioka, Takashi Kambe (Sharp Corp., Japan), Isao Shirakawa (Osaka Univ., Japan)

A-5A.4 Performance Driven Multiple-Source Bus Synthesis Using Buffer Insertion
Chia-Chun Tsai, De-Yu Kao, Chung-Kuan Cheng, Ting-Ting Lin (Univ. of California, San Diego, USA)

Session [A-5B] Logic Synthesis and Optimization (1)

Chair: Dr. Bernd Becker (Johann Wolfgang Goethe-Univ., Germany)
Co-Chair: Tetsuya Fujimoto (Sharp Corp., Japan)

A-5B.1 Communication Based FPGA Synthesis for Multi-Output Boolean Functions
Christoph Scholl (Univ. des Saarlandes, Germany), Paul Molitor (Martin-Luther Univ. Halle, Germany)

A-5B.2 Optimum PLA Folding through Boolean Satisfiability
Jose M. Quintana, Maria J. Avedillo, Maria P. Parra, Jose L. Huertas (Univ. of Sevilla, Spain)

A-5B.3 Technology Mapping for FPGAs with Complex Block Architectures by Fuzzy Logic Technique
Jun-Yong Lee, Eugene Shragowitz (Univ. of Minnesota, USA)

A-5B.4 Logic Rectification and Synthesis for Engineering Change
Chih-Chang Lin, David Ihsin Cheng, Malgorzata Marek-Sadowska (Univ. of California, Santa Barbara, USA), Kuang-Chien Chen (Fujitsu Labs. of America, Inc., USA)

Session [A-5C] Future Direction of Synthesizability and Interoperability of HDL's: Part-1

Chair: Masaharu Imai (Toyohashi Univ. of Technology, Japan)
Co-Chair: Eugenio Villar (Univ. of Cantabria, Spain)
Panelists: Raul Camposano (Synopsys, USA), Andrew Guyler (Mentor Graphics, USA), Victor Berman (Cadence Design Systems, USA), Jeffrey Fox (Viewlogic, USA), Sunil D. Sherlekar (IIT Bombay, India), Shigeaki Hakusui (Harmonix, USA)

Session [A-6A] CAD Algorithms for FPGAs

Chair: Gabriele Saucier (INPG, France)
Co-Chair: Akihiro Tsutsui (NTT, Japan)

A-6A.1 A New K-Way Partitioning Approach for Multiple Types of FPGAs
Bernhard M. Riess, Heiko A. Giselbrecht, Bernd Wurth (Technical Univ. of Munich, Germany)

A-6A.2 Maple-opt: A Simultaneous Technology Mapping, Placement, and Global Routing Algorithm for FPGAs with Performance Optimization
Nozomu Togawa, Masao Sato, Tatsuo Ohtsuki (Waseda Univ., Japan)

A-6A.3 Routing on Regular Segmented 2-D FPGAs
Yu-Liang Wu (Cadence Design Systems, Inc., USA), Malgorzata Marek-Sadowska (Univ. of California, Santa Barbara, USA)

Session [A-6B] Logic Synthesis and Optimization (2)

Chair: Tsutomu Sasao (Kyshu Inst. Technology, Japan)
Co-Chair: Shin-ichi Minato (NTT, Japan)

A-6B.1 Flexible Optimization of Fixed Polarity Reed-Muller Expansions for Multiple Output Completely and Incompletely Specified Boolean Functions
Chip-Hong Chang, Bogdan J. Falkowski (Nanyang Technological Univ., Singapore)

A-6B.2 GRMIN: A Heuristic Simplification Algorithm for Generalized Reed-Muller Expressions
Debatosh Debnath, Tsutomu Sasao (Kyushu Inst. of Technology, Japan)

A-6B.3S Learning Heuristics by Genetic Algorithms
Rolf Drechsler, Bernd Becker (Johann Wolfgang Goethe-Univ., Germany)

A-6B.4S Optimization Methods for Lookup-Table-Based FPGAs Using Transduction Method
Shigeru Yamashita, Yahiko Kambayashi (Kyoto Univ., Japan), Saburo Muroga (Univ. of Illinois, USA)

Session [A-6C] Future Direction of Synthesizability and Interoperability of HDL's: Part-2

Chair: Eugenio Villar (Univ. of Cantabria, Spain)
Co-Chair: Masaharu Imai (Toyohashi Univ. of Technology, Japan)
Panelists: Raul Camposano (Synopsys, USA), Andrew Guyler (Mentor Graphics, USA), Victor Berman (Cadence Design Systems, USA), Jeffrey Fox (Viewlogic, USA), Sunil D. Sherlekar (IIT Bombay, India), Shigeaki Hakusui (Harmonix, USA)

Session [A-7A] Modeling and Simulation

Chair: David Skellern (Macquarie Univ., Australia)
Co-Chair: Tetsuro Kage (Fujitsu Laboratories, Japan)

A-7A.1 A New and Accurate Interconnection Delay Time Evaluation in a General Tree-Type Network
D. Deschacht, C. Dabrin (Univ. Montpellier II, France)

A-7A.2 An Efficient Logic/Circuit Mixed-Mode Simulator for Analysis of Power Supply Voltage Fluctuation
Mikako Miyama, Goichi Yokomizo, Masato Iwabuchi, Masami Kinoshita (Hitachi, Ltd., Japan)

A-7A.3 A Model-Adaptable MOSFET Parameter Extraction System
Masaki Kondo, Hidetoshi Onodera, Keikichi Tamaru (Kyoto Univ., Japan)

Session [A-7B] Extension of Binary Decision Diagrams

Chair: Tomoyuki Fujita (NEC, Japan)
Co-Chair: Yusuke Matsunaga (Fujitsu Laboratories, Japan)

A-7B.1 Improved Computational Methods and Lazy Evaluation of the Ordered Ternary Decision Diagram
Per Lindgren (Luleä Inst. of Technology, Sweden)

A-7B.2 Some Remarks about Spectral Transform Interpretation of MTBDDs and EVBDDs
Radomir S. Stankovic (Yugoslavia)

A-7B.3 Manipulation of Regular Expressions Under Length Constraints Using Zero-Suppressed-BDDs
Shinya Ishihara, Shin-ichi Minato (NTT, Japan)

Session [A-7C] PANEL: How Sub-Micron Delay and Timing Issues Will Be Solved?

Chair: Hitoshi Yoshizawa(NEC, Japan)
Panelists: Ahsan Bootehsaz, Dennis B. Brophy, Donald R. Cottrell, Antun Domic, Vassilios Gerousis, Tamotsu Hiwatashi

Session [A-8A] Placement

Chair: Wayne W.-M. Dai (Univ. of California at Santa Cruz, USA)
Co-Chair: Masato Edahiro (NEC, Japan)

A-8A.1 Exploiting Signal Flow and Logic Dependency in Standard Cell Placement
Jason Cong, Dongmin Xu (Univ. of California, Los Angeles, USA)

A-8A.2 A New Performance Driven Placement Method with the Elmore Delay Model for Row Based VLSIs
Tetsushi Koide, Mitsuhiro Ono, Shin'ichi Wakabayashi, Yutaka Nishimaru (Hiroshima Univ., Japan), Noriyoshi Yoshida (Hiroshima City Univ., Japan)

A-8A.3 A Neural Network Approach to the Placement Problem
Morteza Saheb Zamani, Graham R. Hellestrand (Univ. of New South Wales, Australia)

A-8A.4 Fanout-Tree Restructuring Algorithm for Post-Placement Timing Optimization
T. Aoki, M. Murakata, T. Mitsuhashi, N. Goto (Toshiba Corp., Japan)

Session [A-8B] Application Specific Design

Chair: Hiroaki Kunieda (Tokyo Inst. of Technology, Japan)
Co-Chair: Tatsuya Fujii (NTT, Japan)

A-8B.1 Synthesis and Simulation of Digital Demodulator for Infrared Data Communication
Hiroshi Uno, Toru Chiba (SHARP Corp., Japan), Keiji Kumatani, Isao Shirakawa (Osaka Univ., Japan)

A-8B.2 A Design of High-Performance Multiplier for Digital Video Transmission
Keisuke Okada, Shun Morikawa, Isao Shirakawa (Osaka Univ., Japan), Sumitaka Takeuchi (Mitsubishi Electric Corp., Japan)

A-8B.3 Design Automation for Integrated Continuous-Time Filters Using Integrators
Kazuyuki Wada, Shigetaka Takagi, Zdzislaw Czarnul, Nobuo Fujii (Tokyo Inst. of Technology, Japan, Toshiba Corporation)

A-8B.4S A Hardware-Oriented Design for Weighted Median Filters
Chun-Te Chen, Liang-Gee Chen, Jue-Hsuan Hsiao (National Taiwan Univ., Taiwan)

A-8B.5S Techniques for Low Power Realization of FIR Filters
Mahesh Mehendale (Texas Instruments India Ltd., India), S. D. Sherlekar, G. Venkatesh (Silicon Automation Systems (India)Ltd.)

Session [A-8C] Invited Tutorial: EDIF Version 350/400 and Information Modelling

Chair: Mike Church (Zuken-Redac, UK)
Speaker: Hilary J. Kahn

Session [A-9A] Delay Abstraction/Design Verification

Chair: Kewal K. Saluja (Univ. of Wisconsin, USA)
Co-Chair: Kazuhiro Iwasaki (Chiba Univ., Japan)

A-9A.1 Delay Abstraction in Combinational Logic Circuits
Noriya Kobayashi (NEC Corp., Japan), Sharad Malik (Princeton Univ., USA)

A-9A.2 Limits of Using Signatures for Permutation Independent Boolean Comparison
Janett Mohnke, Paul Molitor (Martin-Luther Univ. Halle, Germany), Sharad Malik (Princeton Univ., USA)

A-9A.3 A Tool for Measuring Quality of Test Pattern for LSIs' Functional Design
Takashi Aoki, Tomoji Toriyama, Kenji Ishikawa, Kennosuke Fukami (NTT, Japan)

Session [A-9B] High Level Synthesis (2)

Chair: Youn-Long Steve Lin (Tsing Hua Univ., Taiwan)
Co-Chair: Vasily Moshnyaga (Kyoto Univ., Japan)

A-9B.1 Search Space Reduction in High Level Synthesis by Use of an Initial Circuit
Atsushi Masuda, Hiroshi Imai, Jeffery P. Hansen, Masatoshi Sekine(Toshiba Corp., Japan)

A-9B.2A Datapath Synthesis System for the Reconfigurable Datapath Architecture
Reiner W. Hartenstein, Rainer Kress (Univ. of Kaiserslautern, Germany)

A-9B.3 Synthesis-for-Testability Using Transformations
Miodrag Potkonjak, Sujit Dey, Rabindra K. Roy (NEC USA, USA)

Session [A-9C] Electronic Data Book: Current Status of Standard Representation and Future Perspective

Organizer: Kinya Tabuchi (Mitsubishi Electric Corp., Japan)
Chair: Kinya Tabuchi (Mitsubishi Electric Corp., Japan)
Panelists: Andy Graham (CFI, USA), Bob Yencha (Pinnacles Group, National Semiconductor, USA), Tom Jeffery (Pinnacles Group, Hitachi Micro Systems, USA), Toshitaka Fukushima (ELISNET, Fujitsu, Japan), Joe Prang (Aspect Development Inc., USA)