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ISLPED 2001 :
[ <A HREF="lpedabs.htm">Abstracts</A> ]
[ <A HREF="lpedsess.htm">Session Index</A> ]
[ <A HREF="lpedai.htm">Author Index</A> ]</H3>
<HR>
<H2>ISLPED 2001 Table of Contents</H2>
<B>
Sessions:
[<A HREF="#keynote">Keynote Speech</A>]
[<A HREF="#sess1">1</A>]
[<A HREF="#sess2">2</A>]
[<A HREF="#pos1">Poster Session 1</A>]
[<A HREF="#pos2">Poster Session 2</A>]
[<A HREF="#invited1">Invited Talk 1</A>]
[<A HREF="#sess3">3</A>]
[<A HREF="#sess4">4</A>]
[<A HREF="#sess5">5</A>]
[<A HREF="#sess6">6</A>]
[<A HREF="#invited2">Invited Talk 2</A>]
[<A HREF="#sess7">7</A>]
[<A HREF="#sess8">8</A>]
[<A HREF="#pos3">Poster Session 3</A>]
[<A HREF="#pos4">Poster Session 4</A>]
[<A HREF="#sess9">9</A>]
[<A HREF="#sess10">10</A>]
[<A HREF="#sess11">11</A>]
[<A HREF="#sess12">12</A>]
<P>
<A HREF="../../pdffiles/conforg.pdf">ISLPED'01 Conference Organization</A><P>
</B>
<HR>
<H2><A HREF="lpedabs.htm#keynote" NAME="keynote">
Keynote Speech
</A></H2>
<I>
Session Chair: Vivek De (Intel)
</I>
<DL>
<DT>
<A HREF="lpedabs.htm#p001"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p001.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Wireless Beyond the Third Generation: Facing the Energy Challenge [p. 1]
<DD><I>
Jan Rabaey (University of California, Berkeley)
</I><P>
</DL>
<HR>
<H2>Session 1: <A HREF="lpedabs.htm#sess1" NAME="sess1">
Energy Reduction in Processor Pipelines
</A></H2>
<I>
Session Chair: Pradip Bose (IBM)<BR>
Session Organizer: Steve Kosonocky (IBM)
</I>
<DL>
<DT>
<A HREF="lpedabs.htm#p004"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p004.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Micro-Operation Cache: A Power Aware Frontend for Variable
Instruction Length ISA [p. 4]
<DD><I>
Baruch Solomon, Avi Mendelson, Doron Orenstien, Yoav Almog, Ronny Ronen (Intel Corporation)
</I><P>
<DT>
<A HREF="lpedabs.htm#p010"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p010.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
L1 Data Cache Decomposition for Energy Efficiency [p. 10]
<DD><I>
Michael Huang, Jose Renau, Seung-Moon Yoo, Josep Torrellas (University of Illinois at Urbana-Champaign)
</I><P>
<DT>
<A HREF="lpedabs.htm#p016"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p016.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Instruction Flow-Based Front-end Throttling for Power-Aware
High-Performance Processors [p. 16]
<DD><I>
Amirali Baniasadi (Northwestern University), Andreas Moshovos (University of Toronto)
</I><P>
<DT>
<A HREF="lpedabs.htm#p022"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p022.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Energy Reduction in Queues and Stacks by Adaptive Bitwidth Compression [p. 22]
<DD><I>
Vasily G. Moshnyaga (Fukuoka University)
</I><P>
</DL>
<HR>
<H2>Session 2: <A HREF="lpedabs.htm#sess2" NAME="sess2">
Voltage and Instruction Scheduling
</A></H2>
<I>
Session Chair: TBD<BR>
Session Organizer: Luca Benini (University di Bologna)
</I>
<DL>
<DT>
<A HREF="lpedabs.htm#p028"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p028.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Energy Priority Scheduling for Variable Voltage Processors [p. 28]
<DD><I>
Johan Pouwelse, Koen Langendoen, Henk Sips (Delft University of Technology)
</I><P>
<DT>
<A HREF="lpedabs.htm#p034"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p034.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Dynamic Voltage Scheduling Technique for Low-Power Multimedia
Applications Using Buffers [p. 34]
<DD><I>
Chaeseok Im, Huiseok Kim, Soonhoi Ha (Seoul National University)
</I><P>
<DT>
<A HREF="lpedabs.htm#p040"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p040.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Power-Aware Modulo Scheduling for High-Performance VLIW Processors [p. 40]
<DD><I>
Han-Saem Yun, Jihong Kim (Seoul National University)
</I><P>
<DT>
<A HREF="lpedabs.htm#p046"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p046.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Hard Real-Time Scheduling for Low-Energy Using Stochastic Data and DVS
Processors [p. 46]
<DD><I>
Flavius Gruian (Lund University)
</I><P>
</DL>
<HR>
<H2><A HREF="lpedabs.htm#pos1" NAME="pos1">
Poster Session 1
</A></H2>
<I>
Session Chair: TBD
</I>
<DL>
<DT>
<A HREF="lpedabs.htm#p052"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p052.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Analysis and Design of Low-Energy Flip-Flops [p. 52]
<DD><I>
Dejan Markovi¾, Borivoje Nikoli¾, Robert W. Brodersen (University of California, Berkeley)
</I><P>
<DT>
<A HREF="lpedabs.htm#p056"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p056.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Analysis of Clocked Timing Elements for Dynamic Voltage Scaling Effects
over Process Parameter Variation [p. 56]
<DD><I>
Hoang Q. Dao (University of California, Davis), Kevin Nowka (IBM Austin Research Lab),
Vojin G. Oklobdzija (University of California, Davis)
</I><P>
<DT>
<A HREF="lpedabs.htm#p060"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p060.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
A Low-Power Motion Estimation Block for Low Bit-Rate Wireless Video* [p. 60]
<DD><I>
R. Steven Richmond, Dong Sam Ha (Virginia Tech)
</I><P>
<DT>
<A HREF="lpedabs.htm#p064"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p064.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Power-aware Partitioned Cache Architectures [p. 64]
<DD><I>
S. Kim, N. Vijaykrishnan, M. Kandemir, A. Sivasubramaniam, M. J. Irwin, E. Geethanjali
(Pennsylvania State University)
</I><P>
<DT>
<A HREF="lpedabs.htm#p068"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p068.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
A Low-Leakage Dynamic Multi-Ported Register File in 0.13µm CMOS [p. 68]
<DD><I>
Atila Alvandpour, Ram Krishnamurthy, K. Soumyanath, Shekhar Borkar (Intel Corporation)
</I><P>
<DT>
<A HREF="lpedabs.htm#p072"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p072.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Energy-Efficient Load and Store Reuse [p. 72]
<DD><I>
Jun Yang, Rajiv Gupta (The University of Arizona)
</I><P>
</DL>
<HR>
<H2><A HREF="lpedabs.htm#pos2" NAME="pos2">
Poster Session 2
</A></H2>
<I>
Session Chair: TBD
</I>
<DL>
<DT>
<A HREF="lpedabs.htm#p076"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p076.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Compiler Support for Block Buffering [p. 76]
<DD><I>
Mahmut Kandemir (The Pennsylvania State University), J. Ramanujam (Louisiana State University),
Uger Sezer (University of Wisconsin ö Madison)
</I><P>
<DT>
<A HREF="lpedabs.htm#p080"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p080.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Automatic Source Code Specialization for Energy Reduction [p. 80]
<DD><I>
Eui-Young Chung (Stanford University), Luca Benini (University di Bologna),
Giovanni De Micheli (Stanford University)
</I><P>
<DT>
<A HREF="lpedabs.htm#p084"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p084.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
FV Encoding for Low-Power Data I/O [p. 84]
<DD><I>
Jun Yang, Rajiv Gupta (The University of Arizona)
</I><P>
<DT>
<A HREF="lpedabs.htm#p088"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p088.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Time-to-Failure Estimation for Batteries in Portable Electronic Systems [p. 88]
<DD><I>
Daler Rakhmatov, Sarma B. K. Vrudhula (University of Arizona)
</I><P>
<DT>
<A HREF="lpedabs.htm#p092"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p092.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Architecture Strategies for Energy-Efficient Packet Forwarding
in Wireless Sensor Networks [p. 92]
<DD><I>
Vlasios Tsiatsis, Scott A. Zimbeck, Mani B. Srivastava (University of California, Los Angeles)
</I><P>
<DT>
<A HREF="lpedabs.htm#p096"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p096.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Modulation Scaling for Energy Aware Communication Systems [p. 96]
<DD><I>
Curt Schurgers, Olivier Aberthorne, Mani B. Srivastava (University of California, Los Angeles)
</I><P>
</DL>
<HR>
<H2><A HREF="lpedabs.htm#invited1" NAME="invited1">
Invited Talk 1
</A></H2>
<I>
Session Chair: Murli Tirumala (Intel)
</I>
<DL>
<DT>
<A HREF="lpedabs.htm#p100"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p100.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Cooling and Power Considerations for Semiconductors into the Next
Century [p. 100]
<DD><I>
Christian Belady (Hewlett Packard)
</I><P>
</DL>
<HR>
<H2>Session 3: <A HREF="lpedabs.htm#sess3" NAME="sess3">
Low Power RF Circuits and Systems
</A></H2>
<I>
Session Chair: Frank Chang (UCLA)
Session Organizer: Satyen Mukherjee (Phillips)
</I>
<DL>
<DT>
<A HREF="lpedabs.htm#p106"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p106.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Energy Efficient Modulation and MAC for Asymmetric RF Microsensor Systems [p. 106]
<DD><I>
Andrew Y. Wang, SeongHwan Cho, Charles G. Sodini, Anantha P. Chandrakasan
(Massachusetts Institute of Technology)
</I><P>
<DT>
<A HREF="lpedabs.htm#p112"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p112.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
A 1 V, 1.9 GHz Mixer Using a Lateral Bipolar Transistor in CMOS [p. 112]
<DD><I>
Song Ye (University of Toronto), Koji Yano (Yamanashi University),
C. Andre T. Salama (University of Toronto)
</I><P>
<DT>
<A HREF="lpedabs.htm#p117"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p117.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
A 60dB, 246MHz CMOS Variable Gain Amplifier for Subsampling
GSM Receivers [p. 117]
<DD><I>
Mohamed A. I. Mostafa (Texas A&M University), Sherif H. K. Embabi (Texas Instruments Inc.),
Mostafa A. I. Elmala (Texas A&M University)
</I><P>
</DL>
<HR>
<H2>Session 4: <A HREF="lpedabs.htm#sess4" NAME="sess4">
Modeling and Estimation Techiques
</A></H2>
<I>
Session Chair: Wolfgang Nebel (Univ. Oldenburg)<BR>
Session Organizer: Radu Marculescu (Carnegie Mellon University)
</I>
<DL>
<DT>
<A HREF="lpedabs.htm#p123"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p123.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
VTCMOS Characteristics and Its Optimum Conditions Predicted
by a Compact Analytical Model [p. 123]
<DD><I>
Hyunsik Im, T. Inukai, H. Gomyo, T. Hiramoto, T. Sakurai (University of Tokyo)
</I><P>
<DT>
<A HREF="lpedabs.htm#p129"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p129.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Memory Controller Policies for DRAM Power Management [p. 129]
<DD><I>
Xiaobo Fan, Carla S. Ellis, Alvin R. Lebeck (Duke University)
</I><P>
<DT>
<A HREF="lpedabs.htm#p135"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p135.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Run-Time Power Estimation in High Performance Microprocessors [p. 135]
<DD><I>
Russ Joseph, Margaret Martonosi (Princeton University)
</I><P>
<DT>
<A HREF="lpedabs.htm#p141"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p141.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Fast, Flexible, Cycle-Accurate Energy Estimation [p. 141]
<DD><I>
Phillip Stanley-Marbell, Michael S. Hsiao (Rutgers University)
</I><P>
</DL>
<HR>
<H2>Session 5: <A HREF="lpedabs.htm#sess5" NAME="sess5">
Low Power Digital Circuits
</A></H2>
<I>
Session Chair: Borivoje Nikolic (University of California, Berkeley)<BR>
Session Organizer: Tadahiro Kuroda (Keio University)
</I>
<DL>
<DT>
<A HREF="lpedabs.htm#p147"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p147.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Comparative Delay and Energy of Single Edge-Triggered & Dual
Edge-Triggered Pulsed Flip-Flops for High-Performance Microprocessors [p. 147]
<DD><I>
James Tschanz, Siva Narendra, Zhanping Chen, Shekhar Borkar, Vivek De (Intel Corporation),
Manoj Sachdev (University of Waterloo)
</I><P>
<DT>
<A HREF="lpedabs.htm#p153"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p153.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Theory and Practical Implementation of Harmonic Resonant Rail Driver [p. 153]
<DD><I>
Joong-Seok Moon, Peter A. Beerel, (University of Southern California),
William C. Athas (Apple Computer)
</I><P>
<DT>
<A HREF="lpedabs.htm#p159"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p159.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
A Resonant Clock Generator for Single-Phase Adiabatic Systems [p. 159]
<DD><I>
Conrad H. Ziesle, Marios C. Papaefthymiou, (University of Michigan),
Suhwan Kim (IBM T.J. Watson Research Center)
</I><P>
<DT>
<A HREF="lpedabs.htm#p165"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p165.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Enhanced Multi-Threshold (MTCMOS) Circuits Using Variable Well Bias [p. 165]
<DD><I>
Stephen V. Kosonocky, Mike Immediato (IBM T.J. Watson Research Center), Peter Cottrell,
Terence Hook, Randy Mann, Jeff Brown (IBM Microelectronics)
</I><P>
</DL>
<HR>
<H2>Session 6: <A HREF="lpedabs.htm#sess6" NAME="sess6">
Bus Encoding
</A></H2>
<I>
Session Chair: Masahiro Asada (Univ. of Tokyo)<BR>
Session Organizer: Renu Mehra (Synopsys)
</I>
<DL>
<DT>
<A HREF="lpedabs.htm#p170"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p170.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Encodings for High-Performance Energy-Efficient Signaling [p. 170]
<DD><I>
Alessandro Bogliolo (University of Ferrara)
</I><P>
<DT>
<A HREF="lpedabs.htm#p176"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p176.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Low-Energy Encoding for Deep-Submicron Address Buses [p. 176]
<DD><I>
Luca Macchiarulo, Enrico Macii, Massimo Poncino (Politecnico di Torino)
</I><P>
<DT>
<A HREF="lpedabs.htm#p182"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p182.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Irredundant Address Bus Encoding for Low Power [p. 182]
<DD><I>
Yazdan Aghaghiri, Massoud Pedram, (University of Southern California),
Farzan Fallah (Fujitsu Laboratories of America)
</I><P>
<DT>
<A HREF="lpedabs.htm#p188"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p188.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Low Power Address Encoding using Self-Organizing Lists [p. 188]
<DD><I>
Mahesh Mamidipaka, Dan Hirschberg, Nikil Dutt (University of California, Irvine)
</I><P>
</DL>
<HR>
<H2><A HREF="lpedabs.htm#invited2" NAME="invited2">
Invited Talk 2
</A></H2>
<I>
Session Chair: Ingrid Verbauwhede (UCLA)
</I>
<DL>
<DT>
<A HREF="lpedabs.htm#p194"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p194.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Wireless Sensor Networks: Application Driver for Low Power
Distributed Systems [p. 194]
<DD><I>
Deborah Estrin (University of California, Los Angeles)
</I><P>
</DL>
<HR>
<H2>Session 7: <A HREF="lpedabs.htm#sess7" NAME="sess7">
Technology for Low Power
</A></H2>
<I>
Session Chair: Fari Assaderaghi (SiliconWave)<BR>
Session Organizer: Rajiv Joshi (IBM)
</I>
<DL>
<DT>
<A HREF="lpedabs.htm#p195"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p195.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Scaling of Stack Effect and its Application for Leakage Reduction [p. 195]
<DD><I>
Siva Narendra (Massachusetts Institute of Technology & Intel), Shekhar Borkar, Vivek De,
Dimitri Antoniadis (Intel), Anantha Chandrakasan (Massachusetts Institute of Technology)
</I><P>
<DT>
<A HREF="lpedabs.htm#p201"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p201.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Variable Threshold Voltage CMOS (VTCMOS) in Series Connected Circuits [p. 201]
<DD><I>
Takashi Inukai, Toshiro Hiramoto, Takayasu Sakurai (University of Tokyo)
</I><P>
<DT>
<A HREF="lpedabs.htm#p207"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p207.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Effectiveness of Reverse Body Bias for Leakage Control
in Scaled Dual Vt CMOS ICS [p. 207]
<DD><I>
A. Keshavarzi, S. Ma, S. Narendra, B. Bloechel, K. Mistry, T. Ghani, S. Borkar, V. De (Intel Corporation)
</I><P>
<DT>
<A HREF="lpedabs.htm#p213"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p213.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Double-Gate Fully-Depleted SOI Transistors for Low-Power High-Performance
Nano-Scale Circuit Design [p. 213]
<DD><I>
Rongtian Zhang, Kaushik Roy, David B. Janes (Purdue University)
</I><P>
</DL>
<HR>
<H2>Session 8: <A HREF="lpedabs.htm#sess8" NAME="sess8">
Architectural Techniques
</A></H2>
<I>
Session Chair: Sumit Roy (Cadence)<BR>
Session Organizer: M. Poncino (Politecnico di Torino)
</I>
<DL>
<DT>
<A HREF="lpedabs.htm#p219"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p219.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
A Self-Optimizing Embedded Microprocessor using a Loop Table
for Low Power [p. 219]
<DD><I>
Frank Vahid, Ann Gordon-Ross (University of California, Riverside)
</I><P>
<DT>
<A HREF="lpedabs.htm#p225"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p225.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Low Power Pipelining of Linear Systems: A Common Operand
Centric Approach [p. 225]
<DD><I>
Daehong Kim, Kiyoung Choi, (Seoul National University),
Dongwan Shin (University of California, Irvine)
</I><P>
<DT>
<A HREF="lpedabs.htm#p231"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p231.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
A System-level Energy Minimization Approach using Datapath
Width Optimization [p. 231]
<DD><I>
Yun Cao, Hiroto Yasuura (Kyushu University)
</I><P>
<DT>
<A HREF="lpedabs.htm#p237"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p237.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Energy-Efficient Instruction Dispatch Buffer Design for Superscalar Processors
[p. 237]
<DD><I>
Gurhan Kucuk, Kanad Ghose, Dmitry V. Ponomarev (State University of New York),
Peter M. Kogge (University of Notre Dame)
</I><P>
</DL>
<HR>
<H2><A HREF="lpedabs.htm#pos3" NAME="pos3">
Poster Session 3
</A></H2>
<I>
Session Chair: Sudhir Gowda (IBM)
</I>
<DL>
<DT>
<A HREF="lpedabs.htm#p243"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p243.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
High Density Capacitance Structures in Submicron CMOS for Low Power
RF Applications [p. 243]
<DD><I>
Tirdad Sowlati, Vickram Vathulya, Domine Leenaerts (Philips Research)
</I><P>
<DT>
<A HREF="lpedabs.htm#p247"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p247.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
A CMOS VCO Architecture Suitable for Sub-1 Volt High-Frequency
(8.7-10 GHz) RF Applications [p. 247]
<DD><I>
Ahmed H. Mostafa, Mourad N. El-Gamal (McGill University)
</I><P>
<DT>
<A HREF="lpedabs.htm#p251"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p251.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Low-Power Direct Sequence Spread-Spectrum Modem Architecture [p. 251]
<DD><I>
Charles Chien, Igor Elgorria (Rockwell Research), Charles McConaghy (Livermore National Lab)
</I><P>
<DT>
<A HREF="lpedabs.htm#p255"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p255.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Effects of Elevated Temperature on Tunable Near-Zero Threshold CMOS [p. 255]
<DD><I>
Vjekoslav Svilan, G. Leonard Tyler (Stanford University), James B. Burr (Sun Microsystems)
</I><P>
<DT>
<A HREF="lpedabs.htm#p259"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p259.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
A Sub-1V Dual-Threshold Domino Circuit Using Product-of-Sum Logic [p. 259]
<DD><I>
Koji Fujii, Takakuni Douseki, Yuichi Kado (NTT Telecommunications Energy Laboratories)
</I><P>
<DT>
<A HREF="lpedabs.htm#p263"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p263.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Mixed Multi-Threshold Differential Cascode Voltage Switch (MT-DCVS)
Circuit Styles and Strategies for Low Power VLSI Design [p. 263]
<DD><I>
W. Chen, W. Hwang, P. Kudva, G. D. Gristede, S. Kosonocky,
R. V. Joshi (IBM T. J. Watson Research Center)
</I><P>
<DT>
<A HREF="lpedabs.htm#p267"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p267.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Selectively Clocked Skewed Logic (SCSL): A Robust Low-Power Logic
Style for High-Performance Applications [p. 267]
<DD><I>
Naran Sirisantana, Aiqun Cao, Shawn Davidson, Cheng-Kok Koh, Kaushik Roy (Purdue University)
</I><P>
</DL>
<HR>
<H2><A HREF="lpedabs.htm#pos4" NAME="pos4">
Poster Session 4
</A></H2>
<I>
Session Chair: Giovanni DeMicheli (Stanford)
</I>
<DL>
<DT>
<A HREF="lpedabs.htm#p271"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p271.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
A Profile-Based Energy-Efficient Intra-Task Voltage Scheduling Algorithm
for Hard Real-Time Applications [p. 271]
<DD><I>
Dongkun Shin, Jihong Kim (Seoul National University)
</I><P>
<DT>
<A HREF="lpedabs.htm#p275"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p275.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Compiler-Directed Dynamic Voltage/Frequency Scheduling for Energy
Reduction in Microprocessors [p. 275]
<DD><I>
Chung-Hsing Hsu, Ulrich Kremer, Michael Hsiao (Rutgers University)
</I><P>
<DT>
<A HREF="lpedabs.htm#p279"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p279.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Variable Voltage Task Scheduling Algorithms for Minimizing Energy [p. 279]
<DD><I>
Ali Manzak, Chaitali Chakrabarti (Arizona State University)
</I><P>
<DT>
<A HREF="lpedabs.htm#p283"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p283.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Design Methodology and Optimization Strategy for Dual-VTH Scheme Using
Commercially Available Tools [p. 283]
<DD><I>
Masayuki Hirabayashi, Koichi Nose, Takayasu Sakurai (University of Tokyo)
</I><P>
<DT>
<A HREF="lpedabs.htm#p287"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p287.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Synthesis of Low-Leakage PD-SOI Circuits with Body-Biasing [p. 287]
<DD><I>
Mario R. Casu, Gianluca Piccinini, Guido Masera, Maurizio Zamboni, (Politecnico di Torino)
</I><P>
<DT>
<A HREF="lpedabs.htm#p291"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p291.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Low-Power Technology Mapping for Mixed-Swing Logic [p. 291]
<DD><I>
Nicola Dragone (Carnegie Mellon University & PDF Solutions), Rob A. Rutenbar, L. Richard Carley
(Carnegie Mellon University), Roberto Zafalon (Carnegie Mellon University & STMicroelectronics)
</I><P>
<DT>
<A HREF="lpedabs.htm#p295"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p295.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Frequency-Domain Supply Current Macro-Model [p. 295]
<DD><I>
Srinivas Bodapati (University of Illinois at Urbana-Champaign), Farid N. Najm (University of Toronto)
</I><P>
</DL>
<HR>
<H2>Session 9: <A HREF="lpedabs.htm#sess9" NAME="sess9">
Low Power Analog Techniques
</A></H2>
<I>
Session Chair: Supher Gouda (IBM)<BR>
Session Organizer: Ken Yang (University of California, Los Angeles)
</I>
<DL>
<DT>
<A HREF="lpedabs.htm#p299"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p299.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
A Low-Power, 5-70MHz, 7th-Order Filter with Programmable Boost,
Group Delay, and Gain Using Instantaneous Companding [p. 299]
<DD><I>
Rola A. Baki, Mourad N. El-Gamal (McGill University)
</I><P>
<DT>
<A HREF="lpedabs.htm#p305"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p305.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Optimizing Bias-circuit Design of Cascode Operational Amplifier
for Wide Dynamic Range Operations [p. 305]
<DD><I>
Takeshi Fukumoto, Hiroyuki Okada, Kazuyuki Nakamura (NEC Corporation)
</I><P>
<DT>
<A HREF="lpedabs.htm#p310"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p310.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Leakage Current Cancellation Technique for Low Power Switched-Capacitor
Circuits [p. 310]
<DD><I>
Louis S. Y. Wong, Shohan Hossain, Andre Walker (St. Jude Medical)
</I><P>
<DT>
<A HREF="lpedabs.htm#p316"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p316.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
A 3-Pin 1.5 V 550 µmW 176 x 144 Self-Clocked CMOS Active
Pixel Image Sensor [p. 316]
<DD><I>
Kwang-Bo Cho, Alexander Krymski, Eric R. Fossum (Photobit Technology Corporation)
</I><P>
</DL>
<HR>
<H2>Session 10: <A HREF="lpedabs.htm#sess10" NAME="sess10">
Algorithmic Transformations and Caching
</A></H2>
<I>
Session Chair: T.N. Vijaykumar (Purdue)<BR>
Session Organizer: Babak Falsafi (Carnegie Mellon University)
</I>
<DL>
<DT>
<A HREF="lpedabs.htm#p322"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p322.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Cached-Code Compression for Energy Minimization in Embedded Processors [p. 322]
<DD><I>
Luca Benini (Universita di Bologna), Alberto Macii (Politecnico di Torino),
Alberto Nannarelli (Universita di Roma)
</I><P>
<DT>
<A HREF="lpedabs.htm#p328"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p328.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Energy Efficient Turbo Decoding for 3G Mobile [p. 328]
<DD><I>
David Garrett, Bing Xu, Chris Nicol (Lucent Technologies)
</I><P>
<DT>
<A HREF="lpedabs.htm#p334"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p334.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Low-Power AEC-Based MIMO Signal Processing for Gigabit
Ethernet 1000Base-T Transceivers [p. 334]
<DD><I>
Lei Wang, Naresh R. Shanbhag (University of Illinois at Urbana-Champaign)
</I><P>
<DT>
<A HREF="lpedabs.htm#p340"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p340.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Power Reduction through Work Reuse [p. 340]
<DD><I>
Emil Talpes, Diana Marculescu (Carnegie Mellon University)
</I><P>
</DL>
<HR>
<H2>Session 11: <A HREF="lpedabs.htm#sess11" NAME="sess11">
Low Power Digital Building Blocks
</A></H2>
<I>
Session Chair: David Garrett (Lucent Technologies)<BR>
Session Organizer: Donald Steiss (Mindspring)
</I>
<DL>
<DT>
<A HREF="lpedabs.htm#p346"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p346.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Clocking Strategies and Scannable Latches for Low Power Applications [p. 346]
<DD><I>
V. Zyuban, D. Meltzer (IBM T. J. Watson Research Center)
</I><P>
<DT>
<A HREF="lpedabs.htm#p352"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p352.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Ultra-Low Power DLMS Adaptive Filter for Hearing Aid Applications [p. 352]
<DD><I>
Hyung-il Kim, Kaushik Roy (Purdue University)
</I><P>
<DT>
<A HREF="lpedabs.htm#p358"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p358.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
A Dynamic-SDRAM-Mode-Control Scheme for Low-Power Systems
with a 32-bit RISC CPU [p. 358]
<DD><I>
Seiji Miura, Kazushige Ayukawa, Takao Watanabe (Hitachi, Ltd.)
</I><P>
<DT>
<A HREF="lpedabs.htm#p364"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p364.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Analysis and Implementation of Charge Recycling for Deep Sub-micron Buses [p. 364]
<DD><I>
Paul P. Sotiriadis, Theodoros Konstantakopoulos, Anantha Chandrakasan
(Massachusetts Institute of Technology)
</I><P>
</DL>
<HR>
<H2>Session 12: <A HREF="lpedabs.htm#sess12" NAME="sess12">
Power Supply and Delivery
</A></H2>
<I>
Session Chair: Farid Najm (University of Toronto)<BR>
Session Organizer: Ed Huijbregts (Magma)
</I>
<DL>
<DT>
<A HREF="lpedabs.htm#p370"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p370.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Estimation of Power Distribution in VLSI Interconnects [p. 370]
<DD><I>
Youngsoo Shin, Takayasu Sakurai (University of Tokyo)
</I><P>
<DT>
<A HREF="lpedabs.htm#p376"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p376.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Maximum Voltage Variation in the Power Distribution Network of VLSI
Circuits with RLC Models [p. 376]
<DD><I>
Sudhakar Bobba (Sun Microsystems Inc.), Ibrahim N. Hajj (American University of Beirut)
</I><P>
<DT>
<A HREF="lpedabs.htm#p382"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p382.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Battery Capacity Measurement and Analysis using Lithium Coin Cell Battery [p. 382]
<DD><I>
Sung Park, Andreas Savvides, Mani B. Srivastava (University of California, Los Angeles)
</I><P>
<DT>
<A HREF="lpedabs.htm#p388"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p388.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
On the Interaction of Power Distribution Network with Substrate [p. 388]
<DD><I>
Rajendran Panda, Savithri Sundareswaran, David Blaauw (Motorola, Inc.)
</I><P>
</DL>
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