ISLPED 2001 Table of Contents

ISLPED'01 Conference Organization

Keynote Speech

Wireless Beyond the Third Generation: Facing the Energy Challenge [p. 1]

Jan Rabaey (University of California, Berkeley)

Session 1: Energy Reduction in Processor Pipelines

Micro-Operation Cache: A Power Aware Frontend for Variable Instruction Length ISA [p. 4]

Baruch Solomon, Avi Mendelson, Doron Orenstien, Yoav Almog, Ronny Ronen (Intel Corporation)

L1 Data Cache Decomposition for Energy Efficiency [p. 10]

Michael Huang, Jose Renau, Seung-Moon Yoo, Josep Torrellas (University of Illinois at Urbana-Champaign)

Instruction Flow-Based Front-end Throttling for Power-Aware High-Performance Processors [p. 16]

Amirali Baniasadi (Northwestern University), Andreas Moshovos (University of Toronto)

Energy Reduction in Queues and Stacks by Adaptive Bitwidth Compression [p. 22]

Vasily G. Moshnyaga (Fukuoka University)

Session 2: Voltage and Instruction Scheduling

Energy Priority Scheduling for Variable Voltage Processors [p. 28]

Johan Pouwelse, Koen Langendoen, Henk Sips (Delft University of Technology)

Dynamic Voltage Scheduling Technique for Low-Power Multimedia Applications Using Buffers [p. 34]

Chaeseok Im, Huiseok Kim, Soonhoi Ha (Seoul National University)

Power-Aware Modulo Scheduling for High-Performance VLIW Processors [p. 40]

Han-Saem Yun, Jihong Kim (Seoul National University)

Hard Real-Time Scheduling for Low-Energy Using Stochastic Data and DVS Processors [p. 46]

Flavius Gruian (Lund University)

Poster Session 1

Analysis and Design of Low-Energy Flip-Flops [p. 52]

Dejan Markovi¾, Borivoje Nikoli¾, Robert W. Brodersen (University of California, Berkeley)

Analysis of Clocked Timing Elements for Dynamic Voltage Scaling Effects over Process Parameter Variation [p. 56]

Hoang Q. Dao (University of California, Davis), Kevin Nowka (IBM Austin Research Lab), Vojin G. Oklobdzija (University of California, Davis)

A Low-Power Motion Estimation Block for Low Bit-Rate Wireless Video* [p. 60]

R. Steven Richmond, Dong Sam Ha (Virginia Tech)

Power-aware Partitioned Cache Architectures [p. 64]

S. Kim, N. Vijaykrishnan, M. Kandemir, A. Sivasubramaniam, M. J. Irwin, E. Geethanjali (Pennsylvania State University)

A Low-Leakage Dynamic Multi-Ported Register File in 0.13µm CMOS [p. 68]

Atila Alvandpour, Ram Krishnamurthy, K. Soumyanath, Shekhar Borkar (Intel Corporation)

Energy-Efficient Load and Store Reuse [p. 72]

Jun Yang, Rajiv Gupta (The University of Arizona)

Poster Session 2

Compiler Support for Block Buffering [p. 76]

Mahmut Kandemir (The Pennsylvania State University), J. Ramanujam (Louisiana State University), Uger Sezer (University of Wisconsin ö Madison)

Automatic Source Code Specialization for Energy Reduction [p. 80]

Eui-Young Chung (Stanford University), Luca Benini (University di Bologna), Giovanni De Micheli (Stanford University)

FV Encoding for Low-Power Data I/O [p. 84]

Jun Yang, Rajiv Gupta (The University of Arizona)

Time-to-Failure Estimation for Batteries in Portable Electronic Systems [p. 88]

Daler Rakhmatov, Sarma B. K. Vrudhula (University of Arizona)

Architecture Strategies for Energy-Efficient Packet Forwarding in Wireless Sensor Networks [p. 92]

Vlasios Tsiatsis, Scott A. Zimbeck, Mani B. Srivastava (University of California, Los Angeles)

Modulation Scaling for Energy Aware Communication Systems [p. 96]

Curt Schurgers, Olivier Aberthorne, Mani B. Srivastava (University of California, Los Angeles)

Invited Talk 1

Cooling and Power Considerations for Semiconductors into the Next Century [p. 100]

Christian Belady (Hewlett Packard)

Session 3: Low Power RF Circuits and Systems

Energy Efficient Modulation and MAC for Asymmetric RF Microsensor Systems [p. 106]

Andrew Y. Wang, SeongHwan Cho, Charles G. Sodini, Anantha P. Chandrakasan (Massachusetts Institute of Technology)

A 1 V, 1.9 GHz Mixer Using a Lateral Bipolar Transistor in CMOS [p. 112]

Song Ye (University of Toronto), Koji Yano (Yamanashi University), C. Andre T. Salama (University of Toronto)

A 60dB, 246MHz CMOS Variable Gain Amplifier for Subsampling GSM Receivers [p. 117]

Mohamed A. I. Mostafa (Texas A&M University), Sherif H. K. Embabi (Texas Instruments Inc.), Mostafa A. I. Elmala (Texas A&M University)

Session 4: Modeling and Estimation Techiques

VTCMOS Characteristics and Its Optimum Conditions Predicted by a Compact Analytical Model [p. 123]

Hyunsik Im, T. Inukai, H. Gomyo, T. Hiramoto, T. Sakurai (University of Tokyo)

Memory Controller Policies for DRAM Power Management [p. 129]

Xiaobo Fan, Carla S. Ellis, Alvin R. Lebeck (Duke University)

Run-Time Power Estimation in High Performance Microprocessors [p. 135]

Russ Joseph, Margaret Martonosi (Princeton University)

Fast, Flexible, Cycle-Accurate Energy Estimation [p. 141]

Phillip Stanley-Marbell, Michael S. Hsiao (Rutgers University)

Session 5: Low Power Digital Circuits

Comparative Delay and Energy of Single Edge-Triggered & Dual Edge-Triggered Pulsed Flip-Flops for High-Performance Microprocessors [p. 147]

James Tschanz, Siva Narendra, Zhanping Chen, Shekhar Borkar, Vivek De (Intel Corporation), Manoj Sachdev (University of Waterloo)

Theory and Practical Implementation of Harmonic Resonant Rail Driver [p. 153]

Joong-Seok Moon, Peter A. Beerel, (University of Southern California), William C. Athas (Apple Computer)

A Resonant Clock Generator for Single-Phase Adiabatic Systems [p. 159]

Conrad H. Ziesle, Marios C. Papaefthymiou, (University of Michigan), Suhwan Kim (IBM T.J. Watson Research Center)

Enhanced Multi-Threshold (MTCMOS) Circuits Using Variable Well Bias [p. 165]

Stephen V. Kosonocky, Mike Immediato (IBM T.J. Watson Research Center), Peter Cottrell, Terence Hook, Randy Mann, Jeff Brown (IBM Microelectronics)

Session 6: Bus Encoding

Encodings for High-Performance Energy-Efficient Signaling [p. 170]

Alessandro Bogliolo (University of Ferrara)

Low-Energy Encoding for Deep-Submicron Address Buses [p. 176]

Luca Macchiarulo, Enrico Macii, Massimo Poncino (Politecnico di Torino)

Irredundant Address Bus Encoding for Low Power [p. 182]

Yazdan Aghaghiri, Massoud Pedram, (University of Southern California), Farzan Fallah (Fujitsu Laboratories of America)

Low Power Address Encoding using Self-Organizing Lists [p. 188]

Mahesh Mamidipaka, Dan Hirschberg, Nikil Dutt (University of California, Irvine)

Invited Talk 2

Wireless Sensor Networks: Application Driver for Low Power Distributed Systems [p. 194]

Deborah Estrin (University of California, Los Angeles)

Session 7: Technology for Low Power

Scaling of Stack Effect and its Application for Leakage Reduction [p. 195]

Siva Narendra (Massachusetts Institute of Technology & Intel), Shekhar Borkar, Vivek De, Dimitri Antoniadis (Intel), Anantha Chandrakasan (Massachusetts Institute of Technology)

Variable Threshold Voltage CMOS (VTCMOS) in Series Connected Circuits [p. 201]

Takashi Inukai, Toshiro Hiramoto, Takayasu Sakurai (University of Tokyo)

Effectiveness of Reverse Body Bias for Leakage Control in Scaled Dual Vt CMOS ICS [p. 207]

A. Keshavarzi, S. Ma, S. Narendra, B. Bloechel, K. Mistry, T. Ghani, S. Borkar, V. De (Intel Corporation)

Double-Gate Fully-Depleted SOI Transistors for Low-Power High-Performance Nano-Scale Circuit Design [p. 213]

Rongtian Zhang, Kaushik Roy, David B. Janes (Purdue University)

Session 8: Architectural Techniques

A Self-Optimizing Embedded Microprocessor using a Loop Table for Low Power [p. 219]

Frank Vahid, Ann Gordon-Ross (University of California, Riverside)

Low Power Pipelining of Linear Systems: A Common Operand Centric Approach [p. 225]

Daehong Kim, Kiyoung Choi, (Seoul National University), Dongwan Shin (University of California, Irvine)

A System-level Energy Minimization Approach using Datapath Width Optimization [p. 231]

Yun Cao, Hiroto Yasuura (Kyushu University)

Energy-Efficient Instruction Dispatch Buffer Design for Superscalar Processors [p. 237]

Gurhan Kucuk, Kanad Ghose, Dmitry V. Ponomarev (State University of New York), Peter M. Kogge (University of Notre Dame)

Poster Session 3

High Density Capacitance Structures in Submicron CMOS for Low Power RF Applications [p. 243]

Tirdad Sowlati, Vickram Vathulya, Domine Leenaerts (Philips Research)

A CMOS VCO Architecture Suitable for Sub-1 Volt High-Frequency (8.7-10 GHz) RF Applications [p. 247]

Ahmed H. Mostafa, Mourad N. El-Gamal (McGill University)

Low-Power Direct Sequence Spread-Spectrum Modem Architecture [p. 251]

Charles Chien, Igor Elgorria (Rockwell Research), Charles McConaghy (Livermore National Lab)

Effects of Elevated Temperature on Tunable Near-Zero Threshold CMOS [p. 255]

Vjekoslav Svilan, G. Leonard Tyler (Stanford University), James B. Burr (Sun Microsystems)

A Sub-1V Dual-Threshold Domino Circuit Using Product-of-Sum Logic [p. 259]

Koji Fujii, Takakuni Douseki, Yuichi Kado (NTT Telecommunications Energy Laboratories)

Mixed Multi-Threshold Differential Cascode Voltage Switch (MT-DCVS) Circuit Styles and Strategies for Low Power VLSI Design [p. 263]

W. Chen, W. Hwang, P. Kudva, G. D. Gristede, S. Kosonocky, R. V. Joshi (IBM T. J. Watson Research Center)

Selectively Clocked Skewed Logic (SCSL): A Robust Low-Power Logic Style for High-Performance Applications [p. 267]

Naran Sirisantana, Aiqun Cao, Shawn Davidson, Cheng-Kok Koh, Kaushik Roy (Purdue University)

Poster Session 4

A Profile-Based Energy-Efficient Intra-Task Voltage Scheduling Algorithm for Hard Real-Time Applications [p. 271]

Dongkun Shin, Jihong Kim (Seoul National University)

Compiler-Directed Dynamic Voltage/Frequency Scheduling for Energy Reduction in Microprocessors [p. 275]

Chung-Hsing Hsu, Ulrich Kremer, Michael Hsiao (Rutgers University)

Variable Voltage Task Scheduling Algorithms for Minimizing Energy [p. 279]

Ali Manzak, Chaitali Chakrabarti (Arizona State University)

Design Methodology and Optimization Strategy for Dual-VTH Scheme Using Commercially Available Tools [p. 283]

Masayuki Hirabayashi, Koichi Nose, Takayasu Sakurai (University of Tokyo)

Synthesis of Low-Leakage PD-SOI Circuits with Body-Biasing [p. 287]

Mario R. Casu, Gianluca Piccinini, Guido Masera, Maurizio Zamboni, (Politecnico di Torino)

Low-Power Technology Mapping for Mixed-Swing Logic [p. 291]

Nicola Dragone (Carnegie Mellon University & PDF Solutions), Rob A. Rutenbar, L. Richard Carley (Carnegie Mellon University), Roberto Zafalon (Carnegie Mellon University & STMicroelectronics)

Frequency-Domain Supply Current Macro-Model [p. 295]

Srinivas Bodapati (University of Illinois at Urbana-Champaign), Farid N. Najm (University of Toronto)

Session 9: Low Power Analog Techniques

A Low-Power, 5-70MHz, 7th-Order Filter with Programmable Boost, Group Delay, and Gain Using Instantaneous Companding [p. 299]

Rola A. Baki, Mourad N. El-Gamal (McGill University)

Optimizing Bias-circuit Design of Cascode Operational Amplifier for Wide Dynamic Range Operations [p. 305]

Takeshi Fukumoto, Hiroyuki Okada, Kazuyuki Nakamura (NEC Corporation)

Leakage Current Cancellation Technique for Low Power Switched-Capacitor Circuits [p. 310]

Louis S. Y. Wong, Shohan Hossain, Andre Walker (St. Jude Medical)

A 3-Pin 1.5 V 550 µmW 176 x 144 Self-Clocked CMOS Active Pixel Image Sensor [p. 316]

Kwang-Bo Cho, Alexander Krymski, Eric R. Fossum (Photobit Technology Corporation)

Session 10: Algorithmic Transformations and Caching

Cached-Code Compression for Energy Minimization in Embedded Processors [p. 322]

Luca Benini (Universita di Bologna), Alberto Macii (Politecnico di Torino), Alberto Nannarelli (Universita di Roma)

Energy Efficient Turbo Decoding for 3G Mobile [p. 328]

David Garrett, Bing Xu, Chris Nicol (Lucent Technologies)

Low-Power AEC-Based MIMO Signal Processing for Gigabit Ethernet 1000Base-T Transceivers [p. 334]

Lei Wang, Naresh R. Shanbhag (University of Illinois at Urbana-Champaign)

Power Reduction through Work Reuse [p. 340]

Emil Talpes, Diana Marculescu (Carnegie Mellon University)

Session 11: Low Power Digital Building Blocks

Clocking Strategies and Scannable Latches for Low Power Applications [p. 346]

V. Zyuban, D. Meltzer (IBM T. J. Watson Research Center)

Ultra-Low Power DLMS Adaptive Filter for Hearing Aid Applications [p. 352]

Hyung-il Kim, Kaushik Roy (Purdue University)

A Dynamic-SDRAM-Mode-Control Scheme for Low-Power Systems with a 32-bit RISC CPU [p. 358]

Seiji Miura, Kazushige Ayukawa, Takao Watanabe (Hitachi, Ltd.)

Analysis and Implementation of Charge Recycling for Deep Sub-micron Buses [p. 364]

Paul P. Sotiriadis, Theodoros Konstantakopoulos, Anantha Chandrakasan (Massachusetts Institute of Technology)

Session 12: Power Supply and Delivery

Estimation of Power Distribution in VLSI Interconnects [p. 370]

Youngsoo Shin, Takayasu Sakurai (University of Tokyo)

Maximum Voltage Variation in the Power Distribution Network of VLSI Circuits with RLC Models [p. 376]

Sudhakar Bobba (Sun Microsystems Inc.), Ibrahim N. Hajj (American University of Beirut)

Battery Capacity Measurement and Analysis using Lithium Coin Cell Battery [p. 382]

Sung Park, Andreas Savvides, Mani B. Srivastava (University of California, Los Angeles)

On the Interaction of Power Distribution Network with Substrate [p. 388]

Rajendran Panda, Savithri Sundareswaran, David Blaauw (Motorola, Inc.)