ASP-DAC 2000 Table of Contents

Sessions: [A1] [B1] [C1] [D1] [A2] [B2] [C2] [D2] [E2] [A3] [B3] [C3] [D3] [E3] [A4] [B4] [C4] [D4] [E4] [A5] [B5] [C5] [D5] [E5] [A6] [B6] [C6] [D6] [E6] [A7] [B7] [C7] [D7] [E7] [A8] [B8] [D8]

Organizing Committee
Steering Committee
General Chair's Message
Technical Program Committee
Technical Program Co-Chair's Message
Best Paper Award Candidates
University LSI Design Contest Committee
University LSI Design Contest Co-Chair's Message
University LSI Design Contest Summary
University LSI Design Contest Awards
Keynote Addresses
EDA Vendor Executive Panel

Session A1: (Special Session) University LSI Design Contest

Co-Chairs : Ryota Kasai, NTT, Japan
Anantha Chandrakasan, MIT, USA
A1.1 A VLSI Implementation of the Blowfish Encryption/Decryption Algorithm [p. 1]
Michael C.-J. Lin, Youn-L. Lin

A1.2 VLSI Implementation of Rake Receiver for IS-95 CDMA Testbed using FPGA [p. 3]
Oliver Y-h. Leung, Chi-Y.Tsui, Roger S. Cheng

A1.3 VLSI Implementation of a Switch Fabric for Mixed ATM and IP Traffic [p. 5]
Chi-Y. Tsui, Louis Chung-Y. Kwan, Chin-T. Lea

A1.4 Design of Digital Neural Cell Scheduler for Intelligent IB-ATM Switch [p. 7]
J.-K. Lee, S.-M. Lee, M.M.-O.Lee, D.-W. Lee, Y.-C. Kim, S.-J. Jeong

A1.5 Genetic Algorithm Accelerator GAA-II [p. 9]
Shin'ichi Wakabayashi, Tetsuhi Koide, Nayoshi Toshine, Masataka Yamane, Hajime Ueno

A1.6 A Programmable Built-In Self-Test Core for Embedded Memories [p. 11]
Chih-T. Huang, Jing-R. Huang, Cheng-W. Wu

A1.7 An Algorithm for VLSI Implementation of Highly Efficient Cubic-Polynomial Evaluation [p. 13]
Fan Mo, Yihua Zhang, Jun Yu, Qianling Zhang

A1.8 Design of Self-timed Asynchronous Boothâs multiplier [p. 15]
Tin-Y. Tang, Chin-S. Choy, Pui-L. Siu, Cheong-F. Chan

A1.9 High Speed and Ultra-Low Power 16x16 MAC Design using TG Techniques for Web-based Multimedia System [p. 17]
Seung-M. Lee, Jin-H. Chung, Hying-S. Yoon, Mike M-O. Lee

A1.10 A Smart Imager for the Vision Processing Front-END [p. 19]
Noriaki Takeda, Mituru Homma, Makoto Nagata, Takashi Morie, Atsushi Iwata

A1.11 A Binary Image Sensor with Flexible Motion Vector Detection using Block Matching Method [p. 21]
Tomohiro Nezuka, Takafumi Fujita, Makoto Ikeda, Kunihiro Asada

A1.12 An Arbitrary Chaos Generator Core Circuit Using PWM/PPM Signals [p. 23]
Kenichi Murakoshi, Takashi Morie, Makoto Nagata, Atushi Iwata

A1.13 An Application Specific Java Processor with Reconfigurabilities [p. 25]
Shinji Kimura, Hiroyuki Kida, Kazuyoshi Takagi, Tatsumori Abematsu, Katsumasa Watanabe

A1.14 Reconfigurable Synchronized Dataflow Processor [p. 27]
Hiroshi Sasaki, Hitoshi Maruyama, Hideaki Tsukioka, Nobuyoshi Shoji, Hiroaki Kobayashi, Tadao Nakamura

A1.15 Prototype Microprocessor LSI with Scheduling Support Hardware for Operating System on Multiprocessor System [p. 29]
Naoki Nishimura, Takahiro Sasaki, Tetsuo Hironaka

A1.16 A Floating Point Arithmetic Unit for a Static Scheduling and Compiler Oriented Multiprocessor System ASCA [p. 31]
Takahiro Kawaguchi, Takayuki Suzuki, Hideharu Amano

A1.17 A 16-bit Redundant Binary Multiplier Using Low-Power Pass-Transistor Logic SPL [p. 33]
Hirofumi Sakamoto, Ken'ichiro Uda, Bu-Y. Lee, Hiroyuki Ochi, Kazuo Taki, Takao Tsuda

A1.18 An 8x8 nRERL Serial Multiplier for Ultra-Low-Power Applications [p. 35]
Joonho Lim, Dong-G. Kim, Sang-C. Kang, Soo-I. Chae

Session B1: IP Reuse and Protection Methods

Co-Chairs : Graham R. Hellestrand, VaST Systems Technology Corp., USA
Minoru Yamamoto, Fujitsu Ltd., Japan
B1.1 Embedded Tutorial: Essential Issues for IP Reuse [p. 37]
Daniel D. Gajski, Allen C.-H. Wu, Viraphol Chaiyakul, Shojiro Mori, Tom Nukiyama, Pierre Bricaud

B1.2 Usage-Based Characterization of Complex Functional Blocks for Reuse in Behavioral Synthesis [p. 43]
Nong Fan, Viraphol Chaiyakul, Daniel D. Gajski

B1.3 Reuse and Protection of Intellectual Property in the SpecC System [p. 49]
Rainer Dömer, Daniel D. Gajski

B1.4 Fair Watermarking Techniques [p. 55]
Gang Qu, Jennifer L. Wong, Miodrag Potkonjak

Session C1: Decision Diagrams and Verification Methods

Co-Chairs : Yirng-An Chen, National Chiao Tung Univ., Taiwan
Kiyoharu Hamaguchi, Osaka Univ., Japan
C1.1 An Efficient Heuristic for State Encoding Minimizing the BDD Representations of the Transition Relations of Finite State Machines [p. 61]
Riccardo Forth, Paul Molitor

C1.2 Automatic Partitioning for Efficient Combinational Verification [p. 67]
Rajarshi Mukherjee, Jawahar Jain, Koichiro Takayama, Masahiro Fujita

C1.3 A Hardware Simulation Engine Based on Decision Diagrams (Short Paper) [p. 73]
Yukihiro Iguchi, Tsutomu Sasao, Munehiro Matsuura, Atsumu Iseno

C1.4 Formal Verification based on Assume and Guarantee Approach - A Case Study (Short Paper) [p. 77]
Subir K. Roy, Hiroaki Iwashita, Tsuneo Nakata

C1.5 Multi-Clock Path Analysis Using Propositional Satisfiability [p. 81]
Kazuhiro Nakamura, Shinji Maruoka, Shinji Kimura, Katsumasa Watanabe

Session D1: Routing in Deep-Submicron

Co-Chairs : Jason Cong, Univ. of California, Los Angeles, USA
Takumi Okamoto, NEC Corp., Japan
D1.1 Self-Reforming Routing for Stochastic Search in VLSI Interconnection Layout [p. 87]
Yukiko Kubo, Yasuhiro Takashima, Shigetoshi Nakatake, Yoji Kajitani

D1.2 An Interconnect Topology Optimization by a Tree Transformation [p. 93]
Naofumi Tsujii, Katsutoshi Baba, Shuji Tsukiyama

D1.3 Timing-Driven Hierarchical Global Routing with Wire-Sizing and Buffer-Insertion for VLSI with Multi-Routing-Layer [p. 99]
Takahiro Deguchi, Tetsushi Koide, Shin'ichi Wakabayashi

D1.4 Area Routing Oriented Hierarchical Corner Stitching with Partial Bin [p. 105]
Zhang Yan, Wang Baohua, Cai Yici, Hong Xianlong

Session A2: (Special Session) CAD for Embedded Systems

Chair : Miodrag Potkonjak, Univ. of California, Los Angeles, USA
A2.1 Offline Program Re-mapping to Improve Branch Prediction Efficiency in Embedded Systems [p. 111]
Stephen S. Brown, Jeet Asher, William H. Mangione-Smith

A2.2 Timing Driven Co-design of Networked Embedded Systems [p. 117]
Dinesh Ramanathan, Ravindra Jejurikar, Rajesh K. Gupta

A2.3 Low-power Design Methodology and Applications utilizing Dual Supply Voltages [p. 123]
Kimiyoshi Usami, Mutsunori Igarashi

A2.4 Co-Synthesis with custom ASICs [p. 129]
Yuan Xie, Wayne Wolf

Session B2: System-Level Power Optimization & Estimation

Co-Chairs : Akira Matsuzawa, Matsushita Electrical Industrial, Co. Ltd., Japan
Masato Edahiro, NEC Corp., Japan
B2.1 A New Method for Constructing IP Level Power Model Based on Power Sensitivity [p. 135]
Heng-Liang Huang, Jiing-Yuan Lin, Wen-Zen Shen, Jing-Yang Jou

B2.2 A hybrid approach for core-based system-level power modeling [p. 141]
Tony Givargis, Frank Vahid, Jörg Henkel

B2.3 Voltage Reduction of Application-Specific Heterogeneous Multiprocessor Systems for Power Minimisation [p. 147]
Allan Rae, Sri Parameswaran

B2.4 Withdrawn

B2.5 Synthesis of Low Power Folded Programmable Coefficient FIR Digital Filters (Short Paper) [p. 153]
Vijay Sundararajan, Keshab K. Parhi

Session C2: Design Environment for FPGA

Co-Chairs : Shinji Kimura, Nara Inst. of Science and Technology, Japan
Kazutoshi Wakabayashi, NEC Corp., Japan
C2.1 Invited Talk : Synthesis Challenges for Next-Generation High-Performance and High-Density PLDs [p. 157]
Jason Cong, Songjie Xu

C2.2 KressArray Xplorer: A New CAD Environment to Optimize Reconfigurable Datapath Array Architectures [p. 163]
Reiner Hartenstein, Michael Herz, Thomas Hoffmann, Ulrich Nageldinger

C2.3 Hardware-Software Cosynthesis for Run-time Incrementally Reconfigurable FPGAs [p. 169]
Byungil Jeong, Sungjoo Yoo, Sunghyun Lee, Kiyoung Choi

Session D2: Placement Consistent with Routing

Co-Chairs : Yu-Liang Wu, Chinese University of Hong Kong, China
Hiroshi Murata, Microark, Japan
D2.1 A New Encoding Scheme for Rectangle Packing Problem [p. 175]
Toshihiko Takahashi

D2.2 Analytical Minimization of Half-Perimeter Wirelength [p. 179]
Andrew A. Kennings, Igor L. Markov

D2.3 Modeling and Minimization of Routing Congestion [p. 185]
Maogang Wang, Majid Sarrafzadeh

Session E2: (Special Session) System-In-Package (SIP)

Chair : Wayne W.-M. Dai, Univ. of California, Santa Cruz, USA
E2.1 System-In-Package (SIP): Challenges and Opportunities [p. 191]
King L. Tai

E2.2 Taiwan Foundry for System-In-Package (SIP) [p. 197]
Albert Lin

E2.3 Integration of Large-Scale FPGA and DRAM in a Package Using Chip-On-Chip Technology [p. 205]
Michael X. Wang, Katsuharu Suzuki, Wayne W.-M. Dai, Yee L. Low, Kevin J. O'conner, King L. Tai

E2.4 Modeling and Analysis of Integrated Spiral Inductors for RF System-In-Package [p. 211]
Minqing Liu, Wayne W.-M. Dai

Session A3: Low Power Design : Implementation

Co-Chairs : Shoji Kawahito, Toyohashi Univ. of Technology, Japan
Jan M. Rabaey, Univ. of California, Berkeley, USA
A3.1 Narrow Bus Encoding for Low Power Systems [p. 217]
Youngsoo Shin, Kiyoung Choi

A3.2 Data Transmission over a Bus with Peak-Limited Transition Activity [p. 221]
Vijay Sundararajan, Keshab K. Parhi

A3.3 Power Analysis and Implementation of a Low-Power 300 MHz 8-b x 8-b Pipelined Multiplier [p. 225]
Jinn-Shyan Wang, Po-Hui Yang

Session B3: Embedded Software

Co-Chairs : Peter Marwedel, Univ. of Dortmund, Germany
Hiroaki Takada, Toyohashi University of Technology, Japan
B3.1 A New Approach to Assembly Software Retargeting for Microcontrollers [p. 229]
Ing-Jer Huang, Dao-Zhen Chen

B3.2 Register Allocation for Common Subexpressions in DSP Data Paths [p. 235]
Rainer Leupers

B3.3 A Technique for QoS-based System Partitioning [p. 241]
Johnson S. Kin, Chunho Lee, William H. Mangione-Smith, Miodrag Potkonjak

Session C3: Implementation of Boolean Functions

Co-Chairs : Yusuke Matsunaga, Fujitsu Laboratories, Ltd., Japan
Hiroyuki Ochi, Hiroshima City Univ., Japan
C3.1 Exact Minimization of Fixed Polarity Reed-Muller Expressions for Incompletely Specified Functions [p. 247]
Debatosh Debnath, Tsutomu Sasao

C3.2 An Efficient Framework of Using Various Decomposition Methods to Synthesize LUT Networks and Its Evaluation [p. 253]
Shigeru Yamashita, Hiroshi Sawada, Akira Nagoya

C3.3 Three Parameters to Find Functional Decompositions [p. 259]
Tsutomu Sasao, Ken-ichi Kurimoto

Session D3: Physical Design Planning

Co-Chairs : Wayne W.-M. Dai, Univ. of California, Santa Cruz, USA
Shuji Tsukiyama, Chuo Univ., Japan
D3.1 Delay-Optimal Wiring Plan for the Microprocessor of High Performance Computing Machines [p. 265]
Jun Kikuchi, Tetsuo Sasaki, Tohru Hashimoto, Kazuhisa Miyamoto

D3.2 MMP : A Novel Placement Algorithm for Combined Macro Block and Standard Cell Layout Design [p. 271]
Hong Yu, Xianlong Hong, Yici Cai

D3.3 Dynamic Weighting Monte Carlo for Constrained Floorplan Designs in Mixed Signal Application [p. 277]
Jason Cong, Tianming Kong, Faming Liang, Jun S. Liu, Wing Hung Wong, Dongmin Xu

Session E3: Methodologies for Reliable Design

Co-Chairs : Mitiko Miura-Mattausch, Hiroshima Univ., Japan
Andrzej J. Strojwas, Carnegie Mellon Univ., USA
E3.1 Symbolic Circuit-Noise Analysis and Modeling with Determinant Decision Diagrams [p. 283]
XiangDong Tan, C.-J. Richard Shi

E3.2 Gate-Level Aged Timing Simulation Methodology for Hot-Carrier Reliability Assurance [p. 289]
Yoshiyuki Kawakami, Jingkun Fang, Hirokazu Yonezawa, Nobufusa Iwanishi, Lifeng Wu, Alvin I-Hsien Chen, Norio Koike, Ping Chen, Chune-Sin Yeh, Zhihong Liu

E3.3 Embedded Tutorial : Subwavelength Lithography (PSM, OPC) [p. 295]
Tsuneo Terasawa

Session A4: Synthesis for System-On-A-Chip

Co-Chairs : Rolf Ernst, Technical Univ. Braunschweig, Germany
Ahmed A. Jerraya, TIMA Laboratory, France
A4.1 Embedded Tutorial : IC Design Technology for Building System-On-A-Chip [p. 301]
Rajesh Gupta

A4.2 Thread Partitioning Method for Hardware Compiler Bach [p. 303]
Mizuki Takahashi, Nagisa Ishiura, Akihisa Yamada, Takashi Kambe

A4.3 An Area/Time Optimizing Algorithm in High-Level Synthesis for Control-Based Hardwares (Short Paper) [p. 309]
Nozomu Togawa, Masayuki Ienaga, Masao Yanagisawa, Tatsuo Ohtsuki

A4.4 A Timing-Driven Synthesis of Arithmetic Circuits using Carry-Save-Adders (Short Paper) [p. 313]
Taewhan Kim, Junhyung Um

Session B4: Reconfigurable Computation

Co-Chairs : Toshiaki Miyazaki, NTT Network Innovation Laboratories, Japan
Tetsuo Hironaka, Hiroshima City Univ., Japan
B4.1 Communicating Logic : An Alternative Embedded Stream Processing Paradigm [p. 317]
Norbert Imlig, Ryusuke Konishi, Tsunemichi Shiozawa, Kiyoshi Oguri, Kouichi Nagami, Hideyuki Ito, Minoru Inamori, Hiroshi Nakada

B4.2 A Scheduling and Allocation Method to Reduce Data Transfer Time by Dynamic Reconfiguration [p. 323]
Kazuhito Ito

B4.3 Invited Talk : Reconfigurable Computing: Its Concept and a Practical Embodiment using Newly Developed Dynamically Reconfigurable Logic (DRL) LSI [p. 329]
Masakazu Yamashina, Masato Motomura

Session C4: Synthesis for Low Power

Co-Chairs : Akira Nagoya, NTT Communication Science Laboratories, Japan
Manish Pandey, Cadence Design Systems, Inc., USA
C4.1 Power Reduction by Simultaneous Voltage Scaling and Gate Sizing [p. 333]
Chunhong Chen, Majid Sarrafzadeh

C4.2 Analysis of Power-Clocked CMOS with Application to the Design of Energy-Recovery Circuits [p. 339]
Massoud Pedram, Xunwei Wu

C4.3 Low-Power Design of Sequential Circuits Using a Quasi-Synchronous Derived Clock [p. 345]
Xunwei Wu, Jian Wei, Massoud Pedram, Qing Wu

C4.4 FSM Decomposition by Direct Circuit Manipulation Applied to Low Power Design [p. 351]
José C. Monteiro, Arlindo L. Oliveira

Session D4: Panel Discussion

Timing Closure : The Solution and Its Problems [p. 359] Organizer: Ralph H.J.M. Otten, Delft University of Technology, The Netherlands
Moderator: Ralph H.J.M. Otten, Delft University of Technology, The Netherlands
Panelists:
Raul Camposano (Synopsys, Inc., USA)
Oliver Coudert (Monterey Design Systems, Inc., USA)
Patrick Groeneveld (Magma Design Automation, USA)
Leon Stok (Thomas J. Watson Research Center, IBM, USA)

Session E4: MOSFET Device Optimization

Co-Chairs : Naoyuki Shigyo, Toshiba Corp., Japan
C.-J. Richard Shi, Univ. of Washington, USA
E4.1 High Performance of Short-Channel MOSFETs due to an Elevated Central-Channel Doping [p. 365]
M. Tanaka, N. Tokida, T. Okagaki, M. Miura-Mattausch, W. Hansch, H. J. Mattausch

E4.2 Circuit Performance Oriented Device Optimization using BSIM3 Pre-Silicon Model Parameters [p. 371]
Mikako Miyama, Shiro Kamohara

E4.3 Embedded Tutorial : Design for Manufacturability : A Path from System Level to High Yielding Chips [p. 375]
Andrzej J. Strojwas

Session A5: Low Power Design : System Approach

Co-Chairs : Keshab K. Parhi, Univ. of Minnesota, USA
Koji Kotani, Tohoku Univ., Japan
A5.1 Embedded Tutorial : Low-Power Silicon Architectures for Wireless Communications [p. 377]
Jan M. Rabaey

A5.2 Run-time Power Control Scheme using Software Feedback Loop for Low-power Real-time Application [p. 381]
Seongsoo Lee, Takayasu Sakurai

A5.3 An Interleaved Dual-Battery Power Supply for Battery-Operated Electronics [p. 387]
Qing Wu, Qinru Qiu, Massoud Pedram

Session B5: System Design and Debugging

Co-Chairs : Rajesh Gupta, Univ. of California, Irvine, USA
Takashi Kambe, Sharp Corp., Japan
B5.1 Embedded Tutorial : Embedded System Design with Multiple Languages [p. 391]
Rolf Ernst, Ahmed A. Jerraya

B5.2 Symbolic Debugging of Globally Optimized Behavioral Specifications [p. 397]
Inki Hong, Darko Kirovski, Miodrag Potkonjak, Marios C. Papaefthymiou

B5.3 Fast Development of Source-level Debugging System Using Hardware Emulation (Short Paper) [p. 401]
Sang-Joon Nam, Jun-Hee Lee, Byoung-Woon Kim, Yeon-Ho Im, Young-Su Kwon, Kyong-Gu Kang, Chong-Min Kyung

B5.4 Methodology for Hardware/Software Co-verification in C/C++ (Short Paper) [p. 405]
Luc Séméria, Abhijit Ghosh

Session C5: Optimization Issues in Logic Synthesis

Co-Chairs : Tsutomu Sasao, Kyushu Inst. of Technology, Japan
Shin'ichi Minato, NTT Network Innovation Laboratories, Japan
C5.1 Performance-Optimal Clustering with Retiming for Sequential Circuits [p. 409]
Tzu-Chieh Tien, Youn-Long Lin

C5.2 IBAW: An Implication-Tree Based Alternative-Wiring Logic Transformation Algorithm [p. 415]
Wangning Long, Yu-Liang Wu, Jinian Bian

C5.3 On Mixture Density and Maximum Likelihood Power Estimation via Expectation-Maximization [p. 423]
R. Chandramouli, Vamsi K. Srikantam

Session D5: Novel Techniques in Advanced Partitioning

Co-Chairs : Shin'ichi Wakabayashi, Hiroshima Univ., Japan
Tetsushi Koide, Univ. of Tokyo, Japan
D5.1 Edge Separability Based Circuit Clustering with Application to Circuit Partitioning [p. 429]
Jason Cong, Sung Kyu Lim

D5.2 Feasible Two-Way Circuit Partitioning with Complex Resource Constraints [p. 435]
Hsun-Cheng Lee, Ting-Chi Wang

D5.3 Performance Driven Multiway Partitioning [p. 441]
Jason Cong, Sung Kyu Lim

Session E5: Efficient Estimation for Interconnection

Co-Chairs : Hiroshi Matsumoto, NEC Corp., Japan
Xianlong Hong, Tsinghua Univ., China
E5.1 Hierarchical Computation of 3-D Interconnect Capacitance using Direct Boundary Element Method [p. 447]
Jiangchun Gu, Zeyi Wang, Xianlong Hong

E5.2 A Simplified Hybrid Method for Calculating the Frequency-dependent Inductances of Transmission Lines with Rectangular Cross Section [p. 453]
Shuzhou Fang, Xiaobo Tang, Zeyi Wang, Xianlong Hong

E5.3 An Analytic Calculation Method for Delay Time of RC-class Interconnects [p. 457]
W. K. Kal, S. Y. Kim

E5.4 A New Efficient Waveform Simulation Method for RLC Interconnect via Amplitude and Phase Approximation [p. 463]
Xiaodong Yang, Walter H. Ku, Chung-Kuan Cheng

Session A6: Optimized LSI Design

Co-Chairs : Chong-Min Kyung, Korea Advanced Inst. of Science and Technology Korea
Takashi Morie, Hiroshima Univ., Japan
A6.1 Optimization of VDD and VTH for Low-Power and High Speed Applications [p. 469]
Koichi Nose, Takayasu Sakurai

A6.2 Compact yet High Performance (CyHP) Library for Short Time-to-Market with New Technologies [p. 475]
Nguyen Minh Duc, Takayasu Sakurai

A6.3 A New CMAC Neural Network Architecture and Its ASIC Realization [p. 481]
Yuan-Bao Hsu, Kao-Shing Hwang, Chien-Yuan Pao, Jinn-Shyan Wang

Session B6: DSP and Memory Architecture

Co-Chairs : Ichiro Kuroda, NEC Corp., Japan
Keshab K. Parhi, Univ. of Minnesota, USA
B6.1 Retargetable Estimation Scheme for DSP Architecture Selection [p. 485]
Naji Ghazal, Richard Newton, Jan Rabaey

B6.2 Data Memory Minimization by Sharing Large Size Buffers [p. 491]
Hyunok Oh, Soonhoi Ha

B6.3 Array Allocation Taking into Account SDRAM Characteristics [p. 497]
Hong-Kai Chang, Youn-Long Lin

Session C6: Validation and Test

Co-Chairs : Cheng-Wen Wu, Univ. of California, Santa Barbara, USA
Tomoo Inoue, Hiroshima City Univ., Japan
C6.1 Causality Based Generation Of Directed Test Cases [p. 503]
Nina Saxena, Jacob Abraham, Avijit Saha

C6.2 Embedded Tutorial : Fault Models and Test Generation for IDDQ Testing [p. 509]
Yoshinobu Higami, Yuzo Takamatsu, Kewal K. Saluja, Kozo Kinoshita

C6.3 Embedded Tutorial : Issues on SOC Testing in DSM Era [p. 515]
Takashi Aikyo

Session D6: Cell Generation & Process Dependent Issues

Co-Chairs : Jun-Dong Cho, Sungkyunkwan Univ., Korea
Yoichi Shiraishi, Gunma Univ., Japan
D6.1 A Cell Synthesis Method for Salicide Process [p. 517]
Kazuhisa Okada, Takayuki Yamanouchi, Takashi Kambe

D6.2 Monte-Carlo Algorithms for Layout Density Control [p. 523]
Yu Chen, Andrew B. Kahng, Gabriel Robins, Alex Zelikovsky

D6.3 Layout Generation of Array Cell for NMOS 4-phase Dynamic Logic (Short Paper) [p. 529]
Makoto Furuie, Bao-Yu Song, Yukihiro Yoshida, Takao Onoye, Isao Shirakawa

D6.4 A New Efficient Method for Substrate-Aware Device-Level Placement (Short Paper) [p. 533]
C. Lin, D. M. W. Leenaerts

Session E6: Analysis Techniques for Analog Circuits

Co-Chairs : Mineo Kaneko, Japan Advanced Inst. of Science and Technology, Japan
Peter M. Lee, Hitachi Ltd., Japan
E6.1 The Enhancing of Efficiency of the Harmonic Balance Analysis by Adaptation of Preconditioner to Circuit Nonlinearity [p. 537]
M.M. Gourary, S. G. Rusakov, S. L. Ulyanov, M.M. Zharov, K.K. Gullapalli, B.J. Mulvaney

E6.2 Analog-Testability Analysis by Determinant-Decision-Diagrams based Symbolic Analysis [p. 541]
Tao Pi, C.-J. Richard Shi

E6.3 A Method for Linking Process-level Variability to System Performances [p. 547]
Tomohiro Fujita, Ken-ichi Okada, Hiroaki Fujita, Hidetoshi Onodera, Keikichi Tamaru

Session A7: Advanced Design Techniques for Deep-Submicron System-On-A-Chip

Co-Chairs : Kazuo Yano, Hitachi, Ltd., Japan
Takao Onoye, Kyoto Univ., Japan
A7.1 Embedded Tutorial : Design Challenges for 0.1um and Beyond [p. 553]
Takayasu Sakurai

A7.2 A Hardware Accelerator for the Specular Intensity of Phong Illumination Model in 3-Dimensional Graphics [p. 559]
Young-Su Kwon, In-Cheol Park, Chong-Min Kyung

A7.3 Radix-4 Modular Multiplication and Exponentiation Algorithms for the RSA Public-Key Cryptosystem [p. 565]
Jin-Hua Hong, Cheng-Wen Wu

Session B7: (Special Session) Future of System Level Design Languages

Chair : Masaharu Imai, Osaka Univ., Japan
B7.1 An Introduction to SLDL and Rosetta [p. 571]
Steven E. Schulz, Texas Instruments, Inc., USA

B7.2 SystemC Standard [p. 573]
Guido Arnout

B7.3 Java Based Object Oriented Hardware Specification and Synthesis [p. 579]
Tommy Kuhn, Wolfgang Rosenstiel

B7.4 Superlog, A Unified Design Language for System-on-chip [p. 583]
Peter L. Flake, Simon J. Davidmann

Session C7: Delay Testing and Design-For-Testability

Co-Chairs : Yukiya Miura, Tokyo Metropolitan Univ., Japan
Hiroshi Date, Inst. of Systems & Information Technologies Kyushu, Japan
C7.1 Performance Sensitivity Analysis Using Statistical Method and Its Applications to Delay Testing [p. 587]
Jing-Jia Liou, Angela Krstic, Kwang-Ting Cheng, Deb Aditya Mukherjee, Sandip Kundu

C7.2 A Testability Metric for Path Delay Faults and Its Application [p. 593]
Huan-Chih Tsai, Kwang-Ting Cheng, Vishwani D. Agrawal

C7.3 A Non-Scan DFT Method at Register-Transfer Level to Achieve Complete Fault Efficiency [p. 599]
Satoshi Ohtake, Hiroki Wada, Toshimitsu Masuzawa, Hideo Fujiwara

C7.4 A Sigma-Delta Modulation Based BIST Scheme for Mixed-Signal Circuits [p. 605]
Jiun-Lang Huang, Kwang-Ting Cheng

Session D7: (Panel Discussion) Industry-Academia Cooperation [p. 611]

Organizer: Tokinori Kozawa, STARC, Japan
Moderator: Hiroto Yasuura, Kyushu Univ., Japan
Panelists:
Bill Joyner (SRC, USA)
Jan Rabaey (Univ. of California, Berkeley, USA)
Ivo Bolson (IMEC, Belgium)
Yoshiaki Masuhara (Hitachi Ltd., Japan)

Session E7: Signal Integrity / Noise Issues in Deep-Submicron

Co-Chairs : Hidetoshi Onodera, Kyoto Univ., Japan
Nobuo Fujii, Tokyo Inst. of Technology, Japan
E7.1 A 12b 50 MHz 3.3V CMOS Acquisition Time Minimized A/D Converter [p. 613]
Young-Deuk Jeon, Byeong-Lyeol Jeon, Seung-Chul Lee, Sang-Min Yoo, Seung-Hoon Lee

E7.2 A Benchmark Suite for Substrate Analysis [p. 617]
Edoardo Charbon, Luis Miguel Silveira, Paolo Miliozzi

E7.3 Embedded Tutorial : Substrate Crosstalk Analysis in Mixed Signal CMOS Integrated Circuits [p. 623]
Makoto Nagata, Atsushi Iwata

Session A8: High Speed LSI Design for Entertainment Application

Co-Chairs : Takayasu Sakurai, Univ. of Tokyo, Japan
Makoto Ikeda, Univ. of Tokyo, Japan
A8.1 Invited TAlk: Importance of CAD Tools and Methodology in High Speed CPU Design [p. 631]
Haruyuki Tago, Kazuhiro Hashimoto, Nobuyuki Ikumi, Masato Nagamatsu, Masakazu Suzuoki, Yasuyuki Yamamoto

A8.2 300MHz Design Methodology of VU for Emotion Synthesis [p. 635]
Takayuki Kamei, Hideki Takeda, Yukio Ootaguro, Takayoshi Shimazawa, Kazuhiko Tachibana, Shin'ichi Kawakami, Seiji Norimatsu, Fujio Ishihara, Toshinori Sato, Hiroaki Murakami, Nobuhiro Ide, Yukio Endo, Akira Aono, Atsushi Kunimatsu

A8.3 Repeater Insertion Method and its Application to a 300MHz 128-bit 2-way Superscalar Microprocessor [p. 641]
Norman Kojima, Yukiko Parameswar, Christian Klingner, Yukio Ohtaguro, Masataka Matsui, Shigeaki Iwasa, Tatsuo Teruyama, Takayoshi Shimazawa, Hideki Takeda, Kouji Hashizume, Haruyuki Tago, Masaaki Yamada

A8.4 Clock Design of 300MHz 128-bit 2-way Superscalar Microprocessor [p. 647]
Fujio Ishihara, Christian Klingner, Ken-ichi Agawa

Session B8: Panel Discussion

One Language or More? -How Can We Design an SoC at a System Level? - [p. 653] Organizer: Masaharu Imai, Osaka Univ., Japan
Moderator: Gary Smith, Dataquest, USA
Panelists:
Steven Schulz - Texas Instruments, Inc., USA (SLDL)
Karen Bartleson - Synopsys, Inc., USA (SystemC)
Daniel D. Gajski - Univ. of Calfornia, Irvine, USA (SpecC)
Wolfgang Rosenstiel - Univ. of Tuebingen, Germany (Java)
Peter Flake - Co-Design Automation, Inc., USA (Superlog)
Hiroto Yasuura - Kyushu Univ., Japan (C,C++)
Masaharu Imai - Osaka Univ., Japan(VHDL)

Session D8: High Performance Partitioning

Co-Chairs : Chung-Kuan Cheng, Univ. of California, San Diego, USA
Toshiyuki Shibuya, Fujitsu Laboratories, Ltd., Japan
D8.1 Circuit Partitioning with Coupled Logic Restructuring Techniques [p. 655]
Yu-Liang Wu, Xiao-Long Yuan, David Ihsin Cheng

D8.2 Improved Algorithms for Hypergraph Bipartitioning [p. 661]
Andrew E. Caldwell, Andrew B. Kahng, Igor L. Markov

D8.3 Multi-way Partitioning Using Bi-partition Heuristics [p. 667]
Maogang Wang, Sung Lim, Jason Cong, Majid Sarrafzadeh