ICCAD 2002 TABLE OF CONTENTS

Foreword
Conference Committee
Technical Program Committee
Reviewers
Awards
Keynote
Tutorial 1
Tutorial 2
Tutorial 3
Tutorial 4
Sunday Panel
Monday Panel
Call For Papers

Session 1A: Substrate Modeling

1A.1 Comprehensive Frequency-Dependent Substrate Noise Analysis Using Boundary Element Methods [p. 2]

Hongmei Li, Jorge Carballido, Harry H. Yu, Vladimir I. Okhmatovski, Elyse Rosenbaum, Andreas C. Cangellaris

1A.2 Theoretical and Practical Validation of Combined BEM/FEM Substrate Resistance Modeling [p. 10]

E. Schrik, P.M. DeWilde, N.P. van der Meijs

1A.3 Implicit Treatment of Substrate and Power-Ground Losses in Return-Limited Inductance Extraction [p. 16]

Dipak Sitaram, Yu Zheng, K. L. Shepard

Session 1B: Invited Session: Design for Low-Power

1B.1 Minimizing Power across Multiple Technology and Design Levels [p. 24]

Takayasu Sakurai

1B.2 Optimization and Control of V_DD and V_TH for Low-Power, High-Speed CMOS Design [p. 28]

Tadahiro Kuroda

1B.3 Methods for True Power Minimization [p. 35]

Robert W. Brodersen, Mark A. Horowitz, Dejan Markovic, Borivoje Nikolic, Vladimir Stojanovic

Session 1C: Routing

1C.1 A Novel Framework for Multilevel Routing Considering Routability and Performance [p. 44]

Shih-Ping Lin, Yao-Wen Chang

1C.2 An Enhanced Multilevel Routing System [p. 51]

Jason Cong, Min Xie, Yan Zhang

1C.3 Track Assignment: A Desirable Intermediate Step Between Global Routing and Detailed Routing [p. 59]

Shabbir H Batterywala, Narendra Shenoy, William Nicholls, Hai Zhou

1C.4 ECO Algorithms for Removing Overlaps Between Power Rails and Signal Wires [p. 67]

Hua Xiang, Kai-Yuan Chao, D.F. Wong

Session 1D: Advances in Testing

1D.1 Fast Seed Computation for Reseeding Shift Register in Test Pattern Compression [p. 76]

Nahmsuk Oh, Rohit Kapur, T. W. Williams

1D.2 On Undetectable Faults in Partial Scan Circuits [p. 82]

Irith Pomeranz, Sudhakar M. Reddy

1D.3 Conflict Driven Techniques for Improving Deterministic Test Pattern Generation [p. 87]

Chen Wang, Sudhakar M. Reddy, Irith Pomeranz, Xijiang Lin, Janusz Rajski

1D.4 On Theoretical and Practical Considerations of Path Selection For Delay Fault Testing [p. 94]

Jing-Jia Liou, Li-C. Wang, Tim Kwang-Ting Cheng

Session 2A: Novel Ideas in High Level Synthesis

2A.1 Interface Specification for Reconfigurable Components [p. 102]

Satnam Singh

2A.2 Interconnect-aware High-level Synthesis for Low Power [p. 110]

Lin Zhong, Niraj K. Jha

2A.3 Predictability: Definition, Analysis and Optimization [p. 118]

Ankur Srivastava, Majid Sarrafzadeh

Session 2B: Formal Techniques for Validation and Synthesis

2B.1 Simplifying Boolean Constraint Solving For Random Simulation-Vector Generation [p. 123]

Jun Yuan, Ken Albin, Adnan Aziz, Carl Pixley

2B.2 Specifying and Verifying Imprecise Sequential Datapaths by Arithmetic Transforms [p. 128]

Katarzyna Radecka, Zeljko Zilic

2B.3 Convertibility Verification and Converter Synthesis: Two Faces of the Same Coin [p. 132]

Roberto Passerone, Luca de Alfaro, Thomas A. Henzinger, Alberto L. Sangiovanni-Vincentelli

Session 2C: Embedded Tutorial: Subthreshold Leakage Modeling and Reduction Techniques

2C.1 Subthreshold Leakage Modeling and Reduction Techniques [p. 141]

James Kao, Siva Narendra, Anantha Chandrakasan,

Session 3A: Compilation Techniques for Hardware/Software Codesign

3A.1 Symbolic Pointer Analysis [p. 150]

Jianwen Zhu

3A.2 Dynamic Compilation for Energy Adaptation [p. 158]

P. Unnikrishnan, G. Chen, M. Kandemir, D. R. Mudgett

3A.3 Hardware/Software Partitioning of Software Binaries [p. 164]

Greg Stitt, Frank Vahid

Session 3B: Timing Driven Placement

3B.1 A Novel Net Weighting Algorithm for Timing-Driven Placement [p. 172]

Tim (Tianming) Kong

3B.2 Timing-Driven Placement using Design Hierarchy Guided Constraint Generation [p. 177]

Xiaojian Yang, Bo-Kyung Choi, Majid Sarrafzadeh

3B.3 Multi-objective Circuit Partitioning for Cutsize and Path-Based Delay Minimization [p. 181]

Cristinel Ababei, Navaratnasothie Selvakkumaran, Kia Bazargan, George Karypis

Session 3C: Invited Session: Emerging Technology Opportunities and Challenges

3C.1 A Hybrid ASIC and FPGA Architecture [p. 187]

Paul S. Zuchowski, Christopher B. Reynolds, Richard J. Grupp, Shelly G. Davis, Brendan Cremen, Bill Troxel

3C.2 Managing Power and Performance for System-on-Chip Designs using Voltage Islands [p. 195]

David E. Lackey, Paul S. Zuchowski, Thomas R. Bednar, Douglas W. Stout, Scott W. Gould, John M. Cohn

3C.3 Sub-90nm Technologies - Challenges and Opportunities for CAD [p. 203]

Tanay Karnik, Shekhar Borkar, Vivek De

Session 3D: Inductance Modeling I

3D.1 A Local Circuit Topology for Inductive Parasitics [p. 208]

Andrea Pacelli

3D.2 INDUCTWISE: Inductance-Wise Interconnect Simulator and Extractor [p. 215]

Tsung-Hao Chen, Clement Luk, Hyungsuk Kim, Charlie Chung-Ping Chen

3D.3 A Precorrected-FFT Method for Simulating On-chip Inductance [p. 221]

Haitian Hu, David T. Blaauw, Vladimir Zolotov, Kaushik Gala, Min Zhao, Rajendran Panda, Sachin S. Sapatnekar

Session 4A: Efficient Simulation for Analog and RF

4A.1 On the Difference between Two Widely Publicized Methods for Analyzing Oscillator Phase Behavior [p. 229]

Piet Vanassche, Georges Gielen, Willy Sansen

4A.2 A Behavioral Simulation Tool for Continuous-Time Delta-Sigma Modulators [p. 234]

Kenneth Francken, Martin Vogels, Ewout Martens, Georges Gielen

4A.3 Making Fourier-Envelope Simulation Robust [p. 240]

Jaijeet Roychowdhury

Session 4B: Interconnect Optimization

4B.1 Optimal Buffered Routing Path Constructions for Single and Multiple Clock Domain Systems [p. 247]

Soha Hassoun, Charles J. Alpert, Meera Thiagarajan

4B.2 Shaping Interconnect for Uniform Current Density [p. 254]

Muzhou Shao, D.F. Wong, Youxin Gao, Li-Pen Yuan, Huijing Cao

4B.3 Non-tree Routing for Reliability and Yield Improvement [p. 260]

Andrew B. Kahng, Bao Liu, Ion I. Mandoiu

Session 4C: Chip-Level Communication Structures

4C.1 Concurrent Flip-Flop and Repeater Insertion for High Performance Integrated Circuits [p. 268]

Pasquale Cocchini

4C.2 Throughput-Driven IC Communication Fabric Synthesis [p. 274]

Tao Lin, Lawrence T. Pileggi

4C.3 Repeater Insertion and Wire Sizing Optimization for Throughput-Centric VLSI Global Interconnects [p. 280]

Harshit Shah, Pun Shiu, Brian Bell, Mamie Aldredge, Namarata Sopory, Jeff Davis

Session 4D: New DFT Techniques and Methodologies

4D.1 Test-Model based Hierarchical DFT Synthesis [p. 286]

Sanjay Ramnath, Frederic Neuveux, Mokhtar Hirech, Felix Ng

4D.2 Characteristic Faults and Spectral Information for Logic BIST [p. 294]

Xiaoding Chen, Michael S. Hsiao

4D.3 A Novel Scan Architecture for Power-Efficient, Rapid Test [p. 299]

Ozgur Sinanoglu, Alex Orailoglu

Session 5A: System-Level Analog Design

5A.1 Optimization of a Fully Integrated Low Power CMOS GPS Receiver [p. 305]

Peter Vancorenland, Philippe Coppejans, Wouter De Cock, Paul Leroux, Michiel Steyaert

5A.2 Analysis and Optimization of Substrate Noise Coupling in Single-Chip RF Transceiver Design [p. 309]

Adil Koukab, Kaustav Banerjee, Michel Declercq

5A.3 Design of Pipeline Analog-to-Digital Converters via Geometric Programming [p. 317]

Maria del Mar Hershenson

Session 5B: Inductance Modeling II

5B.1 Proximity Templates for Modeling of Skin and Proximity Effects on Packages and High Frequency Interconnect [p. 326]

Luca Daniel, Alberto Sangiovanni-Vincentelli, Jacob White

5B.2 Transmission Line Design of Clock Trees [p. 334]

Rafael Escovar, Robert Suaya

5B.3 On-Chip Interconnect Modeling by Wire Duplication [p. 341]

Guoan Zhong, Cheng-Kok Koh, and Kaushik Roy

Session 5C: Emerging Technologies: Circuits and Systems

5C.1 A Case for CMOS/nano Co-design [p. 348]

Matthew M. Ziegler, Mircea R. Stan

5C.2 Reversible Logic Circuit Synthesis [p. 353]

Vivek V. Shende, Aditya K. Prasad, Igor L. Markov, John P. Hayes

5C.3 Extraction and LVS for Mixed-domain Integrated MEMS Layouts [p. 361]

Bikram Baidya, Tamal Mukherjee

5C.4 Schematic-Based Lumped Parameterized Behavioral Modeling for Suspended MEMS [p. 367]

Qi Jing, Tamal Mukherjee, Gary K. Fedder

Session 5D: Low Power and Transistor Level Optimization

5D.1 Standby Power Optimization via Transistor Sizing and Dual Threshold Voltage Assignment [p. 375]

Mahesh Ketkar, Sachin S. Sapatnekar

5D.2 Power Efficiency of Voltage Scaling in Multiple Clock, Multiple Voltage Cores [p. 379]

Anoop Iyer, Diana Marculescu

5D.3 Optimized Power-Delay Curve Generation for Standard Cell ICs [p. 387]

Miodrag Vujkovic, Carl Sechen

5D.4 Gate Sizing Using Lagrangian Relaxation Combined with a Fast Gradient-Based Pre-Processing Step [p. 395]

Hiran Tennakoon, Carl Sechen

Session 6A: Statistical Techniques for Power and Timing Estimation

6A.1 A Markov Chain Sequence Generator for Power Macromodeling [p. 404]

Xun Liu, Marios C. Papaefthymiou

6A.2 Circuit Power Estimation Using Pattern Recognition Techniques [p. 412]

Lipeng Cao

6A.3 Estimation of Signal Arrival Times in the presence of Delay Noise [p. 418]

Sarvesh Bhardwaj, Sarma B.K. Vrudhula, David Blaauw

Session 6B: Embedded Tutorial: CAD Computation for Manufacturability: Can We Save VLSI Technology from Itself ?

6B.1 CAD Computation for Manufacturability: Can We Save VLSI Technology from Itself ? [p. 424]

Mark Lavin, Lars Liebman

Session 6C: Embedded Tutorial: Molecular Electronics: Devices, Systems and Tools for Gigagate, Gigabit Chips

6C.1 Molecular Electronics: Devices, Systems and Tools for Gigagate, Gigabit Chips [p. 433]

Michael Butts, AndrÚ DeHon, Seth Copen Goldstein

Session 7A: Satisfiability Checking

7A.1 Conflict Driven Learning in a Quantified Boolean Satisfiability Solver [p. 442]

Lintao Zhang, Sharad Malik

7A.2 Generic ILP versus Specialized 0-1 ILP: An Update [p. 450]

Fadi A. Aloul, Arathi Ramani, Igor L. Markov, Karem A. Sakallah

7A.3 Binary Time-Frame Expansion [p. 458]

Farzan Fallah

Session 7B: Emerging Technologies: Device Modeling and Simulation

7B.1 Fast Methods for Simulation of Biomolecule Electrostatics [p. 466]

Shihhsien S. Kuo, Michael D. Altman, Jaydeep P. Bardhan, Bruce Tidor, Jacob K. White

7B.2 Efficient Mixed-Domain Analysis of Electrostatic MEMS [p. 474]

Gang Li, N. R. Aluru

7B.3 FastMag: A 3-D Magnetostatic Inductance Extraction Program for Structures with Permeable Materials [p. 478]

Yehia Massoud, Jacob White

Session 7C: Circuit-Level Analog CAD

7C.1 Analog Circuit Sizing Based on Formal Methods Using Affine Arithmetic [p. 486]

Andreas Lemke, Lars Hedrich, Erich Barke

7C.2 SiSMA: A Statistical Simulator for Mismatch Analysis of MOS ICs [p. 490]

G. Biagetti, S. Orcioni, L. Signoracci, C. Turchetti, P. Crippa, M. Alessandrini

7C.3 Efficient Solution Space Exploration Based on Segment Trees in Analog Placement with Symmetry Constraints [p. 497]

Florin Balasa, Sarat C Maruvada, Karthik Krishnamoorthy

Session 7D: Physical Effects in Deep Sub Micron Technology

7D.1 Post Global Routing RLC Crosstalk Budgeting [p. 504]

Jinjun Xiong, Jun Chen, James Ma Lei He,

7D.2 A Technology-independent CAD Tool For ESD Protection Device Extraction - ESDExtractor [p. 510]

R.Y. Zhan, H.G. Feng, Q. Wu, G. Chen, X.K. Guan, Albert Z. Wang

7D.3 On Mask Layout Partitioning for Electron Projection Lithography [p. 514]

Ruiqi Tian, Ronggang Yu, Xiaoping Tang, D.F. Wong

Session 8A: Verification at the Switch, Gate, and RT Levels

8A.1 High Capacity and Automatic Functional Extraction Tool for Industrial VLSI Circuit Designs [p. 520]

Sasha Novakovsky, Shy Shyman, Ziyad Hanna

8A.2 Combinational Equivalence Checking through Function Transformation [p. 526]

Hee Hwan Kwak, In-Ho Moon, James H. Kukula, Thomas R. Shiple

8A.3 GSTE Through a Case Study [p. 534]

Jin Yang, Amit Goel

Session 8B: New Trends in Logic Synthesis

8B.1 Whirlpool PLAs: A Regular Logic Structure and Their Synthesis [p. 543]

Fan Mo, Robert K. Brayton

8B.2 Metrics for Structural Logic Synthesis [p. 551]

Prabhakar Kudva, Andrew Sullivan, William Dougherty

8B.3 Simplification of Non-Deterministic Multi-Valued Networks [p. 557]

Alan Mishchenko, Robert Brayton

Session 8C: Memory Issues in High-Level Synthesis

8C.1 High-Level Synthesis of Distributed Logic-Memory Architectures [p. 564]

Chao Huang, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha

8C.2 An Energy-conscious Algorithm for Memory Port Allocation [p. 572]

Preeti Ranjan Panda, Lakshmikantam Chitturi

8C.3 Energy Efficient Address Assignment Through Minimized Memory Row Switching [p. 577]

Sambuddhi Hettiaratchi, Peter Y.K. Cheung, Thomas J.W. Clarke

Session 8D: Noise Effects on Circuit Operation

8D.1 Refining Switching Window by Time Slots for Crosstalk Noise Calculation [p. 583]

Pinhong Chen, Yuji Kukimoto, Kurt Keutzer

8D.2 Noise Propagation and Failure Criteria for VLSI Designs [p. 587]

V. Zolotov, D. Blaauw, S. Sirichotiyakul, M. Becer, C. Oh, R. Panda, A. Grinshpon, R. Levy

8D.3 Efficient Crosstalk Noise Modeling Using Aggressor and Tree Reductions [p. 595]

Li Ding, David Blaauw, Pinaki Mazumder

Session 9A: Low Level Aware Behavioral Synthesis

9A.1 Bit-level Scheduling of Heterogeneous Behavioural Specifications [p. 602]

M.C. Molina, J.M. Mendâas, R. Hermida

9A.2 Coupling-Aware High-level Interconnect Synthesis for Low Power [p. 609]

Chun-Gi Lyuh, Taewhan Kim, Ki-Wook Kim

9A.3 Layout-Driven Resource Sharing in High-Level Synthesis [p. 614]

Junhyung Um, Jaehoon Kim, Taewhan Kim

Session 9B: Advances in Timing Analysis Accuracy

9B.1 A Delay Metric for RC Circuits based on the Weibull Distribution [p. 620]

Frank Liu, Chandramouli Kashyap, Charles J. Alpert

9B.2 WTA - Waveform-Based Timing Analysis for Deep Submicron Circuits [p. 625]

Larry McMurchie, Carl Sechen

9B.3 General Framework for Removal of Clock Network Pessimism [p. 632]

Jindrich Zejda, Paul Frain

Session 9C: Customization of Embedded System Architectures

9C.1 Synthesis of Custom Processors based on Extensible Platforms [p. 641]

Fei Sun, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha

9C.2 Efficient Instruction Encoding for Automatic Instruction Set Design of Configurable ASIPs [p. 649]

Jong-eun Lee, Kiyoung Choi, Nikil Dutt

9C.3 Synthesis of Customized Loop Caches for Core-Based Embedded Systems [p. 655]

Susan Cotterell, Frank Vahid

9C.4 A Hierarchical Modeling Framework for On-Chip Communication Architectures [p. 663]

Xinping Zhu, Sharad Malik

Session 9D: Advances in Combinational Synthesis

9D.1 A New Enhanced SPFD Rewiring Algorithm [p. 672]

Jason Cong, Joey Y. Lin, Wangning Long

9D.2 Topologically Constrained Logic Synthesis [p. 679]

Subarnarekha Sinha, Alan Mishchenko, Robert K Brayton

9D.3 Resynthesis of Multi-Level Circuits Under Tight Constraints Using Symbolic Optimization [p. 687]

Victor N Kravets, Karem A Sakallah

9D.4 Folding of Logic Functions and Its Application to Look Up Table Compaction [p. 694]

Shinji Kimura, Takashi Horiyama, Masaki Nakanishi, Hirotsugu Kajihara

Session 10A: System-Level Performance and Power Modeling and Optimization

10A.1 Schedulability Analysis of Multiprocessor Real-Time Applications with Stochastic Task Execution Times [p. 699]

Sorin Manolache, Petru Eles, Zebo Peng

10A.2 Battery-Aware Power Management Based on Markovian Decision Processes [p. 707]

Peng Rong, Massoud Pedram

10A.3 Leakage Power Modeling and Reduction with Data Retention [p. 714]

Weiping Liao, Joseph M. Basile, Lei He

Session 10B: Advances in Dynamic Voltage Scheduling

10B.1 Combined Dynamic Voltage Scaling and Adaptive Body Biasing for Lower Power Microprocessors under Dynamic Workloads [p. 721]

Steven M. Martin, Krisztian Flautner, Trevor Mudge, David Blaauw

10B.2 A Realistic Variable Voltage Scheduling Model for Real-Time Applications [p. 726]

Bren Mochocki, Xiaobo Sharon Hu, Gang Quan

10B.3 Frame-Based Dynamic Voltage and Frequency Scaling for a MPEG Decoder [p. 732]

Kihwan Choi, Karthik Dantu, Wei-Chung Cheng, Massoud Pedram

Session 10C: Techniques in Placement

10C.1 Congestion Minimization During Placement Without Estimation [p. 739]

Bo Hu, Malgorzata Marek-Sadowska

10C.2 Free Space Management for Cut-Based Placement [p. 746]

Charles J. Alpert, Gi-Joon Nam, Paul G. Villarrubia

10C.3 Incremental Placement for Layout-Driven Optimizations on FPGAs [p. 752]

Deshanand P. Singh, Stephen D. Brown

Session 10D: Model Order Reduction

10D.1 Robust and Passive Model Order Reduction for Circuits Containing Susceptance Elements [p. 761]

Hui Zheng, Lawrence T. Pileggi

10D.2 Efficient Model Order Reduction via Multi-Node Moment Matching [p. 767]

Yehea I. Ismail

10D.3 Optimization Based Passive Constrained Fitting [p. 775]

Carlos P. Coelho, Joel R. Phillips, L. Miguel Silveira

Session 11A: Embedded Tutorial: SAT & ATPG: Boolean Engines for Formal Hardware Verification

11A.1 SAT and ATPG: Boolean Engines for Formal Hardware Verification [p. 782]

Armin Biere, Wolfgang Kunz

11A.2 ATPG-based Logic Synthesis: An Overview [p. 786]

Chih-Wei Jim Chang, Malgorzata Marek-Sadowska

Session 11B: Embedded Tutorial: The A to Z of SoCs

11B.1 The A to Z of SoCs [p. 791]

Reinaldo A. Bergamaschi, John Cohn