SIGDA Super Compendium, ISPD 2000, Table of Contents

<BODY> <H3><A HREF="../../../../../main_ss.htm">Main Page</A></BR> ISPD 2000 : [ <A HREF="ispdabs.htm">Abstracts</A> ] [ <A HREF="ispdsess.htm">Session Index</A> ] [ <A HREF="ispdai.htm">Author Index</A> ]</H3> <HR> <H2>ISPD 2000 Table of Contents</H2> <B> Sessions: [<A HREF="#sess1">1</A>] [<A HREF="#sess2">2</A>] [<A HREF="#panel1">Panel1</A>] [<A HREF="#sess3">3</A>] [<A HREF="#sess4">4</A>] [<A HREF="#sess5">5</A>] [<A HREF="#sess6">6</A>] [<A HREF="#panel2">Panel2</A>] [<A HREF="#sess7">7</A>] [<A HREF="#sess8">8</A>] [<A HREF="#sess9">9</A>] [<A HREF="#pandis">Panel Discussion</A>] <P> <A HREF="../../pdffiles/foreword.pdf">Foreword [p. iii]</A><BR> Committees [p. ix]</A><BR> Welcome and Keynote [p. 1]</A><BR> Chair: D. Hill (Synopsys)<BR> Keynote Speaker: Aart de Geus (Synopsys) </B> </DL> <HR> <H2>Session 1: <A HREF="ispdabs.htm#sess1" NAME="sess1"> Technology Trends [p. 2] </A></H2> <I>Chair: S. S. Sapatnekar (Univ. of Minnesota)</I> <DL> <DT> Circuit Design Challenges Beyond 0.18 Micron <DD><I>S. Borkar (Intel)</I><P> <DT> How Thin is the ICE? How Variability and Yield Drive Physical Design <DD><I>S. Nassif (IBM)</I><P> <DT> Interconnect Design and Analysis Issues in High Performance ICs <DD><I>A.Devgan (IBM)</I><P> </DL> <HR> <H2>Session 2: <A HREF="ispdabs.htm#sess2" NAME="sess2"> Developments in Routing [p. 3] </A></H2> <I>Chair: P. Groeneveld (Magma)</I> <DL> <DT> <A HREF="ispdabs.htm#2_1"><IMG SRC="../../../../../icons/absicon.gif"></A> <A HREF="../../pdffiles/2_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A> Requirements for Models of Achievable Routing [p. 4] <DD><I>A. B. Kahng, S. Mantik, D. Stroobandt (UCLA)</I><P> <DT> <A HREF="ispdabs.htm#2_2"><IMG SRC="../../../../../icons/absicon.gif"></A> <A HREF="../../pdffiles/2_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A> DUNE: A Multi-Layer Gridless Routing System with Wire Planning [p. 12] <DD><I>J. Cong, J. Fang, K.-Y. Khoo (UCLA)</I><P> <DT> <A HREF="ispdabs.htm#2_3"><IMG SRC="../../../../../icons/absicon.gif"></A> <A HREF="../../pdffiles/2_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A> Provably Good Global Routing by a New Approximation Algorithm for Multicommodity Flow [p. 19] <DD><I>C. Albrecht (Univ. of Bonn)</I><P> <DT> <A HREF="ispdabs.htm#2_4"><IMG SRC="../../../../../icons/absicon.gif"></A> <A HREF="../../pdffiles/2_4.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A> Exact Switchbox Routing with Search Space Reduction [p. 26] <DD><I>F. Schmiedle, D. Unruh, B. Becker (Albert-Ludwigs Univ.)</I><P> <DT> <A HREF="ispdabs.htm#2_5"><IMG SRC="../../../../../icons/absicon.gif"></A> <A HREF="../../pdffiles/2_5.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A> Zero-Skew Clock Tree Construction by Simultaneous Routing, Wire Sizing and Buffer Insertion [p. 33] <DD><I>I-M. Liu (Univ. of Texas-Austin), T.-L. Chou (Intel), A. Aziz and D. F. Wong (Univ. of Texas-Austin)</I><P> </DL> <HR> <H2>Panel 1: <A HREF="ispdabs.htm#panel1" NAME="panel1"> The Bottom-10 Problems in EDA [p. 39] </A></H2> <I> Organizer and Chair: N. Sherwani (Intel) </I> </DL> <HR> <H2>Session 3: <A HREF="ispdabs.htm#sess3" NAME="sess3"> Issues in Interconnect [p. 40] </A></H2> <I> Chair: R. Otten (Delft Univ.) </I> <DL> <DT> <A HREF="ispdabs.htm#3_1"><IMG SRC="../../../../../icons/absicon.gif"></A> <A HREF="../../pdffiles/3_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A> Pseudo Pin Assignment with Crosstalk Noise Control [p. 41] <DD><I>C.-C. Chang, J. Cong (UCLA)</I><P> <DT> <A HREF="ispdabs.htm#3_2"><IMG SRC="../../../../../icons/absicon.gif"></A> <A HREF="../../pdffiles/3_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A> Aggressor Alignment for Worst-Case Coupling Noise [p. 48] <DD><I>L.H. Chen, M. Marek-Sadowska (UCSB)</I><P> <DT> <A HREF="ispdabs.htm#3_3"><IMG SRC="../../../../../icons/absicon.gif"></A> <A HREF="../../pdffiles/3_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A> Simultaneous Shield Insertion and Net Ordering for Capacitive and Inductive Coupling Minimization [p. 55] <DD><I>L. He, K. M. Lepak (Univ. of Wisconsin)</I><P> <DT> <A HREF="ispdabs.htm#3_4"><IMG SRC="../../../../../icons/absicon.gif"></A> <A HREF="../../pdffiles/3_4.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A> Wire Packing: A Strong Formulation of Crosstalk-Aware Chip-Level Track/Layer Assignment with an Efficient Integer Programming Solution [p. 61] <DD><I>R. Kay (Intel), R. A. Rutenbar (CMU)</I><P> <DT> <A HREF="ispdabs.htm#3_5"><IMG SRC="../../../../../icons/absicon.gif"></A> <A HREF="../../pdffiles/3_5.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A> A Two Moment RC Delay Metric for Performance Optimization [p. 69] <DD><I>C. J. Alpert, A. Devgan, C. Kashyap (IBM)</I><P> </DL> <HR> <H2>Session 4: <A HREF="ispdabs.htm#sess4" NAME="sess4"> Challenges for EDA - Analog and Incremental [p. 75] </A></H2> <I>Chair: M. Pedram (USC)</I> <DL> <DT> <A HREF="ispdabs.htm#4_1"><IMG SRC="../../../../../icons/absicon.gif"></A> <A HREF="../../pdffiles/4_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A> Layout Tools for Analog ICs and Mixed-Signal SoCs: A Survey [p. 76] <DD><I>R. Rutenbar (CMU), J. M. Cohn (IBM)</I><P> <DT> <A HREF="ispdabs.htm#4_2"><IMG SRC="../../../../../icons/absicon.gif"></A> <A HREF="../../pdffiles/4_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A> Incremental Physical Design [p. 84] <DD><I>J. Cong, (UCLA), M. Sarrafzadeh (Northwestern U)</I><P> </DL> <HR> <H2>Session 5: <A HREF="ispdabs.htm#sess5" NAME="sess5"> Expanding the Realm of Physical Design [p. 93] </A></H2> <I>Chair: R. Rutenbar (CMU)</I> <DL> <DT> <A HREF="ispdabs.htm#5_1"><IMG SRC="../../../../../icons/absicon.gif"></A> <A HREF="../../pdffiles/5_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A> Itanium<SUP>TM</SUP> Processor Clock Design [p. 94] <DD><I>U. Desai, S. Tam, R. Kim, J. Zhang, S. Rusu (Intel)</I><P> <DT> <A HREF="ispdabs.htm#5_2"><IMG SRC="../../../../../icons/absicon.gif"></A> <A HREF="../../pdffiles/5_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A> Methodology for Repeater Insertion Management in the RTL, Layout, Floorplan and Fullchip Timing Databases of the Itanium<SUP>TM</SUP> Microprocessor [p. 99] <DD><I>R. McInerney, K. Leeper, T. Hill, H. Chan, B. Basaran, L. McQuiddy (Intel)</I><P> <DT> <A HREF="ispdabs.htm#5_3"><IMG SRC="../../../../../icons/absicon.gif"></A> <A HREF="../../pdffiles/5_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A> Buffer Minimization in Pass Transistor Logic [p. 105] <DD><I>H. Zhou (Synopsys), A. Aziz (UT-Austin)</I><P> <DT> <A HREF="ispdabs.htm#5_4"><IMG SRC="../../../../../icons/absicon.gif"></A> <A HREF="../../pdffiles/5_4.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A> A Performance Optimization Method by Gate Sizing using Statistical Static Timing Analysis [p. 111] <DD><I>M. Hashimoto, H. Onodera (Kyoto U.)</I><P> <DT> <A HREF="ispdabs.htm#5_5"><IMG SRC="../../../../../icons/absicon.gif"></A> <A HREF="../../pdffiles/5_5.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A> Simulating Frequency-Dependent Current Distribution for Inductance Modeling of On-Chip Copper Interconnects [p. 117] <DD><I>L.-F. Chang, K.-J. Chang, R. Mathews (Frequency Technology)</I><P> </DL> <HR> <H2>Session 6: <A HREF="ispdabs.htm#sess6" NAME="sess6"> Poster Papers [p. 121] </A></H2> <I> Chair: J. Lillis (U. Illinois-Chicago) </I> <DL> <DT> <A HREF="ispdabs.htm#6_1"><IMG SRC="../../../../../icons/absicon.gif"></A> <A HREF="../../pdffiles/6_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A> Datapath Routing Based on a Decongestion Metric [p. 122] <DD><I>S. Raman, S. S. Sapatnekar (U. Minnesota), C. J. Alpert (IBM)</I><P> <DT> <A HREF="ispdabs.htm#6_2"><IMG SRC="../../../../../icons/absicon.gif"></A> <A HREF="../../pdffiles/6_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A> Optimal Reliable Crosstalk Driven Interconnect Optimization [p. 128] <DD><I>I. H.-R. Jiang, S.-R. Pan, Y.-W. Chang, J.-Y. Jou (National Chiao-Tung U.)</I><P> <DT> <A HREF="ispdabs.htm#6_3"><IMG SRC="../../../../../icons/absicon.gif"></A> <A HREF="../../pdffiles/6_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A> A Hybrid Dynamic / Quadratic Programming Algorithm for Interconnect Tree Optimization [p. 134] <DD><I>Y.-Y. Mo, C. C. N. Chu (Iowa State U.)</I><P> <DT> <A HREF="ispdabs.htm#6_4"><IMG SRC="../../../../../icons/absicon.gif"></A> <A HREF="../../pdffiles/6_4.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A> Critical Area Computation for Missing Material Defects in VLSI Circuits [p. 140] <DD><I>E. Papadopoulou (IBM)</I><P> <DT> <A HREF="ispdabs.htm#6_5"><IMG SRC="../../../../../icons/absicon.gif"></A> <A HREF="../../pdffiles/6_5.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A> Multi-Center Congestion Estimation and Minimization During Placement [p. 147] <DD><I>M. Wang, X. Yang, K. Eguro, M. Sarrafzadeh (Northwestern U.)</I><P> <DT> <A HREF="ispdabs.htm#6_6"><IMG SRC="../../../../../icons/absicon.gif"></A> <A HREF="../../pdffiles/6_6.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A> A Snap-On Placement Tool [p. 153] <DD><I>X. Yang, M. Wang, K. Eguro, M. Sarrafzadeh (Northwestern U.)</I><P> <DT> <A HREF="ispdabs.htm#6_7"><IMG SRC="../../../../../icons/absicon.gif"></A> <A HREF="../../pdffiles/6_7.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A> A Practical Clock Tree Synthesis for Semi-Synchronous Circuit [p. 159] <DD><I>M. Toyonaga, K. Kurokawa, T. Yasui (Matsushita), A. Takahashi (Tokyo Institute) </I><P> </DL> <HR> <H2>Panel 2: <A HREF="ispdabs.htm#panel2" NAME="panel2"> EDA and the Internet [p. 165] </A></H2> <I> Organizer and Chair: D. Hill (Synopsys)<BR> Panelists: Mark Gilbreath (Toolwire), Wayne Heideman (Synopsys),<BR> George Janac (InTime), and Adriaan Ligtenberg (Cadence) </I> </DL> <HR> <H2>Session 7: <A HREF="ispdabs.htm#sess7" NAME="sess7"> Floorplanning and Partitioning [p. 167] </A></H2> <I> Chair: C. J. Alpert (IBM) </I> <DL> <DT> <A HREF="ispdabs.htm#7_1"><IMG SRC="../../../../../icons/absicon.gif"></A> <A HREF="../../pdffiles/7_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A> An Enhanced Perturbing Algorithm for Floorplan Design Using the O-tree Representation [p. 168] <DD><I>Y. Pang, C.-K. Cheng (UCSD), T. Yoshimura (NEC)</I><P> <DT> <A HREF="ispdabs.htm#7_2"><IMG SRC="../../../../../icons/absicon.gif"></A> <A HREF="../../pdffiles/7_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A> Floorplan Area Minimization using Lagrangian Relaxation [p. 174] <DD><I>F. Y. Young (Chinese U. of Hong Kong), C. C. N. Chu (Iowa State U.), W. S. Luk, Y. C Wong (Synopsys)</I><P> <DT> <A HREF="ispdabs.htm#7_3"><IMG SRC="../../../../../icons/absicon.gif"></A> <A HREF="../../pdffiles/7_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A> Planning Buffer Locations by Network Flows [p. 180] <DD><I>X. Tang, D. F. Wong (UT-Austin)</I><P> <DT> <A HREF="ispdabs.htm#7_4"><IMG SRC="../../../../../icons/absicon.gif"></A> <A HREF="../../pdffiles/7_4.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A> Routability-Driven Repeater Block Planning for Interconnect-Centric Floorplanning [p. 186] <DD><I>P. Sarkar, V. Sundararaman, C.-K. Koh (Purdue U.)</I><P> <DT> <A HREF="ispdabs.htm#7_5"><IMG SRC="../../../../../icons/absicon.gif"></A> <A HREF="../../pdffiles/7_5.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A> Multilevel Cooperative Search: Application to the Circuit / Hypergraph Partitioning Problem [p. 192] <DD><I>M. Ouyang (U. Nebraska-Lincoln), M. Toulouse (U. Manitoba), K. Thulasiraman (U. Oklahoma), F. Glover (U. Colorado), J. Deogun (U. Nebraska-Lincoln)</I><P> </DL> <HR> <H2>Session 8: <A HREF="ispdabs.htm#sess8" NAME="sess8"> Complexity and Overlapping Design Space [p. 199] </A></H2> <I> Chair: J. Jess (Eindhoven) </I> <DL> <DT> Coping with Physical Design Problem Sizes in the Post-Moore's Law Era <DD><I>T. Gao, P. Parakh (Monterey)</I><P> <DT> Physopt <DD><I>S. Krishnamoorty, S. Thakur (Synopsys)</I><P> </DL> <HR> <H2>Session 9: <A HREF="ispdabs.htm#sess9" NAME="sess9"> Floorplanning: Use and Abuse [p. 200] </A></H2> <I>Organizer and Chair: P. Groeneveld (Magma)</I> <DL> <DT> <A HREF="ispdabs.htm#9_1"><IMG SRC="../../../../../icons/absicon.gif"></A> <A HREF="../../pdffiles/9_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A> What is a Floorplan? [p. 201] <DD><I>R. Otten (TU-Delft)</I><P> <DT> <A HREF="ispdabs.htm#9_2"><IMG SRC="../../../../../icons/absicon.gif"></A> <A HREF="../../pdffiles/9_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A> Classical Floorplanning Harmful? [p. 207] <DD><I>A. B. Kahng (UCLA)</I><P> </DL> <HR> <H2>Panel Discussion : <A NAME="pandis"> The Right Floorplanning Formulations for Future Chip Implementation Methodologies [p. 214] </A></H2> <I> Moderator: P. Groeneveld (Magma)<BR> Panelists: Jacob Greidinger (Aristo Design), George Janac (InTime Software), Wilm Donath (IBM) </I> </DL>