ISPD 2000 Table of Contents

Foreword [p. iii]
Committees [p. ix]
Welcome and Keynote [p. 1]
Chair: D. Hill (Synopsys)
Keynote Speaker: Aart de Geus (Synopsys)

Session 1: Technology Trends [p. 2]

Circuit Design Challenges Beyond 0.18 Micron

S. Borkar (Intel)

How Thin is the ICE? How Variability and Yield Drive Physical Design

S. Nassif (IBM)

Interconnect Design and Analysis Issues in High Performance ICs

A.Devgan (IBM)

Session 2: Developments in Routing [p. 3]

Requirements for Models of Achievable Routing [p. 4]

A. B. Kahng, S. Mantik, D. Stroobandt (UCLA)

DUNE: A Multi-Layer Gridless Routing System with Wire Planning [p. 12]

J. Cong, J. Fang, K.-Y. Khoo (UCLA)

Provably Good Global Routing by a New Approximation Algorithm for Multicommodity Flow [p. 19]

C. Albrecht (Univ. of Bonn)

Exact Switchbox Routing with Search Space Reduction [p. 26]

F. Schmiedle, D. Unruh, B. Becker (Albert-Ludwigs Univ.)

Zero-Skew Clock Tree Construction by Simultaneous Routing, Wire Sizing and Buffer Insertion [p. 33]

I-M. Liu (Univ. of Texas-Austin), T.-L. Chou (Intel), A. Aziz and D. F. Wong (Univ. of Texas-Austin)

Panel 1: The Bottom-10 Problems in EDA [p. 39]

Session 3: Issues in Interconnect [p. 40]

Pseudo Pin Assignment with Crosstalk Noise Control [p. 41]

C.-C. Chang, J. Cong (UCLA)

Aggressor Alignment for Worst-Case Coupling Noise [p. 48]

L.H. Chen, M. Marek-Sadowska (UCSB)

Simultaneous Shield Insertion and Net Ordering for Capacitive and Inductive Coupling Minimization [p. 55]

L. He, K. M. Lepak (Univ. of Wisconsin)

Wire Packing: A Strong Formulation of Crosstalk-Aware Chip-Level Track/Layer Assignment with an Efficient Integer Programming Solution [p. 61]

R. Kay (Intel), R. A. Rutenbar (CMU)

A Two Moment RC Delay Metric for Performance Optimization [p. 69]

C. J. Alpert, A. Devgan, C. Kashyap (IBM)

Session 4: Challenges for EDA - Analog and Incremental [p. 75]

Layout Tools for Analog ICs and Mixed-Signal SoCs: A Survey [p. 76]

R. Rutenbar (CMU), J. M. Cohn (IBM)

Incremental Physical Design [p. 84]

J. Cong, (UCLA), M. Sarrafzadeh (Northwestern U)

Session 5: Expanding the Realm of Physical Design [p. 93]

Itanium^TM Processor Clock Design [p. 94]

U. Desai, S. Tam, R. Kim, J. Zhang, S. Rusu (Intel)

Methodology for Repeater Insertion Management in the RTL, Layout, Floorplan and Fullchip Timing Databases of the Itanium^TM Microprocessor [p. 99]

R. McInerney, K. Leeper, T. Hill, H. Chan, B. Basaran, L. McQuiddy (Intel)

Buffer Minimization in Pass Transistor Logic [p. 105]

H. Zhou (Synopsys), A. Aziz (UT-Austin)

A Performance Optimization Method by Gate Sizing using Statistical Static Timing Analysis [p. 111]

M. Hashimoto, H. Onodera (Kyoto U.)

Simulating Frequency-Dependent Current Distribution for Inductance Modeling of On-Chip Copper Interconnects [p. 117]

L.-F. Chang, K.-J. Chang, R. Mathews (Frequency Technology)

Session 6: Poster Papers [p. 121]

Datapath Routing Based on a Decongestion Metric [p. 122]

S. Raman, S. S. Sapatnekar (U. Minnesota), C. J. Alpert (IBM)

Optimal Reliable Crosstalk Driven Interconnect Optimization [p. 128]

I. H.-R. Jiang, S.-R. Pan, Y.-W. Chang, J.-Y. Jou (National Chiao-Tung U.)

A Hybrid Dynamic / Quadratic Programming Algorithm for Interconnect Tree Optimization [p. 134]

Y.-Y. Mo, C. C. N. Chu (Iowa State U.)

Critical Area Computation for Missing Material Defects in VLSI Circuits [p. 140]

E. Papadopoulou (IBM)

Multi-Center Congestion Estimation and Minimization During Placement [p. 147]

M. Wang, X. Yang, K. Eguro, M. Sarrafzadeh (Northwestern U.)

A Snap-On Placement Tool [p. 153]

X. Yang, M. Wang, K. Eguro, M. Sarrafzadeh (Northwestern U.)

A Practical Clock Tree Synthesis for Semi-Synchronous Circuit [p. 159]

M. Toyonaga, K. Kurokawa, T. Yasui (Matsushita), A. Takahashi (Tokyo Institute)

Panel 2: EDA and the Internet [p. 165]

Session 7: Floorplanning and Partitioning [p. 167]

An Enhanced Perturbing Algorithm for Floorplan Design Using the O-tree Representation [p. 168]

Y. Pang, C.-K. Cheng (UCSD), T. Yoshimura (NEC)

Floorplan Area Minimization using Lagrangian Relaxation [p. 174]

F. Y. Young (Chinese U. of Hong Kong), C. C. N. Chu (Iowa State U.), W. S. Luk, Y. C Wong (Synopsys)

Planning Buffer Locations by Network Flows [p. 180]

X. Tang, D. F. Wong (UT-Austin)

Routability-Driven Repeater Block Planning for Interconnect-Centric Floorplanning [p. 186]

P. Sarkar, V. Sundararaman, C.-K. Koh (Purdue U.)

Multilevel Cooperative Search: Application to the Circuit / Hypergraph Partitioning Problem [p. 192]

M. Ouyang (U. Nebraska-Lincoln), M. Toulouse (U. Manitoba), K. Thulasiraman (U. Oklahoma), F. Glover (U. Colorado), J. Deogun (U. Nebraska-Lincoln)

Session 8: Complexity and Overlapping Design Space [p. 199]

Coping with Physical Design Problem Sizes in the Post-Moore's Law Era

T. Gao, P. Parakh (Monterey)

Physopt

S. Krishnamoorty, S. Thakur (Synopsys)

Session 9: Floorplanning: Use and Abuse [p. 200]

What is a Floorplan? [p. 201]

R. Otten (TU-Delft)

Classical Floorplanning Harmful? [p. 207]

A. B. Kahng (UCLA)

Panel Discussion : The Right Floorplanning Formulations for Future Chip Implementation Methodologies [p. 214]