login(); } if (!empty($_GET['logout'])) { $auth_object->logout(); } // Next, we can check whether or not you're logged // in by checking the $auth->isLoggedIn() method if ($auth_object->isLoggedIn()) { // do stuff, you can check the ucinetid of // the person by looking at $auth->ucinetid if ($auth_object->allowedAccess($auth_object->EECS31L_ARRAY) or $auth_object->allowedAccess($auth_object->EECS31L_STUDENT_ARRAY)) { // don't need to do anything } else { // logged in but not valid... // don't need to do anything - allow access for all } } else { // you're not logged in, sorry... // try to log user in // logged in but not valid... // don't need to do anything - allow access for all } // Also, you can look at all the values within // the auth object by using the code: // print "
";
    // print_r ($auth_object);
    // print "
"; // As always, feel free to contact me with questions. // Eric Carter, ecarter@uci.edu ?> Lab 1 :: Labs :: EECS 31L / CSE 31L :: Daniel D. Gajski's Web Site

EECS 31L/CSE 31L: Lab 1

Digital Design Lecture Videos for Lab 1

Digital Design Example Videos for Lab 1

Sample Lab Handout

Lab 1 Handout

Digital Design Refresher for Lab 1

Available on EECS 31/CSE 31 Course Page

Lab 1 Quiz Sample Problems

Sample Problem 1

Question

The following VHDL code for gate level logic does not compile and simulate correctly with ModelSim as written below. In the table below, rewrite the minimum number of lines to make the entire code compile and simulate correctly.

Sample Problem 1 Figure

Solution

Line # Code
10 end final_prob1;
13 process (k, p, s)

Detailed Explanation

View Video Explanation for Problem 1

Sample Problem 2

Question

The following VHDL code for an AND function of two 2-bit vectors A and B does not compile and simulate correctly with ModelSim. In the table below, rewrite the minimum number of lines so that code correctly simulates.

Sample Problem 2 Figure

Solution

Line # Code
11 F <= A AND B;
or: 11 F <= (A(1) AND B(1)) & (A(0) AND B(0));

Detailed Explanation

View Video Explanation for Problem 2

Sample Problem 3

Question

Fix the given code for testing a DUT for 60 ns so it generates the test vectors from the time diagram in Figure 1.

Sample Problem 3 Figure - Test Vector

Figure 1: Test Vector

Sample Problem 3 Figure - VHDL Code

Solution

Line # Code
16 WAIT FOR 10 ns;
18 WAIT FOR 20 ns;
24 WAIT;

Detailed Explanation

View Video Explanation for Problem 3

Sample Problem 4

Question

Complete the port map of the given VHDL code so it correctly implements the following design:

Winter 2010 Finals Problem 2 Figure - Design

Winter 2010 Finals Problem 2 Figure - VHDL Code

Solution

Line # Code
18 And2_1: And2 PORT MAP (i0, i2, n1);
19 And2_2: And2 PORT MAP (n2, i1, d);
20 CustHW: CustomHW PORT MAP (n1, n2);

Detailed Explanation

View Video Explanation for Problem 4