";
    // print_r ($auth_object);
    // print "

EECS 31L/CSE 31L: Lab 0 (Sample Lab)

Objective

In this assignment, you will design a small digital circuit, called DriveLock that locks the car driving (by setting an output w to 1) if either of the following conditions are met:

1. A car's key is in the car's ignition slot (indicated by an input k being 1), and a passenger is seated (indicated by an input p being 1), and the passenger's seat belt is not buckled (indicated by a input s being 0)
2. A car's key is in the car's ignition slot (indicated by an input k being 1), and a passenger is seated (indicated by an input p being 1), and the car door is not closed (indicated by a input d being 0).

The purpose of this assignment is threefold:

1. To refresh your memory on logic design that you have learned in digital design class (see video: Logic Design),
2. To get used to Xilinx design and simulation tools (see video Simulation Principles and 31L and Xilinx tutorial videos),
3. To learn some VHDL basics (see Lab1 videos: Logic Gates, Logic Components, and Hierarchical Components).

Procedure

This lab assignment requires you to translate a design specification in English language into a digital design consisting of gates from the given library. You are asked to develop a behavioral (functional) and structural (netlist) model and compare them with simulation (see Lab 1 videos for definition of behavioral and structural models).

1. Create a truth table for the DriveLock from the English description above;
2. Derive a minimal sum-of-products or product-of-sums Boolean equation;
3. Modify Boolean equation for implementation with 2-input NOR gates using Boolean algebra rules;
4. Optimize the equation for minimal input-output delay with 2-input NOR gates (1.4ns delay each);
5. Create VHDL behavioral description for DriveLock;
6. Create VHDL structural description for DriveLock;
7. Create test bench for DriveLock;
8. Simulate your design and report the input-output delay. Repeat until results match all the cases in the truth table.

Deliverable

Upload your VHDL file to drop box (EECS31/CSE31L>31Lab1>Assignment submission).

File names should be "lab1b_studentID.vhd", "lab1s_studentID.vhd", "lab1b_studentID_tb.vhd", and "lab1s_studentID_tb.vhd".

Example:

If your student ID is "12345678", then you should submit "Lab1b_12345678.vhd" for your behavioral model and "Lab1s_12345678.vhd" for your structural model.

Use the following templates:

Notes:

1. The templates include declaration of the entities that you have to design. You have to add the behavior and structural architecture.
2. Do NOT change the names of the entities and ports in the templates.

Template 1: lab0b_studentID.vhd

----------------------------------------------------------------------
-- EECS31L/CSE31L Assignment0
-- DriveLock Behavioral Model
----------------------------------------------------------------------
-- Student First Name : Your First Name
-- Student Last Name : Your Last Name
-- Student ID : Your Student ID
----------------------------------------------------------------------

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
 
ENTITY DriveLock_behav IS
   PORT (k, p, s, d: IN std_logic;
         w: OUT std_logic);
END DriveLock_behav;

ARCHITECTURE Behav OF DriveLock_behav IS


-- add your code here

END Behav;

Template 2: lab0s_studentID.vhd

----------------------------------------------------------------------
-- EECS31L/CSE31L Assignment0
-- DriveLock Structural Model
----------------------------------------------------------------------
-- Student First Name : Your First Name
-- Student Last Name : Your Last Name
-- Student ID : Your Student ID
----------------------------------------------------------------------

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY NOR2 IS
   PORT (x: IN std_logic;
         y: IN std_logic;
         F: OUT std_logic);
END NOR2;  

ARCHITECTURE behav OF NOR2 IS
BEGIN
   PROCESS(x, y)
   BEGIN
      F <= x NOR y AFTER 1.4 ns; 
   END PROCESS;
END behav;
----------------------------------------------------------------------

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY DriveLock_struct IS
   PORT (k, p, s, d: IN std_logic;
         w: OUT std_logic);
END DriveLock_struct;

ARCHITECTURE Struct OF DriveLock_struct IS

-- add your code here

END Struct;