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ICCAD 2003 :
[ <a href="iccadabs.htm">Abstracts</a> ]
[ <a href="iccadses.htm">Session Index</a> ]
[ <a href="iccadai.htm">Author Index</a> ]</h3>
<hr>
<h2>ICCAD 2003 TABLE OF CONTENTS</h2>
<b>
Sessions:
[<a href="#sess1a">1A</a>]
[<a href="#sess1b">1B</a>]
[<a href="#sess1c">1C</a>]
[<a href="#sess1d">1D</a>]
[<a href="#sess2a">2A</a>]
[<a href="#sess2b">2B</a>]
[<a href="#sess2c">2C</a>]
[<a href="#sess3a">3A</a>]
[<a href="#sess3b">3B</a>]
[<a href="#sess3c">3C</a>]
[<a href="#sess3d">3D</a>]
[<a href="#sess4a">4A</a>]
[<a href="#sess4b">4B</a>]
[<a href="#sess4c">4C</a>]
[<a href="#sess4d">4D</a>]
[<a href="#sess5a">5A</a>]
[<a href="#sess5b">5B</a>]
[<a href="#sess5c">5C</a>]
[<a href="#sess5d">5D</a>]
[<a href="#sess6a">6A</a>]
[<a href="#sess6b">6B</a>]
[<a href="#sess6c">6C</a>]
[<a href="#sess6d">6D</a>]
[<a href="#sess7a">7A</a>]
[<a href="#sess7b">7B</a>]
[<a href="#sess7c">7C</a>]
[<a href="#sess7d">7D</a>]
[<a href="#sess8a">8A</a>]
[<a href="#sess8b">8B</a>]
[<a href="#sess8c">8C</a>]
[<a href="#sess8d">8D</a>]
[<a href="#sess9a">9A</a>]
[<a href="#sess9b">9B</a>]
[<a href="#sess9c">9C</a>]
[<a href="#sess9d">9D</a>]
[<a href="#sess10a">10A</a>]
[<a href="#sess10b">10B</a>]
[<a href="#sess10c">10C</a>]
[<a href="#sess10d">10D</a>]
[<a href="#sess11a">11A</a>]
[<a href="#sess11b">11B</a>]
[<a href="#sess11c">11C</a>]
[<a href="#sess11d">11D</a>]<p>
<a href="../../pdffiles/confcom.pdf">Conference Committee</a><br>
<a href="../../pdffiles/foreword.pdf">Foreword</a><br>
<a href="../../pdffiles/awards.pdf">Awards</a><br>
<a href="../../pdffiles/techcom.pdf">Technical Program Committee</a><br>
<a href="../../pdffiles/reviewer.pdf">Reviewers</a><br>
<a href="../../pdffiles/keynote.pdf">Keynote</a><br>
<a href="../../pdffiles/tut1.pdf">Tutorial 1: LINUX for EDA</a><br>
<a href="../../pdffiles/tut2.pdf">Tutorial 2: Leakage Issues in IC Design: Trends, Estimation, and Avoidance</a><br>
<a href="../../pdffiles/tut3.pdf">Tutorial 3: Recent Advances in Formal Verification</a><br>
<a href="../../pdffiles/tut4.pdf">Tutorial 4: Embedded Software Development</a><br>
<a href="../../pdffiles/sunpan.pdf">Sunday Panel: CAD for High-End Design: Help, Hope, or Hype ?</a><br>
<a href="../../pdffiles/monpan.pdf">Monday Panel: Semiconductor Slowdown: Who Will Blink First ?</a><p>
</b>
<hr>
<h2>Session 1A: <a href="iccadabs.htm#sess1a" NAME="sess1a">
Interconnect-Centric SoC Design
</a></h2>
<i>
Moderators: Kaustav Banerjee - Univ. of California, Santa Barbara, CA
<br>
Tajana Simunic - Hewlett-Packard Labs./Stanford Univ., Palo Alto, CA
</i><p>
<dl>
<dt>
<a href="iccadabs.htm#01a_1"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/01a_1.pdf"><img src="../../../../../icons/pdficon.gif"></a>
1A.1 Adaptive Error Protection for Energy Efficiency [p. 2]
<dd><i>
Lin Li, N. Vijaykrishnan, Mahmut Kandemir, Mary Jane Irwin
</i><p>
<dt>
<a href="iccadabs.htm#01a_2"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/01a_2.pdf"><img src="../../../../../icons/pdficon.gif"></a>
1A.2 SAMBA-Bus: A High Performance Bus Architecture for System-on-Chips [p. 8]
<dd><i>
Ruibing Lu, Cheng-Kok Koh
</i><p>
<dt>
<a href="iccadabs.htm#01a_3"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/01a_3.pdf"><img src="../../../../../icons/pdficon.gif"></a>
1A.3 The Y-Architecture for On-Chip Interconnect: Analysis and Methodology [p. 13]
<dd><i>
Hongyu Chen, Chung-Kuan Cheng, Andrew B. Kahng, Ion Mandoiu, Qinke Wang,
Bo Yao
</i><p>
</dl>
<hr>
<h2>Session 1B: <a href="iccadabs.htm#sess1b" NAME="sess1b">
Energy Optimization using Dynamic Voltage Scaling for Embedded Systems
</a></h2>
<i>
Moderators: Stan Y. Liao - Synopsys, Inc., Mountain View, CA
<br>
Hiroyuki Tomiyama - Nagoya Univ., Nagoya, Japan
</i><p>
<dl>
<dt>
<a href="iccadabs.htm#01b_1"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/01b_1.pdf"><img src="../../../../../icons/pdficon.gif"></a>
1B.1 Generalized Network Flow Techniques for Dynamic Voltage Scaling in Hard Real-
Time Systems [p. 21]
<dd><i>
Vishnu Swaminathan, Krishnendu Chakrabarty
</i><p>
<dt>
<a href="iccadabs.htm#01b_2"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/01b_2.pdf"><img src="../../../../../icons/pdficon.gif"></a>
1B.2 Approaching the Maximum Energy Saving on Embedded Systems with Multiple
Voltages [p. 26]
<dd><i>
Shaoxiong Hua, Gang Qu
</i><p>
<dt>
<a href="iccadabs.htm#01b_3"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/01b_3.pdf"><img src="../../../../../icons/pdficon.gif"></a>
1B.3 Combined Dynamic Voltage Scaling and Adaptive Body Biasing for Heterogeneous
Distributed Real-Time Embedded Systems [p. 30]
<dd><i>
Le Yan, Jiong Luo, Niraj K. Jha
</i><p>
</dl>
<hr>
<h2>Session 1C: <a href="iccadabs.htm#sess1c" NAME="sess1c">
New Opportunities in High-Level Synthesis
</a></h2>
<i>
Moderators: James C. Hoe - Carnegie Mellon Univ., Pittsburgh, PA
<br>
Steve Haynal - Intel Corp., Hillsboro, OR
</i><p>
<dl>
<dt>
<a href="iccadabs.htm#01c_1"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/01c_1.pdf"><img src="../../../../../icons/pdficon.gif"></a>
1C.1 RTL Power Optimization with Gate Level Accuracy [p. 39]
<dd><i>
Qi Wang, Sumit Roy
</i><p>
<dt>
<a href="iccadabs.htm#01c_2"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/01c_2.pdf"><img src="../../../../../icons/pdficon.gif"></a>
1C.2 Synthesis of Heterogeneous Distributed Architectures for Memory-Intensive
Applications [p. 46]
<dd><i>
Chao Huang, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
</i><p>
<dt>
<a href="iccadabs.htm#01c_3"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/01c_3.pdf"><img src="../../../../../icons/pdficon.gif"></a>
1C.3 Achieving Design Closure Through Delay Relaxation Parameter [p. 54]
<dd><i>
Ankur Srivastava, Seda Ogrenci Memik, Bo-Kyung Choi, Majid Sarrafzadeh
</i><p>
<dt>
<a href="iccadabs.htm#01c_4"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/01c_4.pdf"><img src="../../../../../icons/pdficon.gif"></a>
1C.4 Hardware Scheduling for Dynamic Adaptability using External Profiling and
Hardware Threading [p. 58]
<dd><i>
Brian Swahn, Soha Hassoun
</i><p>
</dl>
<hr>
<h2>Session 1D: <a href="iccadabs.htm#sess1d" NAME="sess1d">
New Ideas in Placement and Floorplanning
</a></h2>
<i>
Moderators: Zhigang (David) Pan - IBM Corp., Yorktown Heights, NY
<br>
Kia Bazargan - Univ. of Minnesota, Minneapolis, MN
</i><p>
<dl>
<dt>
<a href="iccadabs.htm#01d_1"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/01d_1.pdf"><img src="../../../../../icons/pdficon.gif"></a>
1D.1 Bus-Driven Floorplanning [p. 66]
<dd><i>
Hua Xiang, Xiaoping Tang, Martin D. F. Wong
</i><p>
<dt>
<a href="iccadabs.htm#01d_2"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/01d_2.pdf"><img src="../../../../../icons/pdficon.gif"></a>
1D.2 A Novel Geometric Algorithm for Fast Wire-Optimized Floorplanning [p. 74]
<dd><i>
Peter G. Sassone, Sung K. Lim
</i><p>
<dt>
<a href="iccadabs.htm#01d_3"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/01d_3.pdf"><img src="../../../../../icons/pdficon.gif"></a>
1D.3 Placement Method Targeting Predictability Robustness and Performance [p. 81]
<dd><i>
Cristinel Ababei, Kia Bazargan
</i><p>
<dt>
<a href="iccadabs.htm#01d_4"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/01d_4.pdf"><img src="../../../../../icons/pdficon.gif"></a>
1D.4 Efficient Thermal Placement of Standard Cells in 3D ICs using a Force Directed
Approach [p. 86]
<dd><i>
Brent A. Goplen, Sachin S. Sapatnekar
</i><p>
</dl>
<hr>
<h2>Session 2A: <a href="iccadabs.htm#sess2a" NAME="sess2a">
Improvements in SoC Testing
</a></h2>
<i>
Moderators: Bozena Kaminska - 3MTS, Lake Oswego, OR
<br>
Krishnendu Chakrabarty - Duke Univ., Durham, NC
</i><p>
<dl>
<dt>
<a href="iccadabs.htm#02a_1"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/02a_1.pdf"><img src="../../../../../icons/pdficon.gif"></a>
2A.1 Partial Core Encryption for Performance-Efficient Test of SoCs [p. 91]
<dd><i>
Ozgur Sinanoglu, Alex Orailoglu
</i><p>
<dt>
<a href="iccadabs.htm#02a_2"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/02a_2.pdf"><img src="../../../../../icons/pdficon.gif"></a>
2A.2 TAM Optimization for Mixed-Signal SoCs using Analog Test Wrappers [p. 95]
<dd><i>
Anuja Sehgal, Sule Ozev, Krishnendu Chakrabarty
</i><p>
<dt>
<a href="iccadabs.htm#02a_3"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/02a_3.pdf"><img src="../../../../../icons/pdficon.gif"></a>
2A.3 Using Distributed Rectangle Bin-Packing Approach for Core-based SoC Test
Scheduling with Power Constraints [p. 100]
<dd><i>
Yu Xia, Malgorzata E. Chrzanowska-Jeske, Benyi Wang, Marcin Jeske
</i><p>
</dl>
<hr>
<h2>Session 2B: <a href="iccadabs.htm#sess2b" NAME="sess2b">
Electrical and Power Models - System to Transistor Level
</a></h2>
<i>
Moderators: David Overhauser - Cadence Design Systems, Inc., San Jose, CA
<br>
Farid N. Najm - Univ. of Toronto, Toronto, Canada
</i><p>
<dl>
<dt>
<a href="iccadabs.htm#02b_1"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/02b_1.pdf"><img src="../../../../../icons/pdficon.gif"></a>
2B.1 Moment-Based Power Estimation in Very Deep Submicron Technologies [p. 107]
<dd><i>
Alberto Garcia-Ortiz, Lukusa Kabulepa, Tudor Murgan, Manfred Glesner
</i><p>
<dt>
<a href="iccadabs.htm#02b_2"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/02b_2.pdf"><img src="../../../../../icons/pdficon.gif"></a>
2B.2 IDAP: A Tool for High Level Power Estimation of Custom Array Structures [p. 113]
<dd><i>
Mahesh N. Mamidipaka, Kamal Khouri, Nikil Dutt, Magdy Abadir
</i><p>
<dt>
<a href="iccadabs.htm#02b_3"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/02b_3.pdf"><img src="../../../../../icons/pdficon.gif"></a>
2B.3 SOI Transistor Model for Fast Transient Simulation [p. 120]
<dd><i>
Dmitry Nadezhin, Sergey Gavrilov, Alexey Glebov, Yury Egorov, Vladimir P.
Zolotov, David Blaauw, Rajendran Panda, Murat Becer, Alexandre Ardelea,
Ajay Patel
</i><p>
</dl>
<hr>
<h2>Session 2C: <a href="iccadabs.htm#sess2c" NAME="sess2c">
Embedded Tutorial: Design and CAD Challenges for sub-90nm CMOS
Technology
</a></h2>
<i>
Moderators: Dennis Sylvester - Univ. of Michigan, Ann Arbor, MI
<br>
Thomas Burd - Consultant, Berkeley, CA
</i><p>
<dl>
<dt>
<a href="iccadabs.htm#02c_1"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/02c_1.pdf"><img src="../../../../../icons/pdficon.gif"></a>
2C.1 Embedded Tutorial: Design and CAD Challenges in sub-90nm CMOS Technologies [p. 129]
<dd><i>
Kerry Bernstein, Ching-Te Chuang, Rajiv V. Joshi, Ruchir Puri
</i><p>
</dl>
<hr>
<h2>Session 3A: <a href="iccadabs.htm#sess3a" NAME="sess3a">
Emerging Techniques in Dynamic Verification
</a></h2>
<i>
Moderators: Jay Lawrence - Cadence Design Systems, Inc., Chelmsford, MA
<br>
Arturo Salz - Synopsys, Inc., Mountain View, CA
</i><p>
<dl>
<dt>
<a href="iccadabs.htm#03a_1"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/03a_1.pdf"><img src="../../../../../icons/pdficon.gif"></a>
3A.1 Fast Cycle-Accurate Behavioral Simulation for Pipelined Processors using Early
Pipeline Evaluation [p. 138]
<dd><i>
In-Cheol Park, Sehyeon Kang, Yongseok Yi
</i><p>
<dt>
<a href="iccadabs.htm#03a_2"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/03a_2.pdf"><img src="../../../../../icons/pdficon.gif"></a>
3A.2 A Framework for Constrained Functional Verification [p. 142]
<dd><i>
Jun Yuan, Carl Pixley, Adnan Aziz, Ken Albin
</i><p>
<dt>
<a href="iccadabs.htm#03a_3"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/03a_3.pdf"><img src="../../../../../icons/pdficon.gif"></a>
3A.3 Generator-Based Verification [p. 146]
<dd><i>
Yunshan Zhu, James H. Kukula
</i><p>
<dt>
<a href="iccadabs.htm#03a_4"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/03a_4.pdf"><img src="../../../../../icons/pdficon.gif"></a>
3A.4 Efficient Generation of Monitor Circuits for GSTE Assertion Graphs [p. 154]
<dd><i>
Alan J. Hu, Jeremy Casas, Jin Yang
</i><p>
</dl>
<hr>
<h2>Session 3B: <a href="iccadabs.htm#sess3b" NAME="sess3b">
Delay and Signal Modeling for Timing Analysis
</a></h2>
<i>
Moderators: David J. Hathaway - IBM Corp., Essex Junction, VT
<br>
Timothy Burks - Magma Design Automation, Cupertino, CA
</i><p>
<dl>
<dt>
<a href="iccadabs.htm#03b_1"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/03b_1.pdf"><img src="../../../../../icons/pdficon.gif"></a>
3B.1 Weibull Based Analytical Waveform Model [p. 161]
<dd><i>
Chirayu S. Amin, Florentin Dartu, Yehea I. Ismail
</i><p>
<dt>
<a href="iccadabs.htm#03b_2"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/03b_2.pdf"><img src="../../../../../icons/pdficon.gif"></a>
3B.2 Equivalent Waveform Propagation for Static Timing Analysis [p. 169]
<dd><i>
Masanori Hashimoto, Yuji Yamada, Hidetoshi Onodera
</i><p>
<dt>
<a href="iccadabs.htm#03b_3"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/03b_3.pdf"><img src="../../../../../icons/pdficon.gif"></a>
3B.3 Timing Analysis in Presence of Power Supply and Ground Voltage Variations [p. 176]
<dd><i>
Rubil Ahmadi, Farid N. Najm
</i><p>
<dt>
<a href="iccadabs.htm#03b_4"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/03b_4.pdf"><img src="../../../../../icons/pdficon.gif"></a>
3B.4 Vectorless Analysis of Supply Noise Induced Delay Variation [p. 184]
<dd><i>
Sanjay Pant, David Blaauw, Vladimir Zolotov, Savithri Sundareswaran,
Rajendran Panda
</i><p>
</dl>
<hr>
<h2>Session 3C: <a href="iccadabs.htm#sess3c" NAME="sess3c">
Software Techniques for Energy and Performance Optimization in Embedded
Systems
</a></h2>
<i>
Moderators: Wen-Mei W. Hwu - Univ. of Illinois, Urbana, IL
<br>
Rainer Leupers - RWTH Aachen Univ. of Tech., Aachen, Germany
</i><p>
<dl>
<dt>
<a href="iccadabs.htm#03c_1"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/03c_1.pdf"><img src="../../../../../icons/pdficon.gif"></a>
3C.1 Array Composition and Decomposition for Optimizing Embedded Applications [p. 193]
<dd><i>
Guilin Chen, Mahmut Kandemir, Ugur Sezer, Avanti Nadgir
</i><p>
<dt>
<a href="iccadabs.htm#03c_2"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/03c_2.pdf"><img src="../../../../../icons/pdficon.gif"></a>
3C.2 Code Placement with Selective Cache Activity Minimization for Embedded Real-Time
Software Design [p. 197]
<dd><i>
Junhyung Um, Taewhan Kim
</i><p>
<dt>
<a href="iccadabs.htm#03c_3"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/03c_3.pdf"><img src="../../../../../icons/pdficon.gif"></a>
3C.3 Energy Optimization of Distributed Embedded Processors by Combined Data
Compression and Functional Partitioning [p. 201]
<dd><i>
Jinfeng Liu, Pai H. Chou
</i><p>
<dt>
<a href="iccadabs.htm#03c_4"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/03c_4.pdf"><img src="../../../../../icons/pdficon.gif"></a>
3C.4 Energy-Aware Fault Tolerance in Fixed-Priority Real-Time Embedded Systems [p. 209]
<dd><i>
Ying Zhang, Krishnendu Chakrabarty, Vishnu Swaminathan
</i><p>
</dl>
<hr>
<h2>Session 3D: <a href="iccadabs.htm#sess3d" NAME="sess3d">
Optimization of Global Interconnects
</a></h2>
<i>
Moderators: Martin D. F. Wong - Univ. of Illinois, Urbana, IL
<br>
Atsushi Takahashi - Tokyo Institute of Tech., Tokyo, Japan
</i><p>
<dl>
<dt>
<a href="iccadabs.htm#03d_1"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/03d_1.pdf"><img src="../../../../../icons/pdficon.gif"></a>
3D.1 Retiming for Wire Pipelining in System-On-Chip [p. 215]
<dd><i>
Chuan Lin, Hai Zhou
</i><p>
<dt>
<a href="iccadabs.htm#03d_2"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/03d_2.pdf"><img src="../../../../../icons/pdficon.gif"></a>
3D.2 Retiming with Interconnect and Gate Delay [p. 221]
<dd><i>
Chris Chu, Evangeline F. Y. Young, Dennis K. Y. Tong, Sampath Dechu
</i><p>
<dt>
<a href="iccadabs.htm#03d_3"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/03d_3.pdf"><img src="../../../../../icons/pdficon.gif"></a>
3D.3 Performance Optimization of Latency Insensitive Systems through Buffer Queue
Sizing of Communication Channels [p. 227]
<dd><i>
Ruibing Lu, Cheng-Kok Koh
</i><p>
<dt>
<a href="iccadabs.htm#03d_4"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/03d_4.pdf"><img src="../../../../../icons/pdficon.gif"></a>
3D.4 Clock Scheduling and Clocktree Construction for High Performance ASICs [p. 232]
<dd><i>
Stephan Held, Bernhard Korte, Jens Maßberg, Matthias Ringe, Jens Vygen
</i><p>
</dl>
<hr>
<h2>Session 4A: <a href="iccadabs.htm#sess4a" NAME="sess4a">
Numerical Methods for Analog Optimization and Analysis
</a></h2>
<i>
Moderators: Eric Bracken - Ansoft Corp., Pittsburgh, PA
<br>
Joel R. Phillips - Cadence Berkeley Labs., San Jose, CA
</i><p>
<dl>
<dt>
<a href="iccadabs.htm#04a_1"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/04a_1.pdf"><img src="../../../../../icons/pdficon.gif"></a>
4A.1 Initial Sizing of Analog Integrated Circuits by Centering within Topology-Given
Implicit Specifications [p. 241]
<dd><i>
Guido Stehr, Michael Pronath, Frank Schenkel, Helmut Graeb, Kurt Antreich
</i><p>
<dt>
<a href="iccadabs.htm#04a_2"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/04a_2.pdf"><img src="../../../../../icons/pdficon.gif"></a>
4A.2 A Generalized Method for Computing Oscillator Phase Noise Spectra [p. 247]
<dd><i>
Piet Vanassche, Georges G. Gielen, Willy Sansen
</i><p>
<dt>
<a href="iccadabs.htm#04a_3"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/04a_3.pdf"><img src="../../../../../icons/pdficon.gif"></a>
4A.3 Efficient Iterative Time Preconditioners for Harmonic Balance RF Circuit Simulation [p. 251]
<dd><i>
Fabrice Veersé
</i><p>
</dl>
<hr>
<h2>Session 4B: <a href="iccadabs.htm#sess4b" NAME="sess4b">
CAD Algorithms for Emerging Technologies
</a></h2>
<i>
Moderators: Bernard Courtois - TIMA Labs., Grenoble, France
<br>
Michael R. Butts - Cadence Design Systems, Inc., Portland, OR
</i><p>
<dl>
<dt>
<a href="iccadabs.htm#04b_1"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/04b_1.pdf"><img src="../../../../../icons/pdficon.gif"></a>
4B.1 Fredkin/Toffoli Templates for Reversible Logic Synthesis [p. 256]
<dd><i>
Dmitri Maslov, Gerhard W. Dueck, David M. Miller
</i><p>
<dt>
<a href="iccadabs.htm#04b_2"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/04b_2.pdf"><img src="../../../../../icons/pdficon.gif"></a>
4B.2 Evaluation of Placement Techniques for DNA Probe Array Layout [p. 262]
<dd><i>
Andrew B. Kahng, Ion Mandoiu, Sherief Reda, Xu Xu, Alex Z. Zelikovsky
</i><p>
<dt>
<a href="iccadabs.htm#04b_3"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/04b_3.pdf"><img src="../../../../../icons/pdficon.gif"></a>
4B.3 Physical and Reduced-Order Dynamic Analysis of MEMS [p. 270]
<dd><i>
Sudipto K. DE, Narayan Aluru
</i><p>
</dl>
<hr>
<h2>Session 4C: <a href="iccadabs.htm#sess4c" NAME="sess4c">
Design Techniques for Customized Processors
</a></h2>
<i>
Moderators: Radu Marculescu - Carnegie Mellon Univ., Pittsburgh, PA
<br>
Tony Givargis - Univ. of California, Irvine, CA
</i><p>
<dl>
<dt>
<a href="iccadabs.htm#04c_1"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/04c_1.pdf"><img src="../../../../../icons/pdficon.gif"></a>
4C.1 Fast, Accurate Static Analysis for Fixed-Point Finite Precision Effects in DSP Designs [p. 275]
<dd><i>
Claire F. Fang, Rob A. Rutenbar, Tsuhan Chen
</i><p>
<dt>
<a href="iccadabs.htm#04c_2"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/04c_2.pdf"><img src="../../../../../icons/pdficon.gif"></a>
4C.2 A Scalable Application-Specific Processor Synthesis Methodology [p. 283]
<dd><i>
Fei Sun, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
</i><p>
<dt>
<a href="iccadabs.htm#04c_3"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/04c_3.pdf"><img src="../../../../../icons/pdficon.gif"></a>
4C.3 INSIDE: INstruction Selection/Identification & Design Exploration for Extensible
Processors [p. 291]
<dd><i>
Newton Cheung, Sri Parameswaran, Joerg Henkel
</i><p>
</dl>
<hr>
<h2>Session 4D: <a href="iccadabs.htm#sess4d" NAME="sess4d">
New Improvements in Placement
</a></h2>
<i>
Moderators: Kia Bazargan - Univ. of Minnesota, Minneapolis, MN
<br>
Salil Raje - Hier Design Inc., Santa Clara, CA
</i><p>
<dl>
<dt>
<a href="iccadabs.htm#04d_1"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/04d_1.pdf"><img src="../../../../../icons/pdficon.gif"></a>
4D.1 An Enhanced Multilevel Algorithm for Circuit Placement [p. 299]
<dd><i>
Tony F. Chan, Jason Cong, Tim Kong, Joseph R. Shinnerl, Kenton Sze
</i><p>
<dt>
<a href="iccadabs.htm#04d_2"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/04d_2.pdf"><img src="../../../../../icons/pdficon.gif"></a>
4D.2 Fractional Cut: Improved Recursive Bisection Placement [p. 307]
<dd><i>
Ameya Agnihotri, Mehmet C. YILDIZ, Ateen Khatkhate, Ajita Mathur, Satoshi Ono,
Patrick H. Madden
</i><p>
<dt>
<a href="iccadabs.htm#04d_3"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/04d_3.pdf"><img src="../../../../../icons/pdficon.gif"></a>
4D.3 On Whitespace and Stability in Mixed-Size Placement and Physical Synthesis [p. 311]
<dd><i>
Saurabh N. Adya, Igor L. Markov, Paul G. Villarrubia
</i><p>
</dl>
<hr>
<h2>Session 5A: <a href="iccadabs.htm#sess5a" NAME="sess5a">
Optimizations for Verification Engines
</a></h2>
<i>
Moderators: Aarti Gupta - NEC Labs., Princeton, NJ
<br>
Eugene Goldberg - Cadence Berkeley Labs., Berkeley, CA
</i><p>
<dl>
<dt>
<a href="iccadabs.htm#05a_1"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/05a_1.pdf"><img src="../../../../../icons/pdficon.gif"></a>
5A.1 SATORI -- A Fast Sequential SAT Engine for Circuits [p. 320]
<dd><i>
Madhu Iyer, Ganapathy Parthasarathy, Kwang Ting (Tim) Cheng
</i><p>
<dt>
<a href="iccadabs.htm#05a_2"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/05a_2.pdf"><img src="../../../../../icons/pdficon.gif"></a>
5A.2 CAMA: A Multi-Valued Satisfiability Solver [p. 326]
<dd><i>
Cong Liu, Andreas Kuehlmann, Matthew W. Moskewicz
</i><p>
<dt>
<a href="iccadabs.htm#05a_3"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/05a_3.pdf"><img src="../../../../../icons/pdficon.gif"></a>
5A.3 The Compositional Far Side of Image Computation [p. 334]
<dd><i>
Chao Wang, Gary D. Hachtel, Fabio Somenzi
</i><p>
</dl>
<hr>
<h2>Session 5B: <a href="iccadabs.htm#sess5b" NAME="sess5b">
System Design Concepts
</a></h2>
<i>
Moderators: Vijaykrishnan Narayanan - Penn State Univ., University Park, PA
<br>
Yatin Hoskote - Intel Corp., Portland, OR
</i><p>
<dl>
<dt>
<a href="iccadabs.htm#05b_1"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/05b_1.pdf"><img src="../../../../../icons/pdficon.gif"></a>
5B.1 Cache Optimization For Embedded Processor Cores: An Analytical Approach [p. 342]
<dd><i>
Arijit Ghosh, Tony Givargis
</i><p>
<dt>
<a href="iccadabs.htm#05b_2"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/05b_2.pdf"><img src="../../../../../icons/pdficon.gif"></a>
5B.2 Fault-Tolerant Techniques for Ambient Intelligent Distributed Systems [p. 348]
<dd><i>
Diana Marculescu, Nicholas H. Zamora, Phillip Stanley-Marbell,
Radu Marculescu
</i><p>
<dt>
<a href="iccadabs.htm#05b_3"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/05b_3.pdf"><img src="../../../../../icons/pdficon.gif"></a>
5B.3 Performance Efficiency of Context-Flow System-On-Chip Platform [p. 356]
<dd><i>
Rami Beidas, Jianwen Zhu
</i><p>
</dl>
<hr>
<h2>Session 5C: <a href="iccadabs.htm#sess5c" NAME="sess5c">
Analog Design and Methodology
</a></h2>
<i>
Moderators: Kenneth Kundert - Cadence Design Systems, Inc., San Jose, CA
<br>
Georges G. Gielen - Katholieke Univ., Leuven, Belgium
</i><p>
<dl>
<dt>
<a href="iccadabs.htm#05c_1"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/05c_1.pdf"><img src="../../../../../icons/pdficon.gif"></a>
5C.1 Amplification of Ultrawideband Signals [p. 363]
<dd><i>
Won Namgoong, Jongrit Lerdworatawee
</i><p>
<dt>
<a href="iccadabs.htm#05c_2"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/05c_2.pdf"><img src="../../../../../icons/pdficon.gif"></a>
5C.2 A Statistical Approach to Estimate the Dynamic Non-Linearity Parameters of Pipeline
ADCs [p. 367]
<dd><i>
Mohammad Taherzadeh-Sani, Reza Lotfi, Omid Shoaei
</i><p>
<dt>
<a href="iccadabs.htm#05c_3"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/05c_3.pdf"><img src="../../../../../icons/pdficon.gif"></a>
5C.3 Systematic Design for Power Minimization of Pipelined Analog-to-Digital Converters [p. 371]
<dd><i>
Reza Lotfi, Mohammad Taherzadeh-Sani, Mohammad Yaser Azizi, Omid Shoaei
</i><p>
<dt>
<a href="iccadabs.htm#05c_4"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/05c_4.pdf"><img src="../../../../../icons/pdficon.gif"></a>
5C.4 A Framework for Designing Reusable Analog Circuits [p. 375]
<dd><i>
Dean Liu, Stefanos Sidiropoulos, Mark Horowtiz
</i><p>
</dl>
<hr>
<h2>Session 5D: <a href="iccadabs.htm#sess5d" NAME="sess5d">
Routing
</a></h2>
<i>
Moderators: Hai Zhou - Northwestern Univ., Evanston, IL
<br>
Charles Chiang - Synopsys, Inc., Mountain View, CA
</i><p>
<dl>
<dt>
<a href="iccadabs.htm#05d_1"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/05d_1.pdf"><img src="../../../../../icons/pdficon.gif"></a>
5D.1 A Fast Crosstalk- and Performance-Driven Multilevel Routing System [p. 382]
<dd><i>
Tsung-Yi Ho, Yao-Wen Chang, Sao-Jie Chen, and D. T. Lee
</i><p>
<dt>
<a href="iccadabs.htm#05d_2"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/05d_2.pdf"><img src="../../../../../icons/pdficon.gif"></a>
5D.2 A Min-Cost Flow Based Detailed Router for FPGAs [p. 388]
<dd><i>
Seokjin Lee, Yongseok Cheon, Martin D. F. Wong
</i><p>
<dt>
<a href="iccadabs.htm#05d_3"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/05d_3.pdf"><img src="../../../../../icons/pdficon.gif"></a>
5D.3 Length-Matching Routing for High-Speed Printed Circuit Boards [p. 394]
<dd><i>
Muhammet Mustafa Ozdal, Martin D. F. Wong
</i><p>
<dt>
<a href="iccadabs.htm#05d_4"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/05d_4.pdf"><img src="../../../../../icons/pdficon.gif"></a>
5D.4 Analytical Bound for Unwanted Clock Skew Due to Wire Width Variation [p. 401]
<dd><i>
Anand K. Rajaram, Bing Lu, Wei Guo, Rabi N. Mahapatra, Jiang Hu
</i><p>
</dl>
<hr>
<h2>Session 6A: <a href="iccadabs.htm#sess6a" NAME="sess6a">
Automatic Abstraction for Formal Verification
</a></h2>
<i>
Moderators: James H. Kukula - Synopsys, Inc., Hillsboro, OR
<br>
Ken McMillan - Cadence Berkeley Labs., Berkeley, CA
</i><p>
<dl>
<dt>
<a href="iccadabs.htm#06a_1"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/06a_1.pdf"><img src="../../../../../icons/pdficon.gif"></a>
6A.1 Improving Ariadne's Bundle by Following Multiple Threads in Abstraction
Refinement [p. 408]
<dd><i>
Chao Wang, Bing Li, HoonSang Jin, Gary D. Hachtel, Fabio Somenzi
</i><p>
<dt>
<a href="iccadabs.htm#06a_2"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/06a_2.pdf"><img src="../../../../../icons/pdficon.gif"></a>
6A.2 Iterative Abstraction using SAT-based BMC with Proof Analysis [p. 416]
<dd><i>
Aarti Gupta, Malay Ganai, Zijiang Yang, Pranav Ashar
</i><p>
<dt>
<a href="iccadabs.htm#06a_3"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/06a_3.pdf"><img src="../../../../../icons/pdficon.gif"></a>
6A.3 Efficient Verification of Hazard-Freedom in Gate-Level Timed Asynchronous Circuits [p. 424]
<dd><i>
Curtis A. Nelson, Chris J. Myers, Tomohiro Yoneda
</i><p>
</dl>
<hr>
<h2>Session 6B: <a href="iccadabs.htm#sess6b" NAME="sess6b">
Embedded Tutorial: System Level Design and Verification using a
Synchronous Lan
</a></h2>
<i>
Moderators: Nikil Dutt - Univ. of California, Irvine, CA
<br>
Joerg Henkel - NEC Labs., Princeton, NJ
</i><p>
<dl>
<dt>
<a href="iccadabs.htm#06b_1"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/06b_1.pdf"><img src="../../../../../icons/pdficon.gif"></a>
6B.1 Embedded Tutorial: System Level Design and Verification using a Synchronous
Language [p. 433]
<dd><i>
Gérard Berry, Michael Kishinevshy, Satnam Singh
</i><p>
</dl>
<hr>
<h2>Session 6C: <a href="iccadabs.htm#sess6c" NAME="sess6c">
Nonlinear Modelling of Analog and Optical Systems
</a></h2>
<i>
Moderators: Jaijeet Roychowdhury - Univ. of Minnesota, Minneapolis, MN
<br>
Mustafa Celik - Magma Design Automation, Cupertino, CA
</i><p>
<dl>
<dt>
<a href="iccadabs.htm#06c_1"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/06c_1.pdf"><img src="../../../../../icons/pdficon.gif"></a>
6C.1 Noise Analysis for Optical Fiber Communication Systems [p. 441]
<dd><i>
Alper Demir
</i><p>
<dt>
<a href="iccadabs.htm#06c_2"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/06c_2.pdf"><img src="../../../../../icons/pdficon.gif"></a>
6C.2 Analog Macromodeling using Kernel Methods [p. 446]
<dd><i>
Joel R. Phillips, João Pedro Afonso, Arlindo Oliveira, L. Miguel Silveira
</i><p>
<dt>
<a href="iccadabs.htm#06c_3"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/06c_3.pdf"><img src="../../../../../icons/pdficon.gif"></a>
6C.3 A Hybrid Approach to Nonlinear Macromodel Generation for Time-Varying Analog
Circuits [p. 454]
<dd><i>
Peng Li, Xin Li, Yang Xu, Lawrence T. Pileggi
</i><p>
</dl>
<hr>
<h2>Session 6D: <a href="iccadabs.htm#sess6d" NAME="sess6d">
Timing and Tradeoffs in Placement
</a></h2>
<i>
Moderators: Igor L. Markov - Univ. of Michigan, Ann Arbor, MI
<br>
Rajeev Jayaraman - Xilinx Inc., San Jose, CA
</i><p>
<dl>
<dt>
<a href="iccadabs.htm#06d_1"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/06d_1.pdf"><img src="../../../../../icons/pdficon.gif"></a>
6D.1 Incremental Placement for Timing Optimization [p. 463]
<dd><i>
Wonjoon Choi, Kia Bazargan
</i><p>
<dt>
<a href="iccadabs.htm#06d_2"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/06d_2.pdf"><img src="../../../../../icons/pdficon.gif"></a>
6D.2 A Trade-off Oriented Placement Tool [p. 467]
<dd><i>
Huaiyu Xu, Maogang Wang, Bo-Kyung Choi, Majid Sarrafzadeh
</i><p>
<dt>
<a href="iccadabs.htm#06d_3"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/06d_3.pdf"><img src="../../../../../icons/pdficon.gif"></a>
6D.3 Optimality and Stability Study of Timing-Driven Placement Algorithms [p. 472]
<dd><i>
Jason Cong, Michail Romesis, Min Xie
</i><p>
</dl>
<hr>
<h2>Session 7A: <a href="iccadabs.htm#sess7a" NAME="sess7a">
Simulation at the Nanometer Scale
</a></h2>
<i>
Moderators: Kenneth Kundert - Cadence Design Systems, Inc, San Jose, CA
<br>
Narayan Aluru - Univ. of Illinois, Urbana, IL
</i><p>
<dl>
<dt>
<a href="iccadabs.htm#07a_1"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/07a_1.pdf"><img src="../../../../../icons/pdficon.gif"></a>
7A.1 A Probabilistic-Based Design Methodology for Nanoscale Computation [p. 480]
<dd><i>
R. Iris Bahar, Joseph Mundy, Jie Chen
</i><p>
<dt>
<a href="iccadabs.htm#07a_2"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/07a_2.pdf"><img src="../../../../../icons/pdficon.gif"></a>
7A.2 Modeling of Ballistic Carbon Nanotube Field Effect Transistors for Efficient Circuit
Simulation [p. 487]
<dd><i>
Arijit Raychowdhury, Saibal Mukhopadhyay, Kaushik Roy
</i><p>
<dt>
<a href="iccadabs.htm#07a_3"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/07a_3.pdf"><img src="../../../../../icons/pdficon.gif"></a>
7A.3 Circuit Simulation of Nanotechnology Devices with Non-Monotonic I-V
Characteristics [p. 491]
<dd><i>
Jiayong Le, Lawrence T. Pileggi, Anirudh Devgan
</i><p>
<dt>
<a href="iccadabs.htm#07a_4"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/07a_4.pdf"><img src="../../../../../icons/pdficon.gif"></a>
7A.4 A CAD Framework for Co-Design and Analysis of CMOS-SET Hybrid Integrated
Circuits [p. 497]
<dd><i>
Santanu Mahapatra, Kaustav Banerjee, Florent Pegeon, Adrian M. Ionescu
</i><p>
</dl>
<hr>
<h2>Session 7B: <a href="iccadabs.htm#sess7b" NAME="sess7b">
Energy Issues in Systems Design
</a></h2>
<i>
Moderators: Wolfgang Nebel - Oldenburg Univ. and OFFIS, Oldenburg, Germany
<br>
Marcello Lajolo - NEC Labs., Princeton, NJ
</i><p>
<dl>
<dt>
<a href="iccadabs.htm#07b_1"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/07b_1.pdf"><img src="../../../../../icons/pdficon.gif"></a>
7B.1 A Game Theoretic Approach to Dynamic Energy Minimization in Wireless
Transceivers [p. 504]
<dd><i>
Ali Iranli, Hanif Fatemi, Massoud Pedram
</i><p>
<dt>
<a href="iccadabs.htm#07b_2"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/07b_2.pdf"><img src="../../../../../icons/pdficon.gif"></a>
7B.2 Communication-Aware Task Scheduling and Voltage Selection for Total Systems
Energy Minimization [p. 510]
<dd><i>
Girish V. Varatkar, Radu Marculescu
</i><p>
<dt>
<a href="iccadabs.htm#07b_3"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/07b_3.pdf"><img src="../../../../../icons/pdficon.gif"></a>
7B.3 LRU-SEQ: A Novel Replacement Policy for Transition Energy Reduction in
Instruction Caches [p. 518]
<dd><i>
Praveen G. Kalla, Xiaobo Sharon Hu, Joerg Henkel
</i><p>
<dt>
<a href="iccadabs.htm#07b_4"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/07b_4.pdf"><img src="../../../../../icons/pdficon.gif"></a>
7B.4 Compiler-Based Register Name Adjustment for Low-Power Embedded Processors [p. 523]
<dd><i>
Peter Petrov, Alex Orailoglu
</i><p>
</dl>
<hr>
<h2>Session 7C: <a href="iccadabs.htm#sess7c" NAME="sess7c">
Constraint Driven High-Level Synthesis
</a></h2>
<i>
Moderators: Michael Kishinevsky - Intel Corp., Hillsboro, OR
<br>
Barry Pangrle - Synopsys, Inc., Mountain View, CA
</i><p>
<dl>
<dt>
<a href="iccadabs.htm#07c_1"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/07c_1.pdf"><img src="../../../../../icons/pdficon.gif"></a>
7C.1 Gradual Relaxation Techniques with Applications to Behavioral Synthesis [p. 529]
<dd><i>
Zhiru Zhang, Yiping Fan, Miodrag Potkonjak, Jason Cong
</i><p>
<dt>
<a href="iccadabs.htm#07c_2"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/07c_2.pdf"><img src="../../../../../icons/pdficon.gif"></a>
7C.2 Architectural Synthesis Integrated with Global Placement for Multi-Cycle
Communication [p. 536]
<dd><i>
Jason Cong, Yiping Fan, Guoling Han, Xun Yang, Zhiru Zhang
</i><p>
<dt>
<a href="iccadabs.htm#07c_3"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/07c_3.pdf"><img src="../../../../../icons/pdficon.gif"></a>
7C.3 Binding, Allocation and Floorplanning in Low Power High-Level Synthesis [p. 544]
<dd><i>
Ansgar Stammermann, Domenik Helms, Milan Schulte, Arne Schulz, Wolfgang
Nebel
</i><p>
<dt>
<a href="iccadabs.htm#07c_4"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/07c_4.pdf"><img src="../../../../../icons/pdficon.gif"></a>
7C.4 A High-Level Interconnect Power Model for Design Space Exploration [p. 551]
<dd><i>
Pallav Gupta, Lin Zhong, Niraj K. Jha
</i><p>
</dl>
<hr>
<h2>Session 7D: <a href="iccadabs.htm#sess7d" NAME="sess7d">
Optimal Interconnect Synthesis and Analysis
</a></h2>
<i>
Moderators: Leon Stok - IBM Corp., Yorktown Heights, NY
<br>
John P. Fishburn - Consultant, Murray Hill, NJ
</i><p>
<dl>
<dt>
<a href="iccadabs.htm#07d_1"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/07d_1.pdf"><img src="../../../../../icons/pdficon.gif"></a>
7D.1 A Probabilistic Approach to Buffer Insertion [p. 560]
<dd><i>
Vishal Khandelwal, Azadeh Davoodi, Akash Nanavati, Ankur Srivastava
</i><p>
<dt>
<a href="iccadabs.htm#07d_2"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/07d_2.pdf"><img src="../../../../../icons/pdficon.gif"></a>
7D.2 Simultaneous Analytic Area and Power Optimization for Repeater Insertion [p. 568]
<dd><i>
Giuseppe S. Garcea, Nick P. van der Meijs, Ralph H. J. M. Otten
</i><p>
<dt>
<a href="iccadabs.htm#07d_3"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/07d_3.pdf"><img src="../../../../../icons/pdficon.gif"></a>
7D.3 Full-Chip Interconnect Power Estimation and Simulation Considering Concurrent
Repeater and Flip-Flop Insertion [p. 574]
<dd><i>
Weiping Liao, Lei He
</i><p>
<dt>
<a href="iccadabs.htm#07d_4"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/07d_4.pdf"><img src="../../../../../icons/pdficon.gif"></a>
7D.4 Power-Optimal Simultaneous Buffer Insertion/Sizing and Wire Sizing [p. 581]
<dd><i>
Ruiming Li, Dian Zhou, Jin Liu, Xuan Zeng
</i><p>
</dl>
<hr>
<h2>Session 8A: <a href="iccadabs.htm#sess8a" NAME="sess8a">
Memory Testing
</a></h2>
<i>
Moderators: Yervant Zorian - Virage Logic, Fremont, CA
<br>
Adit Singh - Auburn Univ., Montgomery, AL
</i><p>
<dl>
<dt>
<a href="iccadabs.htm#08a_1"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/08a_1.pdf"><img src="../../../../../icons/pdficon.gif"></a>
8A.1 Dynamic Data-bit Memory Built-In Self-Repair [p. 588]
<dd><i>
Michael Nicolaidis, Nadir Achouri, Slimane Boutobza
</i><p>
<dt>
<a href="iccadabs.htm#08a_2"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/08a_2.pdf"><img src="../../../../../icons/pdficon.gif"></a>
8A.2 FAME: A Fault-Pattern Based Memory Failure Analysis Framework [p. 595]
<dd><i>
Kuo-Liang Cheng, Chih-Wea Wang, Jih-Nung Lee, Yung-Fa Chou, Chih-Tsun
Huang, Cheng-Wen Wu
</i><p>
<dt>
<a href="iccadabs.htm#08a_3"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/08a_3.pdf"><img src="../../../../../icons/pdficon.gif"></a>
8A.3 Hardware/Software Co-Testing of Embedded Memories in Complex SoCs [p. 599]
<dd><i>
Bai Hong Fang, Qiang Xu, Nicola Nicolici
</i><p>
</dl>
<hr>
<h2>Session 8B: <a href="iccadabs.htm#sess8b" NAME="sess8b">
Statistical Static Timing - I
</a></h2>
<i>
Moderators: Louis Scheffer - Cadence Design Systems, Inc., San Jose, CA
<br>
Duncan M. (Hank) Walker - Texas A&M Univ., College Station, TX
</i><p>
<dl>
<dt>
<a href="iccadabs.htm#08b_1"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/08b_1.pdf"><img src="../../../../../icons/pdficon.gif"></a>
8B.1 Block-Based Static Timing Analysis with Uncertainty [p. 607]
<dd><i>
Anirudh Devgan, Chandramouli Kashyap
</i><p>
<dt>
<a href="iccadabs.htm#08b_2"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/08b_2.pdf"><img src="../../../../../icons/pdficon.gif"></a>
8B.2 τAU: Timing Analysis Under Uncertainty [p. 615]
<dd><i>
Sarvesh Bhardwaj, Sarma B. Vrudhula, David Blaauw
</i><p>
<dt>
<a href="iccadabs.htm#08b_3"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/08b_3.pdf"><img src="../../../../../icons/pdficon.gif"></a>
8B.3 Statistical Timing Analysis Considering Spatial Correlations Using a Single PERTlike
Traversal [p. 621]
<dd><i>
Hongliang Chang, Sachin S. Sapatnekar
</i><p>
</dl>
<hr>
<h2>Session 8C: <a href="iccadabs.htm#sess8c" NAME="sess8c">
Power-Aware Design
</a></h2>
<i>
Moderators: Tanay Karnik - Intel Corp., Hillsboro, OR
<br>
Bora Nikolic - Univ. of California, Berkeley, CA
</i><p>
<dl>
<dt>
<a href="iccadabs.htm#08c_1"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/08c_1.pdf"><img src="../../../../../icons/pdficon.gif"></a>
8C.1 Leakage Power Optimization Techniques for Ultra Deep Sub-Micron Multi-Level
Caches [p. 627]
<dd><i>
Nam S. Kim, David Blaauw, Trevor N. Mudge
</i><p>
<dt>
<a href="iccadabs.htm#08c_2"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/08c_2.pdf"><img src="../../../../../icons/pdficon.gif"></a>
8C.2 Dynamic Fault-Tolerance and Metrics for Battery Powered, Failure-Prone Systems [p. 633]
<dd><i>
Phillip Stanley-Marbell, Diana Marculescu
</i><p>
<dt>
<a href="iccadabs.htm#08c_3"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/08c_3.pdf"><img src="../../../../../icons/pdficon.gif"></a>
8C.3 Dynamic Platform Management for Configurable Platform-Based System-on-Chips [p. 641]
<dd><i>
Krishna Sekar, Kanishka Lahiri, Sujit Dey
</i><p>
</dl>
<hr>
<h2>Session 8D: <a href="iccadabs.htm#sess8d" NAME="sess8d">
Interconnect Reduction
</a></h2>
<i>
Moderators: Chung-Kuan Cheng - Univ. of California at San Diego, La Jolla, CA
<br>
Eli Chiprout - Intel Corp., Chandler, AZ
</i><p>
<dl>
<dt>
<a href="iccadabs.htm#08d_1"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/08d_1.pdf"><img src="../../../../../icons/pdficon.gif"></a>
8D.1 A General s-Domain Hierarchical Network Reduction Algorithm [p. 650]
<dd><i>
Sheldon X.-D. Tan
</i><p>
<dt>
<a href="iccadabs.htm#08d_2"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/08d_2.pdf"><img src="../../../../../icons/pdficon.gif"></a>
8D.2 Branch Merge Reduction of RLCM Networks [p. 658]
<dd><i>
Bernard N. Sheehan
</i><p>
<dt>
<a href="iccadabs.htm#08d_3"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/08d_3.pdf"><img src="../../../../../icons/pdficon.gif"></a>
8D.3 A Sum-Over-Paths Impulse-Response Moment-Extraction Algorithm for IC Interconnect
Networks: Verification, Coupled RC Lines [p. 665]
<dd><i>
Yannick L. Le Coz, Dhivya Krishna, Dusan M. Petranovic, William M. Loh,
Peter Bendix
</i><p>
</dl>
<hr>
<h2>Session 9A: <a href="iccadabs.htm#sess9a" NAME="sess9a">
Embedded Tutorial: Mixed Signal DFT: A Concise Overview
</a></h2>
<i>
Moderators: Erik Larsson - Linköping Univ., Linköping, Sweden
<br>
Sule Ozev - Duke Univ., Durham, NC
</i><p>
<dl>
<dt>
<a href="iccadabs.htm#09a_1"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/09a_1.pdf"><img src="../../../../../icons/pdficon.gif"></a>
9A.1 Embedded Tutorial: Mixed Signal DFT: A Concise Overview [p. 672]
<dd><i>
Bozena Kaminska, Karim Arabi
</i><p>
</dl>
<hr>
<h2>Session 9B: <a href="iccadabs.htm#sess9b" NAME="sess9b">
Embedded Tutorial: Manufacturing-Aware Physical Design
</a></h2>
<i>
Moderators: Sani R. Nassif - IBM Corp., Austin, TX
<br>
Sachin S. Sapatnekar - Univ. of Minnesota, Minneapolis, MN
</i><p>
<dl>
<dt>
<a href="iccadabs.htm#09b_1"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/09b_1.pdf"><img src="../../../../../icons/pdficon.gif"></a>
9B.1 Embedded Tutorial: Manufacturing-Aware Physical Design [p. 681]
<dd><i>
Andrew B. Kahng, Puneet Gupta
</i><p>
</dl>
<hr>
<h2>Session 9C: <a href="iccadabs.htm#sess9c" NAME="sess9c">
Cool Topics in Logic Synthesis
</a></h2>
<i>
Moderators: Olivier R. Coudert - Monterey Design Systems, Inc., Sunnyvale, CA
<br>
Diana Marculescu - Carnegie Mellon Univ., Pittsburgh, PA
</i><p>
<dl>
<dt>
<a href="iccadabs.htm#09c_1"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/09c_1.pdf"><img src="../../../../../icons/pdficon.gif"></a>
9C.1 A Heuristic to Determine Low Leakage Sleep State Vectors for CMOS Combinational
Circuits [p. 689]
<dd><i>
Rahul M. Rao, Frank Liu, Jeffrey L. Burns, Richard B. Brown
</i><p>
<dt>
<a href="iccadabs.htm#09c_2"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/09c_2.pdf"><img src="../../../../../icons/pdficon.gif"></a>
9C.2 Algorithm for Achieving Minimum Energy Consumption in CMOS Circuits Using
Multiple Supply and Threshold Voltages at the Module Level [p. 693]
<dd><i>
Yuvraj S. Dhillon, Abdulkadir U. Diril, Abhijit Chatterjee, Hsien-Hsin S. Lee
</i><p>
<dt>
<a href="iccadabs.htm#09c_3"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/09c_3.pdf"><img src="../../../../../icons/pdficon.gif"></a>
9C.3 On the Interaction between Power-Aware FPGA CAD Algorithms [p. 701]
<dd><i>
Julien Lamoureux, Steven J. E. Wilton
</i><p>
<dt>
<a href="../../pdffiles/09c_4.pdf" name="09c_4"><img src="../../../../../icons/pdficon.gif"></a>
9C.4 A Theory of Non-Deterministic Networks [p. 709]
<dd><i>
Alan Mishchenko, Robert K. Brayton
</i><p>
</dl>
<hr>
<h2>Session 9D: <a href="iccadabs.htm#sess9d" NAME="sess9d">
Graph Algorithmic Approaches to EDA Problems
</a></h2>
<i>
Moderators: Dwight D. Hill - Synopsys, Inc., Mountain View, CA
<br>
Igor L. Markov - Univ. of Michigan, Ann Arbor, MI
</i><p>
<dl>
<dt>
<a href="iccadabs.htm#09d_1"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/09d_1.pdf"><img src="../../../../../icons/pdficon.gif"></a>
9D.1 Stable Multiway Circuit Partitioning for ECO [p. 718]
<dd><i>
Yongseok Cheon, Seokjin Lee, Martin D. F. Wong
</i><p>
<dt>
<a href="iccadabs.htm#09d_2"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/09d_2.pdf"><img src="../../../../../icons/pdficon.gif"></a>
9D.2 Multi-Objective Hypergraph Partitioning Algorithms for Cut and Maximum
Subdomain Degree Minimization [p. 726]
<dd><i>
Navaratnasothie Selvakkumaran, George Karypis
</i><p>
<dt>
<a href="iccadabs.htm#09d_3"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/09d_3.pdf"><img src="../../../../../icons/pdficon.gif"></a>
9D.3 An Algorithmic Approach for Generic Parallel Adders [p. 734]
<dd><i>
Jianhua Liu, Shuo Zhou, Haikun Zhu, Chung-Kuan Cheng
</i><p>
<dt>
<a href="iccadabs.htm#09d_4"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/09d_4.pdf"><img src="../../../../../icons/pdficon.gif"></a>
9D.4 FROSTY: A Fast Hierarchy Extractor for Industrial CMOS Circuits [p. 741]
<dd><i>
Lei Yang, C.-J. Richard Shi
</i><p>
</dl>
<hr>
<h2>Session 10A: <a href="iccadabs.htm#sess10a" NAME="sess10a">
Parametric Considerations in Test Schemes
</a></h2>
<i>
Moderators: Andre Ivanov - Univ. of British Columbia, Vancouver, Canada
<br>
Kwang-Ting (Tim) Cheng - Univ. of California, Santa Barbara, CA
</i><p>
<dl>
<dt>
<a href="iccadabs.htm#10a_1"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/10a_1.pdf"><img src="../../../../../icons/pdficon.gif"></a>
10A.1 Path Delay Estimation using Power Supply Transient Signals: A Comparative Study
using Fourier and Wavelet Analysis [p. 748]
<dd><i>
Abhishek Singh, Jitin Tharian, Jim Plusquellic
</i><p>
<dt>
<a href="iccadabs.htm#10a_2"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/10a_2.pdf"><img src="../../../../../icons/pdficon.gif"></a>
10A.2 Layout-Aware Scan Chain Synthesis for Improved Path Delay Fault Coverage [p. 754]
<dd><i>
Puneet Gupta, Andrew B. Kahng, Ion I. Mandoiu, Puneet Sharma
</i><p>
<dt>
<a href="iccadabs.htm#10a_3"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/10a_3.pdf"><img src="../../../../../icons/pdficon.gif"></a>
10A.3 Static Verification of Test Vectors for IR Drop Failure [p. 760]
<dd><i>
Aman A. Kokrady, C. P. Ravikumar
</i><p>
<dt>
<a href="iccadabs.htm#10a_4"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/10a_4.pdf"><img src="../../../../../icons/pdficon.gif"></a>
10A.4 ATPG for Noise-Induced Switch Failures in Domino Logic [p. 765]
<dd><i>
Rahul Kundu, Ronald D. (Shawn) Blanton
</i><p>
</dl>
<hr>
<h2>Session 10B: <a href="iccadabs.htm#sess10b" NAME="sess10b">
Power-Grid and Substrate Analysis
</a></h2>
<i>
Moderators: Kenneth L. Shepard - Columbia Univ., New York, NY
<br>
David Blaauw - Univ. of Michigan, Ann Arbor, MI
</i><p>
<dl>
<dt>
<a href="iccadabs.htm#10b_1"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/10b_1.pdf"><img src="../../../../../icons/pdficon.gif"></a>
10B.1 Statistical Verification of Power Grids Considering Process-Induced Leakage Current
Variations [p. 770]
<dd><i>
Imad A. Ferzli, Farid N. Najm
</i><p>
<dt>
<a href="iccadabs.htm#10b_2"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/10b_2.pdf"><img src="../../../../../icons/pdficon.gif"></a>
10B.2 A Methodology for the Computation of an Upper Bound on Noise Current Spectrum
of CMOS Switching Activity [p. 778]
<dd><i>
Alessandra Nardi, Haibo Zeng, Joshua L. Garrett, Luca Daniel, Alberto L.
Sangiovanni-Vincentelli
</i><p>
<dt>
<a href="iccadabs.htm#10b_3"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/10b_3.pdf"><img src="../../../../../icons/pdficon.gif"></a>
10B.3 SuPREME: Substrate and Power-delivery Reluctance-Enhanced Macromodel
Evaluation [p. 786]
<dd><i>
Tsung Hao Chen, Clement Luk, Charlie Chung-Ping Chen
</i><p>
<dt>
<a href="iccadabs.htm#10b_4"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/10b_4.pdf"><img src="../../../../../icons/pdficon.gif"></a>
10B.4 SILCA: Fast-Yet-Accurate Time-Domain Simulation of VLSI Circuits with Strong
Parasitic Coupling Effects [p. 793]
<dd><i>
Zhao Li, C.-J. Richard Shi
</i><p>
</dl>
<hr>
<h2>Session 10C: <a href="iccadabs.htm#sess10c" NAME="sess10c">
Hot Topics in Logic Synthesis
</a></h2>
<i>
Moderators: Michel Berkelaar - Magma Design Automation, Eindhoven, The Netherlands
<br>
Yusuke Matsunaga - Kyushu Univ., Fukuoka, Japan
</i><p>
<dl>
<dt>
<a href="iccadabs.htm#10c_1"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/10c_1.pdf"><img src="../../../../../icons/pdficon.gif"></a>
10C.1 Multi-Domain Clock Skew Scheduling [p. 801]
<dd><i>
Kaushik Ravindran, Andreas Kuehlmann, Ellen M. Sentovich
</i><p>
<dt>
<a href="iccadabs.htm#10c_2"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/10c_2.pdf"><img src="../../../../../icons/pdficon.gif"></a>
10C.2 Clock Period Minimization of Non-Zero Clock Skew Circuits [p. 809]
<dd><i>
Shih-Hsu Huang, Yow-Tyng Nieh
</i><p>
<dt>
<a href="iccadabs.htm#10c_3"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/10c_3.pdf"><img src="../../../../../icons/pdficon.gif"></a>
10C.3 Minimum-Area Sequential Budgeting for FPGA [p. 813]
<dd><i>
Chao-Yang Yeh, Malgorzata Marek-Sadowska
</i><p>
<dt>
<a href="iccadabs.htm#10c_4"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/10c_4.pdf"><img src="../../../../../icons/pdficon.gif"></a>
10C.4 ILP Models for the Synthesis of Asynchronous Control Circuits [p. 818]
<dd><i>
Josep Carmona, Jordi Cortadella
</i><p>
</dl>
<hr>
<h2>Session 10D: <a href="iccadabs.htm#sess10d" NAME="sess10d">
Interconnect Modeling
</a></h2>
<i>
Moderators: Nick van der Meijs - Delft Univ. of Tech., Delft, The Netherlands
<br>
Sharad Kapur - Integrand Software, Hoboken, NJ
</i><p>
<dl>
<dt>
<a href="iccadabs.htm#10d_1"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/10d_1.pdf"><img src="../../../../../icons/pdficon.gif"></a>
10D.1 Passive Synthesis of Compact Frequency-Dependent Interconnect Models via
Quadrature Spectral Rules [p. 827]
<dd><i>
Traianos Yioultsis, Anne Woo, Andreas C. Cangellaris
</i><p>
<dt>
<a href="iccadabs.htm#10d_2"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/10d_2.pdf"><img src="../../../../../icons/pdficon.gif"></a>
10D.2 Analytic Modeling of Interconnects for Deep Sub-Micron Circuits [p. 835]
<dd><i>
Dinesh Pamunuwa, Shauki Elassaad, Hannu Tenhunen
</i><p>
<dt>
<a href="iccadabs.htm#10d_3"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/10d_3.pdf"><img src="../../../../../icons/pdficon.gif"></a>
10D.3 A New Surface Integral Formulation for Wideband Impedance Extraction of 3-D
Structures [p. 843]
<dd><i>
Ben Song, Zhenhai Z. Zhu, John D. Rockway, Jacob K. White
</i><p>
<dt>
<a href="iccadabs.htm#10d_4"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/10d_4.pdf"><img src="../../../../../icons/pdficon.gif"></a>
10D.4 Switch-Factor Based Loop RLC Modeling for Efficient Timing Analysis [p. 848]
<dd><i>
Yu Cao, Xiao-dong Yang, Xuejue Huang, Dennis Sylvester
</i><p>
</dl>
<hr>
<h2>Session 11A: <a href="iccadabs.htm#sess11a" NAME="sess11a">
Test Data Reduction Techniques
</a></h2>
<i>
Moderators: Alex Orailoglu - Univ. of California at San Diego, La Jolla, CA
<br>
Vivek Chickermane - IBM Corp., Endicott, NY
</i><p>
<dl>
<dt>
<a href="iccadabs.htm#11a_1"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/11a_1.pdf"><img src="../../../../../icons/pdficon.gif"></a>
11A.1 On Compacting Test Response Data Containing Unknown Values [p. 855]
<dd><i>
Chen Wang, Sudhakar M. Reddy, Irith Pomeranz , Janusz Rajski, Jerzy Tyszer
</i><p>
<dt>
<a href="iccadabs.htm#11a_2"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/11a_2.pdf"><img src="../../../../../icons/pdficon.gif"></a>
11A.2 Adjustable Width Linear Combinational Scan Vector Decompression [p. 863]
<dd><i>
C. V. Krishna, Nur A. Touba
</i><p>
<dt>
<a href="iccadabs.htm#11a_3"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/11a_3.pdf"><img src="../../../../../icons/pdficon.gif"></a>
11A.3 On Application of Output Masking to Undetectable Faults in Synchronous Sequential
Circuits with Design-for-Testability Logic [p. 867]
<dd><i>
Irith Pomeranz, Sudhakar M. Reddy
</i><p>
</dl>
<hr>
<h2>Session 11B: <a href="iccadabs.htm#sess11b" NAME="sess11b">
Embedded Tutorial: Formal Methods for Dynamic Power Management
</a></h2>
<i>
Moderators: Giovanni De Micheli - Stanford Univ., Stanford CA
<br>
Massoud Pedram - Univ. of Southern California, Los Angeles, CA
</i><p>
<dl>
<dt>
<a href="iccadabs.htm#11b_1"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/11b_1.pdf"><img src="../../../../../icons/pdficon.gif"></a>
11B.1 Embedded Tutorial: Formal Methods for Dynamic Power Management [p. 874]
<dd><i>
Rajesh K. Gupta, Sandeep K. Shukla, Sandy Irani
</i><p>
</dl>
<hr>
<h2>Session 11C: <a href="iccadabs.htm#sess11c" NAME="sess11c">
Embedded Tutorial: Large-Scale Circuit Placement: Gap and Promise
</a></h2>
<i>
Moderators: William H. Joyner, Jr. - SRC, Research Triangle Park, NC
<br>
Yoji Kajitani - Univ. of Kitakyushu, Fukuoka, Japan
</i><p>
<dl>
<dt>
<a href="iccadabs.htm#11c_1"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/11c_1.pdf"><img src="../../../../../icons/pdficon.gif"></a>
11C.1 Embedded Tutorial: Large-Scale Circuit Placement: Gap and Promise [p. 883]
<dd><i>
Jason Cong, Tim Kong, Joseph R. Shinnerl, Min Xie, Xin Yuan
</i><p>
<dt>
<a href="iccadabs.htm#11c_2"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/11c_2.pdf"><img src="../../../../../icons/pdficon.gif"></a>
11C.2 Embedded Tutorial: Multi-Million Gate FPGA Physical Design Challenges [p. 891]
<dd><i>
Maogang Wang, Abhishek Ranjan, Salil Raje
</i><p>
</dl>
<hr>
<h2>Session 11D: <a href="iccadabs.htm#sess11d" NAME="sess11d">
Statistical Static Timing - II
</a></h2>
<i>
Moderators: Nagib Z. Hakim - Intel Corp., Santa Clara, CA
<br>
Sani R. Nassif - IBM Corp., Austin, TX
</i><p>
<dl>
<dt>
<a href="iccadabs.htm#11d_1"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/11d_1.pdf"><img src="../../../../../icons/pdficon.gif"></a>
11D.1 Statistical Timing Analysis for Intra-Die Process Variations with Spatial Correlations [p. 900]
<dd><i>
Aseem Agarwal, David Blaauw, Vladimir Zolotov
</i><p>
<dt>
<a href="iccadabs.htm#11d_2"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/11d_2.pdf"><img src="../../../../../icons/pdficon.gif"></a>
11D.2 A Statistical Gate-Delay Model Considering Intra-Gate Variability [p. 908]
<dd><i>
Kenichi Okada, Kento Yamaoka, Hidetoshi Onodera
</i><p>
<dt>
<a href="iccadabs.htm#11d_3"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/11d_3.pdf"><img src="../../../../../icons/pdficon.gif"></a>
11D.3 Statistical Clock Skew Analysis Considering Intra-Die Process Variation [p. 914]
<dd><i>
Aseem Agarwal, David Blaauw, Vladimir Zolotov
</i><p>
</dl>
]]>