| Title | Efficient Techniques for 3-D Impedance Extraction Using Mixed Boundary Element Method |
| Author | *Fang Gong, Wenjian Yu, Zeyi Wang (Dept. of Computer Science, Tsinghua University, China), Zhiping Yu (Institute of Microelectronics, Tsinghua University, China), Changhao Yan (Fudan University, China) |
| Page | pp. 158 - 163 |
| Keyword | parasitic extraction, preconditioner, surface integral formulation, wide-band analysis, mixed boundary element method |
| Abstract | In this paper, we describe the algorithms implemented in MBEM, a program for wideband impedance extraction of complicated 3-D structures. MBEM is based on a mixed boundary element method (BEM), which reduces the number of unknowns from about 7N in FastImp to 4N, for MQS analysis. Efficient techniques are proposed to handle the extra matrix multiplication, form post-process matrices, and solve the final linear equation system. The inaccuracy of calcu- lation using FastImp at low frequency is also analyzed, which shows the mixed BEM eliminates it completely. Experiments on several typical 3-D structures validate the advantage of MBEM over FastImp, on both accuracy and efficiency. |
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| Title | Generating Stable and Sparse Reluctance/Inductance Matrix under Insufficient Conditions |
| Author | *Yuichi Tanji (Kagawa University, Japan), Takayuki Watanabe (The University of Shizuoka, Japan), Hideki Asai (Shizuoka University, Japan) |
| Page | pp. 164 - 169 |
| Keyword | Sparse, Inductance, Reluctance, Extraction |
| Abstract | This paper presents generating stable and sparse
reluctance/inductance matrix from the inductance
matrix which is extracted under insufficient discretization.
So far, to generate the sparse reluctance matrix with
guaranteed stability, this matrix has to be diagonally
dominant M matrix. Hence, the repeated inductance extractions
are necessary using a smaller grid size, in order to
obtain the well-defined matrix. Alternatively, this paper
provides some ideas for generating the sparse reluctance
matrix, even if the extracted reluctance matrix is not
diagonally dominant M matrix, precisely, the positive
off-diagonal elements are even found.
This eases the extraction tasks greatly.
Furthermore, the sparse inductance matrix is also generated
by using the practical and sophisticated double inverse
methods, which is useful for the SPICE simulation,
since reluctance components are not still supported in
SPICE-like simulators. |
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| Title | Hierarchical Krylov Subspace Reduced Order Modeling of Large RLC Circuits |
| Author | Duo Li, *Sheldon X.-D. Tan (University of California, Riverside, United States) |
| Page | pp. 170 - 175 |
| Keyword | Model order reduction, interconnect |
| Abstract | In this paper, we propose a new model order reduction approach for large interconnect circuits using hierarchical decomposition and Krylov subspace projection-based model order reduction. The new approach, called hiePrimor, first partitions a large interconnect circuit into a number of smaller subcircuits and then performs the projection-based model order reduction on each of subcircuits in isolation and on the top level circuit thereafter. The new approach can exploit the parallel computing to speed up the reduction process. Theoretically we show hiePrimor can have the same accuracy as the flat reduction method given the same reduction order and it can also preserves the passivity of the reduced models as well. We also show that partitioning is important for hierarchical projection-based reduction and the minimum-span objective should be required to archive best performance for hierarchical reduction. The proposed method is suitable for reducing large global interconnects like coupled bus, transmission lines, large clock nets in the post layout stage. Experimental results demonstrate that hiePrimor can be
significantly faster than flat projection method like PRIMA and be order of magnitude faster than PRIMA with parallel computing without
loss of accuracy. |
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| Title | Statistical Noise Margin Estimation for Sub-Threshold Combinational Circuits |
| Author | *Yu Pu (Technische Universiteit Eindhoven, Netherlands), Jose Pineda de Gyvez (NXP Research Eindhoven, Netherlands), Henk Corporaal (Technische Universiteit Eindhoven, Netherlands), Yajun Ha (National University of Singapore, Singapore) |
| Page | pp. 176 - 179 |
| Keyword | subthreshold , reliability, noise margin |
| Abstract | The increasingly popular sub-threshold design is strongly calling for EDA support to estimate noise margins, minimum functional supply voltage, as well as the functional yield. In this paper, we propose a fast, accurate and statistical approach to accomplish these goals. First, we derive close-form functions based on a new equivalent resistance model which enables the fast estimation of noise margins of individual cells at the gate-level. Second, we propose to calculate and propagate the noise margin information with an affine arithmetic model that takes into account process variations and correspondent inter-cell correlations. Experiments with ISCAS benchmarks have shown that the new approach has an accuracy of 98.5% w.r.t. transistor-level Monte Carlo simulations. The running time per input vector of the new approach only needs a few seconds, in contrast to the many hours required by transistor-level DC Monte-Carlo simulations. To the best of our knowledge, we are the first to provide a fast, accurate and statistical methodology other than Monte-Carlo simulation for the noise margin estimation of sub-threshold combinational circuits. |
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