| Title | A 1.2GHz Delayed Clock Generator for High-speed Microprocessors |
| Author | *Inhwa Jung, Moo-Young Kim, Chulwoo Kim (Korea University, Republic of Korea) |
| Page | pp. 95 - 96 |
| Keyword | clock generator, clock-on-demand, lock time, low-power |
| Abstract | A 1.2GHz delayed clock generator capable of adjusting its clock phase according to input clock frequencies has been developed. It consists of a full-digital CMOS circuit that leads to a simple, robust, and portable IP. One-cycle lock time enables clock-on-demand circuit structures. The implemented delayed clock generator tile in 0.13um CMOS technology occupies only 0.004mm2 and operates at variable input frequencies ranging from 625MHz to 1.2GHz. |
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| Title | LVDS-Type On-Chip Transmision Line Interconnect with Passive Equalizers in 90 nm CMOS Process |
| Author | *Akiko Mineyama, Hiroyuki Ito, Takahiro Ishii, Kenichi Okada, Kazuya Masu (Tokyo Institute of Technology, Japan) |
| Page | pp. 97 - 98 |
| Keyword | transmision line , on-chip interconnect, global interconnect, LVDS-type, passive equalizer |
| Abstract | This paper demonstrates a low voltage differential signaling (LVDS)-type on-chip transmission line (TL) interconnect with passive equalizers to solve delay issues on global interconnects. The proposed on-chip TL interconnect can achieve 10.5 Gbps signaling and has smaller delay, smaller delay variation and better power efficiency than conventional on-chip interconnects at high-frequencies. |
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| Title | A Slew-Rate Controlled Output Driver with One-Cycle Tuning Time |
| Author | *Young-Ho Kwak, Inhwa Jung, Chulwoo Kim (Korea University, Republic of Korea) |
| Page | pp. 99 - 100 |
| Keyword | slew-rate, one-cycle, low power, 0.18um |
| Abstract | A low-power slew-rate controlled output driver with open loop digital
scheme, one-cycle lock time is presented. Proposed output driver maintains slew rate in the range of 2.1V/ns to 3.6V/ns in a one cycle after the enable clock is inserted. It is implemented in 0.18um CMOS process, and the control block consumes 13.7mW at 1Gbps. |
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| Title | A Low-Leakage Current Power 180-nm CMOS SRAM |
| Author | *Tadayoshi Enomoto, Yuki Higuchi (Chuo University, Japan) |
| Page | pp. 101 - 102 |
| Keyword | SRAM, leakage, power, CMOS |
| Abstract | A low leakage power, 180-nm 1K-b SRAM was fabricated. The stand-by leakage power of a 1K-bit memory cell array incorporating a newly developed leakage current reduction circuit called a “self-controllable voltage level (SVL)” circuit was only 3.7 nW, 5.4% of that of an equivalent conventional memory-cell array at VDD of 1.8 V. On the other hand, the speed remained almost constant with a minimal overhead in terms of the memory cell array area. |
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| Title | A CMOS Direct Sampling Mixer Using Switched Capacitor Filter Technique for Software-Defined Radio |
| Author | *Hong Phuc Ninh, Takashi Moue, Takashi Kurashina, Kenichi Okada, Akira Matsuzawa (Tokyo Institute of Technology, Japan) |
| Page | pp. 103 - 104 |
| Keyword | Sampling Mixer, Switched Capacitor Filter, Software-Defined Radio |
| Abstract | This paper proposes a novel direct sampling mixer (DSM) using Switched Capacitor Filter (SCF) for multi-band receivers. The proposed DSM has a higher gain, more flexibility and lower flicker noise than that of conventional circuits. The mixer for Digital Terrestrial Television (ISDB-T) 1-segment was fabricated in a 0.18um CMOS process, and measured results are presented for a sampling frequency of 800MHz. The experimental results exhibit 430kHz signal bandwith with 27.3dB attenuation of adjacent interferer assuming at 3MHz offset. |
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| Title | Small-Area CMOS RF Distributed Mixer Using Multi-Port Inductors |
| Author | *Susumu Sadoshima, Satoshi Fukuda, Tackya Yammouch, Hiroyuki Ito, Kenichi Okada, Kazuya Masu (Tokyo Institute of Technology, Japan) |
| Page | pp. 105 - 106 |
| Keyword | mixer, cmos, uwb |
| Abstract | This paper presents a novel small-area distributed mixer for ultrawide-band (UWB) receivers.The proposed mixer uses five 4-port inductors instead of fifteen 2-port inductors to shrink area of the circuit.The proposed mixer achieves conversion gain of -10dB, noise figure of 15dB, return loss of less than -10dB from 2.3 to 6.0GHz, IIP3 of 13.6dBm, and the circuit area of 0.51mm^2. |
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| Title | Duo-Binary Circular Turbo Decoder Based on Border Metric Encoding for WiMAX |
| Author | *Ji-Hoon Kim, In-Cheol Park (KAIST, Republic of Korea) |
| Page | pp. 109 - 110 |
| Keyword | turbo code, turbo decoder, duo-binary SISO decoding, WiMAX, interleaver |
| Abstract | This paper presents a duo-binary circular turbo decoder based on border metric encoding. With the proposed method, the memory size for branch memory is reduced by half and the dummy calculation is removed at the cost of the small-sized memory which holds the encoded border metrics. Based on the proposed SISO decoder and the dedicated hardware interleaver, a duo-binary circular turbo decoder is designed for the WiMAX standard using a 0.13 um CMOS process, which can support 24.26Mbps at 200MHz. |
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| Title | Area and Power Efficient Design of Coarse Time Synchronizer and Frequency Offset Estimator for Fixed WiMAX System |
| Author | *Tae-Hwan Kim, In-Cheol Park (KAIST, Republic of Korea) |
| Page | pp. 111 - 112 |
| Keyword | OFDM, WiMAX, IEEE 802.16d, coarse time synchronization, carrier frequency offset estimation |
| Abstract | Targeting fixed WiMAX systems, this paper presents
a new architecture for coarse time synchronization and carrier
frequency offset (CFO) estimation. The proposed architecture
is based on a two-step approach where the data-paths are
decoupled to individually optimize performance and area.
Implemented with 0.13um CMOS technology, the results show
that the proposed architecture has advantages of less silicon
area and power consumption as well as better performance
compared to the previous joint approach. |
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| Title | A Low-Cost Cryptographic Processor for Security Embedded System |
| Author | *Ronghua Lu, Jun Han, Xiaoyang Zeng, Qing Li, Lang Mai, Jia Zhao (Fudan Univ., China) |
| Page | pp. 113 - 114 |
| Keyword | Security, Processor, Cryptographic, RSA, AES |
| Abstract | A low-cost cryptographic processor for security embedded system is presented in this paper. The processor, without any assistance of dedicated cryptographic coprocessors, is scalable and very efficient for popular cryptographic functions such as RSA/ECC, AES, Hash, etc. Based on SMIC 0.18um standard CMOS technology, the core circuit of the test chip has only about 32k gates, and a max frequency of 200MHz, under which the 1024-bit RSA algorithm takes only 150ms and the throughout of AES reaches 256Mbits/s. |
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| Title | Parameterized Embedded In-circuit Emulator and Its Retargetable Debugging Software for Microprocessor/Microcontroller/DSP Processor |
| Author | *Liang-Bi Chen, Yung-Chih Liu, Chien-Hung Chen, Chung-Fu Kao, Ing-Jer Huang (Department of Computer Science and Engineering National Sun Yat-Sen University, Taiwan) |
| Page | pp. 117 - 118 |
| Keyword | In-circuit Emulation, In-circuit Emulator, Testing, Debugging, Mircoprocessor |
| Abstract | The in-circuit emulator (ICE) is commonly adopted as a microprocessor debugging technique. In this paper, a parameterized embedded in-circuit emulator and its retargetable debugging software are proposed. The parameterized embedded in-circuit emulator can be integrated into different style processors such as microcontroller, microprocessor, and DSP processor. The GUI interface Debugging software can help user to debug easily. As a result of it, the duration of microprocessor debugging design procedure time is reduced. |
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