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The 11th Asia and South Pacific Design Automation Conference
Technical Program

Remark: The presenter of each paper is marked with "*".
Technical Program:   SIMPLE version   DETAILED version with abstract    One Page (Not Separated) version
Author Index:   HERE

Session Schedule


Wednesday January 25, 2006

ABCD
Op (Small Auditorium, 5F)
Opening Session
8:30 - 9:00
1K (Small Auditorium, 5F)
Keynote Address I
9:00 - 10:00
1A (Room 411+412)
Formal Methods for Coverage and Scalable Verification
10:15 - 12:20
1B (Room 413)
Interconnect for High-End SoC
10:15 - 12:20
1C (Room 414+415)
Timing Analysis and Optimization
10:15 - 12:20
1D (Room 416+417)
University Design Contest
10:15 - 12:20
2A (Room 411+412)
Software Techniques for Efficient SoC Design
13:30 - 15:35
2B (Room 413)
Application Examples with Leading Edge Design Methodology
13:30 - 15:35
2C (Room 414+415)
Placement
13:30 - 15:35
2D (Room 416+417)
Special Session: Electrothermal Design of Nanoscale Integrated Circuits
13:30 - 15:35
3A (Room 411+412)
Logic Synthesis
16:00 - 18:05
3B (Room 413)
Future Technical Directions for Design Automation
16:00 - 18:05
3C (Room 414+415)
Routing and Interconnect Optimization
16:00 - 18:05
3D (Room 416+417)
Special Session: Flash Memory in Embedded Systems
16:00 - 18:05


Thursday January 26, 2006

ABCD
2K (Small Auditorium, 5F)
Keynote Address II
9:00 - 10:00
4A (Room 411+412)
Resolving Timing Issues: Design and Test
10:15 - 12:20
4B (Room 413)
Leading Edge Design Methodology for SoCs and SiPs
10:15 - 12:20
4C (Room 414+415)
Advanced Circuit Simulation
10:15 - 12:20
4D (Room 416+417)
Special Session: Open Access Overview
10:15 - 12:20
5A (Room 411+412)
Advances in Simulation Technologies
13:30 - 15:35
5B (Room 413)
Scheduling for Embedded Systems
13:30 - 15:35
5C (Room 414+415)
High Frequency Interconnect Effects in Nanometer Technology
13:30 - 15:35
5D (Small Auditorium, 5F)
Designers' Forum: Low Power Design
13:30 - 15:30
6A (Room 411+412)
Power Optimization of Large-Scale Circuits
16:00 - 18:05
6B (Room 413)
Advanced Memory and Processor Architectures for MPSoC
16:00 - 18:05
6C (Room 414+415)
New Routing Techniques
16:00 - 18:05


Friday January 27, 2006

ABCD
3K (Small Auditorium, 5F)
Keynote Address III
9:00 - 10:00
7A (Room 411+412)
Minimization of Test Cost and Power
10:15 - 12:20
7B (Room 413)
Substrate Coupling and Analog Synthesis
10:15 - 12:20
7C (Room 414+415)
Statistical and Yield Analysis
10:15 - 12:20
7D (Room 416+417)
Special Session: H.264/AVC Design Challenges and Solutions
10:15 - 12:20
8A (Room 411+412)
Floorplanning
13:30 - 15:35
8B (Room 413)
Memory Optimization for Embedded Systems
13:30 - 15:35
8C (Room 414+415)
Inductive Issues in Power Grids and Packages
13:30 - 15:35
8D (Small Auditorium, 5F)
Designers' Forum: "Cell" Processor
13:30 - 15:30
9A (Room 411+412)
High-Level Synthesis
16:00 - 18:05
9B (Room 413)
Modeling, Compilation and Optimization of Embedded Architectures
16:00 - 18:05
9C (Room 414+415)
Statistical Design
16:00 - 18:05