| Title | Fast Substrate Noise-Aware Floorplanning with Preference Directed Graph for Mixed-Signal SOCs |
| Author | *Minsik Cho, Hongjoong Shin, David Z. Pan (University of Texas at Austin, United States) |
| Page | pp. 765 - 770 |
| Keyword | Floorplanning, substrate noise, mixed-signal |
| Abstract | In this paper, we introduce a novel substrate noise estimation technique during early floorplanning, based on the concept of Block Preference Directed Graph (BPDG) and the classic Sequence Pair (SP) floorplan representation. Given a set of analog and digital blocks, the BPDG is constructed based on their inherent noise characteristics
to capture their preferred relative orders for substrate noise minimization. For each sequence pair generated during floorplanning evaluation, we can measure its violation against BPDG very efficiently. We observe that by simply counting the number of violations obtained in this manner, it correlates remarkably well with accurate but computation-intensive substrate noise modeling. Thus, our BPDG-based model has high fidelity to guide the substrate noise-aware floorplanning and layout optimization, which become a growing concern for mixed-signal/RF system on chips (SOC). Our experimental results show that the proposed approach is over 60x faster than conventional floorplanning with even very compact substrate noise models. We also obtain less area and total substrate noise than the conventional approach. |
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| Title | A Multi-Technology-Process Reticle Floorplanner and Wafer Dicing Planner for Multi-Project Wafers |
| Author | *Chien-Chang Chen, Wai-Kei Mak (National Tsing Hua University, Taiwan) |
| Page | pp. 777 - 782 |
| Keyword | floorplan, integer linear programming, multi project wafers |
| Abstract | As the VLSI manufacturing technology advances
into the deep sub-micron(DSM) era, the mask cost can reach one or two million dollars. Multiple project wafers (MPW) which put different dies onto the same set of masks is a good cost-sharing approach. Every design needs to be produced by its desired technology process, such as 1 poly with 4 metal layers (1P4M), or 1 poly with 5 metal layers (1P5M). Dies with different desired manufacturing processes cannot be produced from the same wafer,
but they can be put onto the same set of masks in order to reduce the total cost of the used masks and wafers. In this paper, we propose a novel integer linear programming (ILP)-based floorplanner for shuttle runs consisting of projects requiring different desired processes. Two simulated annealing-based side-to-side wafer dicing planners are also presented. Experimental results
show that our approach achieves 28% wafer reduction on
average compared to a previous simulated annealing-based reticle floorplanner. |
| PDF file |
| Title | Design Space Exploration for Minimizing Multi-Project Wafer Production Cost |
| Author | Rung-Bin Lin, *Meng-Chiou Wu, Wei-Chiu Tseng, Ming-Hsine Kuo, Tsai-Ying Lin, Shr-Cheng Tsai (Yuan Ze University, Taiwan) |
| Page | pp. 783 - 788 |
| Keyword | Multi-project wafer, Reticle floorplanning, Wafer dicing, Design space exploration, Mask cost |
| Abstract | Chip floorplan in a reticle for Multi-Project Wafer (MPW) plays a key role in deciding chip fabrication cost. In this paper , we propose a methodology to explore reticle flooplan design space to minimize MPW production cost, facilitated by a new cost model and an efficient reticle floorplanning method. It is shown that a good floorplan saves 47% and 42% production cost with respect to a poor floorplan for small and medium volume production, respectively. |
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