| Friday January 27, 2006 |
| Title | Introduction to H.264 Advanced Video Coding |
| Author | Jian-Wen Chen, Chao-Yang Kao, *Youn-Long Lin (National Tsing Hua University, Taiwan) |
| Page | pp. 736 - 741 |
| Keyword | Video Coding, H.264, Video Compression, MPEG-4 Part 10, Advanced Video Coding |
| Abstract | We give a tutorial on video coding principles and standards with emphasis on the latest technology called H.264 or MPEG-4 Part 10. We describe a basic method called block-based hybrid coding employed by most video coding standards. We use graphical illustration to show the functionality. This paper is suitable for those who are interested in implementing video codec in embedded software, pure hardwired, or a combination of both. |
| PDF file | |
| Title | Algorithms and DSP Implementation of H.264/AVC |
| Author | Hung-Chih Lin, Yu-Jen Wang, Kai-Ting Cheng, Shang-Yu Yeh, Wei-Nien Chen, Chia-Yang Tsai, Tian-Sheuan Chang, *Hsueh-Ming Hang (National Chiao-Tung University, Taiwan) |
| Page | pp. 742 - 749 |
| Keyword | H.264, AVC, video coding |
| Abstract | This survey paper intends to provide a comprehensive coverage of the techniques that are pertinent to the processor-based implementation of H.264/AVC video codec, particularly on DSP. Most of this paper is devoted to the computationally efficient algorithms, or the fast algorithms. Fast algorithms for motion estimation, intra-prediction and mode decision are described to reduce the computational complexity. In addition, in order to port the H.264/AVC codec to DSP, we also outline the basic principles of DSP code optimization. |
| PDF file | |
| Title | Hardware Architecture Design of an H.264/AVC Video Codec |
| Author | Tung-Chien Chen, Chung-Jr Lian, *Liang-Gee Chen (National Taiwan University, Taiwan) |
| Page | pp. 750 - 757 |
| Keyword | H.264/AVC, Video Codec, VLSI architecture, Video coding, Motion estimation |
| Abstract | H.264/AVC is the latest video coding standard. It significantly outperforms the previous video coding standards, but the extraordinary huge computation complexity and memory access requirement make the hardwired codec solution a tough job. This paper describes the design methodology for H.264/AVC video codec. The system architecture and scheduling will be addressed. The design consideration and optimization for its significant modules including bandwidth optimized motion compensation engine, reconfigurable intra predictor generator, low bandwidth parallel integer motion estimation will be mentioned. Due to the complex, sequential, and highly data-depended characteristics of all essential algorithms in H.264/AVC, not only the pipeline structure but also efficient memory hierarchy is required. The design case with a hybrid task pipelining scheme, a balanced schedule with block-level, MB-level, and frame-level pipelining, will be presented. By combining with many bandwidth reduction techniques and data reused schemes, very efficient architecture and implementation for plate-form based system is proved by the prototype chips. |
| PDF file | |
| Title | ASIP Approach for Implementation of H.264/AVC |
| Author | Sung Dae Kim, Jeong Hoo Lee, Chung Jin Hyun, *Myung Hoon Sunwoo (Ajou University, Republic of Korea) |
| Page | pp. 758 - 764 |
| Keyword | H.264/AVC, ASIP, ASDSP |
| Abstract | This paper introduces an Application-Specific Instruction Set Processor (ASIP) approach for implementation of H.264/AVC. The proposed ASIP has special instructions for intra prediction, deblocking filter, integer transform, etc. The proposed ASIP also has hardware accelerators for inter prediction and entropy coding. Performance comparisons show a significant improvement compared with existing DSPs. The proposed hardware accelerators have small size and can support real-time video processing. Moreover, the proposed ASIP can operate various multimedia standards. The results indicate that the ASIP approach is one of promising solutions for H.264/AVC. |
| PDF file | |