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The 11th Asia and South Pacific Design Automation Conference

Wednesday January 25, 2006

Session 2C Placement (13:30 - 15:35)
Location: Room 414+415
Chair(s): Evangeline F.Y. Young (Chinese Univ. of Hong Kong, Hong Kong), Shin'ichi Wakabayashi (Hiroshima City Univ., Japan)

2C-1 (Time: 13:30 - 13:55)
TitleA Robust Detailed Placement for Mixed-Size IC Designs
AuthorJason Cong, *Min Xie (Univ. of California, Los Angeles, United States)
Pagepp. 188 - 194
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2C-2 (Time: 13:55 - 14:20)
TitleFastPlace 2.0: An Efficient Analytical Placer for Mixed-Mode Designs
Author*Natarajan Viswanathan, Min Pan, Chris Chu (Iowa State Univ., United States)
Pagepp. 195 - 200
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2C-3 (Time: 14:20 - 14:45)
TitleTiming-Driven Placement Based on Monotone Cell Ordering Constraints
AuthorChanseok Hwang, *Massoud Pedram (Univ. of Southern California, United States)
Pagepp. 201 - 206
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2C-4 (Time: 14:45 - 15:10)
TitleConstraint Driven I/O Planning and Placement for Chip-package Co-design
Author*Jinjun Xiong (Univ. of California, Los Angeles, United States), Yiu-Chung Wong, Egino Sarto (Rio Design Automation, United States), Lei He (Univ. of California, Los Angeles, United States)
Pagepp. 207 - 212
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2C-5 (Time: 15:10 - 15:35)
TitleSimultaneous Block and I/O Buffer Floorplanning for Flip-Chip Design
Author*Chih-Yang Peng, Wen-Chang Chao, Yao-Wen Chang (National Taiwan Univ., Taiwan), J.-H. Wang (Faraday Technology Corp., Taiwan)
Pagepp. 213 - 218
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