Disclaimer -- Permission to make digital/hard copy of all or part of any of the following publications and technical reports for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage. To copy otherwise, to republish, to post on servers, or to redistribute to lists requires prior specific permission.

• Andreas Gerstlauer, Dongwan Shin, Samar Abdi, Pramod Chandraiah and Daniel D. Gajski, "Design of a MP3 Decoder using the System-On-Chip Environment (SCE)," CECS, UC Irvine, Technical Report CECS-TR-07-05, November 2007.

• Eric James Johnson, Andreas Gerstlauer and Rainer Doemer, "Efficient Debugging and Tracing of System Level Designs," CECS, UC Irvine, Technical Report CECS-TR-06-08, May 2006.
• Gunar Schirner, Gautam Sachdeva, Andreas Gerstlauer and Rainer Doemer, "Modeling, Simulation and Synthesis in an Embedded Software Design Flow for an ARM Processor," CECS, UC Irvine, Technical Report CECS-TR-06-06, May 2006.

• Daniel Gajski, Andreas Gerstlauer, Rainer Dömer, Samar Abdi, Jerry Peng and Dongwan Shin, "TL Environment," CECS, UC Irvine, Technical Report CECS-TR-05-10, July 2005.

• Dongwan Shin, Andreas Gerstlauer, Rainer Dömer and Daniel D. Gajski, "System-on-Chip Communication Modeling Style Guide," CECS, UC Irvine, Technical Report CECS-TR-04-25, July 2004.
• Dongwan Shin, Lukai Cai, Andreas Gerstlauer, Rainer Dömer and Daniel D. Gajski, "System-on-Chip Transaction-Level Modeling Style Guide," CECS, UC Irvine, Technical Report CECS-TR-04-24, July 2004.
• Dongwan Shin, Junyu Peng, Andreas Gerstlauer, Rainer Dömer and Daniel D. Gajski, "System-on-Chip Network Modeling Style Guide," CECS, UC Irvine, Technical Report CECS-TR-04-23, July 2004.
• Junyu Peng, Andreas Gerstlauer, Rainer Dömer and Daniel D. Gajski, "System-on-Chip Architecture Modeling Style Guide," CECS, UC Irvine, Technical Report CECS-TR-04-22, July 2004.
• Rainer Dömer, Andreas Gerstlauer, and Dongwan Shin, "Cycle-accurate RTL Modeling with Multi-Cycled and Pipelined Components," CECS, UC Irvine, Technical Report CECS-TR-04-19, July 2004.
• Dongwan Shin, Andreas Gerstlauer and Daniel Gajski, "Communication Link Synthesis for SoC," CECS, UC Irvine, Technical Report CECS-TR-04-16, June 2004.
• Dongwan Shin, Andreas Gerstlauer and Daniel Gajski, "Network Synthesis for SoC," CECS, UC Irvine, Technical Report CECS-TR-04-15, June 2004.
• Lucai Cai, Andreas Gerstlauer, and Daniel Gajski, "Retargetable Profiling for Rapid, Early System-Level Design Space Exploration," CECS, UC Irvine, Technical Report CECS-TR-04-04, October 2003.

• Dongwan Shin, Andreas Gerstlauer, Rainer Dömer, Daniel Gajski, "C-based Interactive RTL Design Methodology," CECS, UC Irvine, Technical Report CECS-TR-03-42, December 2003.
• Samar Abdi, Junyu Peng, Haobo Yu, Dongwan Shin, Andreas Gerstlauer, Rainer Dömer, Daniel Gajski, "System-on-Chip Environment (SCE Version 2.2.0 Beta): Tutorial," CECS, UC Irvine, Technical Report CECS-TR-03-41, July 2003.
• Dongwan Shin, Samar Abdi, Daniel Gajski, "Automatic Generation of Bus Functional Models from Transaction Level Models," CECS, UC Irvine, Technical Report CECS-TR-03-33, November 2003.
• Daniel Gajski and Samar Abdi, "System Debugging and Verification : A New Challenge," CECS, UC Irvine, Technical Report CECS-TR-03-31, October 2003.
• Andreas Gerstlauer, "Communication Abstractions for System-Level Design and Synthesis," CECS, UC Irvine, Technical Report CECS-TR-03-30, October 2003.
• Samar Abdi and Daniel D. Gajski, "Provably Correct Architecture Refinement," CECS, UC Irvine, Technical Report CECS-TR-03-29, September 2003.
• Daniel D. Gajski, "NISC: The Ultimate Reconfigurable Component," CECS, UC Irvine, Technical Report CECS-TR-03-28, September 2003.
• Andreas Gerstlauer, Kiran Ramineni, Rainer Dömer and Daniel D. Gajski, "System-On-Chip Specification Style Guide," CECS, UC Irvine, Technical Report CECS-TR-03-21, June 2003.
• Kiran Ramineni and Daniel Gajski, "C to SpecC Conversion Style," CECS, UC Irvine, Technical Report CECS-TR-03-13, April 2003.
• Haobo Yu, Andreas Gerstlauer, Daniel Gajski, "RTOS Scheduling in Transaction Level Models," CECS, UC Irvine, Technical Report CECS-TR-03-12, March 2003.
• Lucai Cai, Shireesh Verma, Daniel D. Gajski, "Comparison of SpecC and SystemC Languages for System Design," CECS, UC Irvine, Technical Report CECS-TR-03-11, May 2003.
• Lucai Cai and Daniel Gajski, "Transaction Level Modeling in System Level Design," CECS, UC Irvine, Technical Report CECS-TR-03-10, March 2003.
• Anshuman Tripathi, Shireesh Verma, Daniel D. Gajski, "G.729E Algorithm Optimization for ARM926EJ-S Processor," CECS, UC Irvine, Technical Report CECS-TR-03-09, March 2003.
• Samar Abdi and Daniel Gajski, "Automatic Communication Refinement for System Level Design," CECS, UC Irvine, Technical Report CECS-TR-03-08, March 2003.
• Samar Abdi and Daniel Gajski, "Formal Verification of Specification Partitioning," CECS, UC Irvine, Technical Report CECS-TR-03-06, March 2003.
• Lukai Cai and Daniel Gajski, "Channel Mapping in System Level Design," CECS, UC Irvine, Technical Report CECS-TR-03-03, January 2003.
• Daniel Gajski, Junyu Peng, Andreas Gerstlauer, Haobo Yu, Dongwan Shin, "System Design Methodology and Tools," CECS, UC Irvine, Technical Report CECS-TR-03-02, January 2003.

• Daniel D. Gajski, "System Level Design Flow: What is needed and what is not," CECS, UC Irvine, Technical Report CECS-TR-02-33, November 2002.
• Lukai Cai, Daniel D. Gajski, "Variable Mapping of System Level Design," CECS, UC Irvine, Technical Report CECS-TR-02-32, October 2002.
• Lukai Cai, Daniel D. Gajski, "Grouping-Based Architecture Exploration of System-Level Design," CECS, UC Irvine, Technical Report CECS-TR-02-31, August 2002.
• Lukai Cai, Daniel D. Gajski, Mike Olivarez, Paul Kritzinger, "C/C++ Based System Design Flow Using SpecC, VCC and SystemC," CECS, UC Irvine, Technical Report CECS-TR-02-30, June 2002.
• S. Abdi, J. Peng, R. Dömer, D. Shin, A. Gerstlauer, A. Gluhak, L.Cai, Q. Xie, H. Yu, P. Zhang, D. Gajski, "System-On-Chip Environment (SCE): Tutorial," CECS, UC Irvine, Technical Report CECS-TR-02-28, September 2002.
• Haobo Yu, Daniel D. Gajski, "RTOS Modeling in System Level Synthesis," CECS, UC Irvine, Technical Report CECS-TR-02-25, August 2002.
• Lukai Cai, Daniel D. Gajski, "Specification Tuning of System-Level Design," CECS, UC Irvine, Technical Report CECS-TR-02-20, June 2002.
• Lukai Cai, Daniel D. Gajski, "Parallelization Optimization of System-Level Specification," CECS, UC Irvine, Technical Report CECS-TR-02-18, June 2002.
• Andreas Gerstlauer, Daniel D. Gajski, "System-Level Abstraction Semantics," CECS, UC Irvine, Technical Report CECS-TR-02-17, July 2002.
• Andreas Gerstlauer, "SpecC Modeling Guidelines," CECS, UC Irvine, Technical Report CECS-TR-02-16, April 2002.
• Junyu Peng, Lukai Cai, Andreas Gerstlauer, Daniel D. Gajski, "Interactive System Design Flow," CECS, UC Irvine, Technical Report CECS-TR-02-15, April 2002.
• Junyu Peng, Samar Abdi, Daniel D. Gajski, "Automatic Model Refinement for Fast Architecture Exploration," CECS, UC Irvine, Technical Report CECS-TR-02-14, April 2002.
• Dongwan Shin, Daniel D. Gajski, "Interface Synthesis from Protocol Specification," CECS, UC Irvine, Technical Report CECS-TR-02-13, April 2002.
• Dongwan Shin, Daniel D. Gajski, "Queue Generation Algorithm for Interface Synthesis," CECS, UC Irvine, Technical Report CECS-TR-02-12, February 2002.
• Dongwan Shin, Daniel D. Gajski, "Scheduling in RTL Design Methodology," CECS, UC Irvine, Technical Report CECS-TR-02-11, April 2002.
• Pei Zhang, Daniel D. Gajski, "RTL Design and Synthesis of Sequential Matrix Multiplication," CECS, UC Irvine, Technical Report CECS-TR-02-09, April 2002.
• Lukai Cai, Daniel D. Gajski, "System Level Design Using SpecC Profiler," CECS, UC Irvine, Technical Report CECS-TR-02-08, April 2002.
• Lukai Cai, Daniel D. Gajski, "Introduction of Design-Oriented Profiler of SpecC Language," CECS, UC Irvine, Technical Report CECS-TR-02-07, March 2002.
• Qiang Xie, Daniel D. Gajski, "Parity Checker Implementations in SpecC," CECS, UC Irvine, Technical Report CECS-TR-02-06, January 2002.
• Haobo Yu, Daniel D. Gajski, "Datapath Synthesis for a 16-bit Microprocessor," CECS, UC Irvine, Technical Report CECS-TR-02-05, January 2002.
• Wolfgang Mueller, Rainer Dömer, Daniel D. Gajski, "The Formal Execution Semantics of SpecC," CECS, UC Irvine, Technical Report CECS-TR-02-04, January 2002.

• Dongwan Shin, Daniel D. Gajski, "Scheduling in RTL Design Methodology," UC Irvine, Technical Report ICS-TR-01-65, July 2001.
• Wolfgang Mueller, Rainer Dömer, Andreas Gerstlauer, "The Formal Execution Semantics of SpecC," UC Irvine, Technical Report ICS-TR-01-59, November 2001.
• Slim Ben Saoud, Daniel D. Gajski, "Co-design of Emulators for Power electric Processes Using SpecC Methodology," UC Irvine, Technical Report ICS-TR-01-46, July 2001.
• Slim Ben Saoud, Daniel D. Gajski, "SpecC Methodology applied to the Design of Control systems for Power Electronics and Electric Drives," UC Irvine, Technical Report ICS-TR-01-45, July 2001.
• Slim Ben Saoud, Daniel D. Gajski, "Specification and Validation of New Control Algorithms for Electric Drives using SpecC Language," UC Irvine, Technical Report ICS-TR-01-44, July 2001.
• Haobo Yu, Daniel D. Gajski, "Interconnection Binding in RTL Design Methodology," UC Irvine, Technical Report ICS-TR-01-38, June 2001.
• Pei Zhang, Daniel D. Gajski, "Storage Binding in RTL Synthesis," UC Irvine, Technical Report ICS-TR-01-37, August 2001.
• Qiang Xie, Daniel D. Gajski, "Function Binding in RTL Design Methodology," UC Irvine, Technical Report ICS-TR-01-37, June 2001.
• Martin von Weymarn, "Development of a Specification Model of the EFR Vocoder," UC Irvine, Technical Report ICS-TR-01-35, July 2001.
• Shuqing Zhao, "RTL Modeling in C++," UC Irvine, Technical Report ICS-TR-01-18, April, 2001.
• David Berner, Dirk Jansen, Daniel D. Gajski, "Development of a Visual Refinement and Exploration Tool for SpecC," UC Irvine, Technical Report ICS-TR-01-12, March 2001.

• Lucai Cai, Daniel D. Gajski, "Introduction of Design-Oriented Profiler of SpecC Language," UC Irvine, Technical Report ICS-TR-00-47, June 2001.
• Andreas Gerstlauer, "Communication Software Code Generation," UC Irvine, Technical Report ICS-TR-00-46, August 2000.
• Pei Zhang, Dongwan Shin, Haobo Yu, Qiang Xie, Daniel D. Gajski, "SpecC RTL Methodology," UC Irvine, Technical Report ICS-TR-00-44, December 2000.
• Hanyu Yin, Haito Du, Tzu-Chia Lee, Daniel D. Gajski, "Design of a JPEG Encoder using SpecC Methodology," UC Irvine, Technical Report ICS-TR-00-23, July 2000.
• Dirk Jansen, "SpecC for Beginners: The Example of a Sounding Dice," UC Irvine, Technical Report ICS-TR-00-14, May 2000.
• Junyu Peng, Lukai Cai, Anand Selka, Daniel D. Gajski, "Design of a JBIG Encoder using SpecC Methodology," UC Irvine, Technical Report ICS-TR-00-13, June 2000.

• D. Gajski, J. Zhu, R. Dömer, A. Gerstlauer, S. Zhao, "The SpecC Methodology" UC Irvine, Technical Report ICS-TR-99-56, December 1999.
• L. Cai, J. Peng, C. Chang, A. Gerstlauer, H. Li, A. Selka, C. Siska, L. Sun, S. Zhao and D. Gajski, "Design of a JPEG Encoding System," UC Irvine, Technical Report ICS-TR-99-54, November 1999.
• Heiko Lehr and Daniel D. Gajski, "Modeling Custom Hardware in VHDL," UC Irvine, Technical Report ICS-TR-99-29, July 1999.
• En-Shou Chang and Daniel D. Gajski, "SpecC System-level Static Scheduling," UC Irvine, Technical Report ICS-TR-99-23, May 1999.
• Andreas Gerstlauer, Shuqing Zhao, Daniel D. Gajski and Arkady M. Horak, "Design of a GSM Vocoder using SpecC Methodology," UC Irvine, Technical Report ICS-TR-99-11, March 1999.
• Jianwen Zhu and Daniel D. Gajski, "A Unified Formal Model of ISA and FSMD," UC Irvine, Technical Report ICS-TR-99-06, Feburary 1999.

• Andreas Gerstlauer, Shuqing Zhao and Daniel D. Gajski, "VHDL+/SpecC Comparisons - A Case Study," UC Irvine, Technical Report ICS-TR-98-23, May 1998.
• En-Shou Chang and Daniel D. Gajski, "System-Level Timing-constrained Scheduling," UC Irvine, Technical Report ICS-TR-98-15, January 1998.
• Rainer Dömer, Jianwen Zhu, Daniel D. Gajski, "The SpecC Language Reference Manual," UC Irvine, Technical Report ICS-TR-98-13, March 1998.
• Gaurav Aggarwal and Daniel D. Gajski, "Exploring DCT Implementations," UC Irvine, Technical Report ICS-TR-98-10, March 1998.
• Daniel D. Gajski, Gaurav Aggarwal, En-Shou Chang, Rainer Doemer, Tadatoshi Ishii, Jon Kleinsmith and Jianwen Zhu, "Methodology for Co-design of Embedded Systems," UC Irvine, Technical Report ICS-TR-98-07, March 1998.
• Jon Kleinsmith and Daniel D. Gajski, "Communication Synthesis for Reuse," UC Irvine, Technical Report ICS-TR-98-06, February 1998.
• Gaurav Aggarwal and Daniel D. Gajski, "Modeling Guidelines for ASIC Reuse," UC Irvine, Technical Report ICS-TR-98-03, March 1998

• Jon Kleinsmith, Jianwen Zhu and Daniel D. Gajski, "ATM Modeling Example for SpecGen Evaluation," UC Irvine, Technical Report ICS-TR-97-47, October 1997.
• En-Shou Chang and Daniel D. Gajski, "A generic binding model for concurrently optimizing interconnection and functional units," UC Irvine, Technical Report ICS-TR-97-42, October 1997.
• Peter Grun, Nikil Dutt and Florin Balasa, "System Level Memory Size Estimation," UC Irvine, Technical Report ICS-TR-97-37, September 1997.
• Hartej Singh and Daniel D. Gajski, "A Design Methodology for Behavioral Level Power Exploration: Implementation and Experiments," UC Irvine, Technical Report ICS-TR-97-28.
• Daniel D. Gajski, Jianwen Zhu, Rainer Doemer, "Essential Issues in Codesign," UC Irvine, Technical Report ICS-TR-97-26, June 1997.
• Jianwen Zhu, Rainer Doemer, Daniel D. Gajski, "Syntax and Semantics of the SpecC+ Language," UC Irvine, Technical Report ICS-TR-97-16, April 1997.
• Daniel D. Gajski, Jianwen Zhu, Rainer Doemer, "The SpecC+ Language," UC Irvine, Technical Report ICS-TR-97-15, April 15, 1997.
• Jon Kleinsmith, Tatsuya Umezaki, Zhuzhen Kang and Daniel Gajski, "Co-Design Methodology for ATM Applications Domain," UC Irvine, Technical Report ICS-TR-97-14, January 1997.

• En-Shou Chang and Daniel D. Gajski, "A connection-oriented binding model for binding algorithms," UC Irvine, Technical Report ICS-TR-96-49, Oct 1996
• Hartej Singh and Daniel D. Gajski, "A Design Methodology for Behavioral Level Power Exploration," UC Irvine, Technical Report ICS-TR-96-44, Oct 1996
• Daniel D. Gajski, Peter Grun, Wenwei Pan and Smita Bakshi, "Design Exploration for Pipelined IDCT," UC Irvine, Technical Report ICS-TR-96-41, September 1996.
• Wenwei Pan, Peter Grun, Daniel D. Gajski, "Behavioral Exploration with RTL Library," UC Irvine, Technical Report ICS-TR-96-34, July 1996.
• Daniel D. Gajski, Tadatoshi Ishii, Viraphol Chaiyakul, Hsiao-Ping Juan and Tedd Hadley, "A Design Methodology and Environment for Interactive Behavioral Synthesis," UC Irvine, Technical Report ICS-TR-96-29, June 1996.
• En-Shou Chang and Daniel D. Gajski, "Software Performance Estimation for Toshiba TLCS-R3900," UC Irvine, Technical Report ICS-TR-96-19, May 1996.
• Hsiao-ping Juan, Daniel D. Gajski and Viraphol Chaiyakul, "Clock-Driven Performance Optimization in Interactive Behavioral Synthesis," UC Irvine, Technical Report ICS-TR-96-08, April 1996.
• Hsiao-Ping Juan, Daniel D. Gajski and Smita Bakshi, "Clock Optimization for High-Performance Pipelined Design," UC Irvine, Technical Report ICS-TR-96-01.

• En-Shou Chang and Daniel D. Gajski and Sanjiv Narayan, "An optimal clock period selection method based on slack minimization criteria," UC Irvine, Technical Report ICS-TR-95-57, December 1995.
• En-Shou Chang, "An optimal slack minimization method," UC Irvine, Technical Report ICS-TR-95-34, 1995
• Daniel D. Gajski and Hsiao-Ping Juan, "A Design Methodology for Interactive Behavioral Synthesis," UC Irvine, Technical Report ICS-TR-95-25, July 1995.
• Chu-Yi Huang and Daniel D. Gajski, "Software Performance Estimation for Pipeline and Superscalar Processors," UC Irvine, Technical Report ICS-TR-95-20, June 1995.
• Smita Baskshi and Daniel D. Gajski, "A Memory Selection Algorithm for High-Performance Pipelines," UC Irvine, Technical Report ICS-TR-95-03, Jan 1995.

• Hsiao-Ping Juan, Viraphol Chaiyakul and Daniel D. Gajski, "Condition Graphs for High-Quality Behavioral Synthesis," UC Irvine, Technical Report ICS-TR-94-32, August 1994.
• Nikil Dutt and Pradip K. Jha, "RT Component Sets for High Level Design Applications," UC Irvine, Technical Report ICS-TR-94-27, June 1994
• Roger Ang and Nikil Dutt, "Scheduling for Design Reuse of Datapath Components," UC Irvine, Technical Report ICS-TR-94-16, May 1994
• Pradip K. Jha and Nikil Dutt, "High-Level Library Mapping for Arithmetic Components," UC Irvine, Technical Report ICS-TR-94-15, April 1994.
• Smita Bakshi and Daniel D. Gajski, "A Component Selection Algorithm for High-Performance Pipelines," UC Irvine, Technical Report ICS-TR-94-01, June 1994.

• Roger Ang and Nikil Dutt, "Allocation of Functional Units from Realistic Component Libraries," UC Irvine, Technical Report ICS-TR-93-47, October 1993.
• Frank Vahid, Jie Gong and Daniel D. Gajski, "A Hardware-Software Partitioning Algorithm for Minimizing Hardware," UC Irvine, Technical Report ICS-TR-93-38, September 1993.
• Smita Bakshi and Daniel D. Gajski, "Design Space Exploration for The Beamformer System," UC Irvine, Technical Report ICS-TR-93-34, August 1993, 29 pages.
• Pradip K. Jha, Tedd Handley and Nikil Dutt, "The GENUS User Manual and C Programming Library," UC Irvine, Technical Report ICS-TR-93-32, April 1993.
• Daniel D. Gajski, Frank Vahid, and Sanjiv Narayan, "SpecCharts: A VHDL Front-End for Embedded Systems," UC Irvine, Technical Report ICS-TR-93-31, June 1993, 26 pages.
• Smita Bakshi and Daniel D. Gajski, "A Strategy for Design Space Exploration," UC Irvine, Technical Report ICS-TR-93-10, August 1993.
• Pradip K. Jha, Nikil D. Dutt, and Daniel D. Gajski, "An Evaluative Study of RT Component Libraries ," UC Irvine, Technical Report ICS-TR-93-11, March 1993, 53 pages.
• Daniel D. Gajski, Tedd Hadley, Viraphol Chaiyakul, and Tadatoshi Ishii, "Design Process and Human Interface for a Behavioral-Synthesis Environment," UC Irvine, Technical Report ICS-TR-93-07, January 1993, 47 pages.
• Jie Gong, Daniel Gajski, and Sanjiv Narayan, "Software Estimation from Executable Specifications," UC Irvine, Technical Report ICS-TR-93-05, March 1993, 28 pages.
• Daniel Gajski, Jie Gong, Frank Vahid, and Sanjiv Narayan, "The SpecSyn Design Process and Human Interface ," UC Irvine, Technical Report ICS-TR-93-03, 1993, 46 pages.

• Pradip K. Jha, Champaka Ramachandran, Nikil D. Dutt and Daniel D. Gajski, "The Effects of Variations om Component Styles and Shapes on High-Level Synthesis," UC Irvine, Technical Report ICS-TR-92-115, December 1992, 24 pages.
• Viraphol Chaiyakul and Daniel D. Gajski, "Assignment Decision Diagram for High-Level Synthesis," UC Irvine, Technical Report ICS-TR-92-103, December 1992, 51 pages.
• Daniel Gajski, Sanjiv Narayan, and Frank Vahid, "A System-Level Specification and Design Methodology," UC Irvine, Technical Report ICS-TR-92-102, October 1992, 22 pages.
• Roger Ang and Nikil Dutt, "On Linking RT-Component Functionality to Abstract HDL Behavior - REVISED," UC Irvine, Technical Report ICS-TR-92-97, July 1993.
• Hsiao-Ping Juan, Nancy Holmes, Smita Bakshi, and Daniel Gajski, "Top-Down Modeling of RISC Processors in VHDL," UC Irvine, Technical Report ICS-TR-92-96, October 1992, 47 pages
• Loganath Ramachandran, Viraphol Chaiyakul, and Daniel D. Gajski, "VHDL Synthesis System (VSS) User's Manual Version 5.0," UC Irvine, Technical Report ICS-TR-92-52, June 1992, 16 pages. ($2.00)
• Loganath Ramachandran and Daniel D. Gajski, "Architectural Tradeoffs in Synthesis of Pipelined Controls," UC Irvine, Technical Report ICS-TR-92-49, May 1992, 22 pages.
• Viraphol Chaiyakul, Daniel D. Gajski, and Loganath Ramachandran, "Minimizing Syntactic Variance with Assignment Decision Diagrams," UC Irvine, Technical Report ICS-TR-92-34, April 1992, 19 pages.
• Pradip K. Jha and Nikil D. Dutt, "A Fast Area-Delay Estimation Technique for RTL Component Generators," UC Irvine, Technical Report ICS-TR-92-33, April 1992, 33 pages.
• Roger Ang and Nikil Dutt, "Transformations Supporting Interactive Rescheduling for High-Level Synthesis," UC Irvine, Technical Report ICS-TR-92-20, February 1992.

• Frank Vahid, "A Survey of Behavioral-Level Partitioning Systems," UC Irvine, Technical Report ICS-TR-91-71, October 1991, 33 pages.
• Sanjiv Narayan, Frank Vahid, Daniel D. Gajski, "Modeling with SpecCharts," UC Irvine, Technical Report ICS-TR-90-20, July 1990, revised October 1992, 61 pages.
• Nikil Dutt, Tedd Hadley and Daniel D. Gajski, "BIF: A Behavioral Intermediate Format For High Level Synthesis," UC Irvine, Technical Report ICS-TR-89-03, February 1989.