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CODES+ISSS'08 Table of Contents Message from the Technical Program Chairs Session 1A: Analysis of Parallel Application and Architecture Synthesis Synthesis of Heterogeneous Pipelined Multiprocessor Systems using ILP : JPEG Case Study (Page 1) Concurrency Emulation and Analysis of Parallel Applications for Multi-Processor System-on-Chip Co-Design (Page 7) Session 1B: Flash Memory Management A Time-Predictable System Initialization Design for Huge-Capacity Flash-Memory Storage Systems (Page 13) Deterministic Service Guarantees for NAND Flash Using Partial Block Cleaning (Page 19) |
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Session 2A: Application Specific Processor Systems Static Analysis of Processor Stall Cycle Aggregation (Page 25) Application Specific Non-Volatile Primary Memory for Embedded Systems (Page 31) Scratchpad Allocation for Concurrent Embedded Software (Page 37) Software Optimization for MPSoC : A MPEG-2 Decoder Case Study (Page 43) Session 2B: Performance Enhancement—New Techniques for FPGAs and Partitioning Hardware/Software Partitioning of Floating Point Software Applications to Fixed-Pointed Coprocessor Circuits (Page 49) A Performance-Oriented Hardware/Software Partitioning for Datapath Applications (Page 55) Traversal Caches: A First Step Towards FPGA Acceleration of Pointer-Based Data Structures (Page 61) Specification and OS-Based Implementation of Self-adaptive, Hardware / Software Embedded Systems (Page 67) |
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Session 3A: Multiprocessor and MPSoC Architectures Distributed and Low-Power Synchronization Architecture for Embedded Multiprocessors (Page 73) LOCS: A Low Overhead Profiler-Driven Design Flow for Security of MPSoCs (Page 79) Online Adaptive Utilization Control for Real-Time Embedded Multiprocessor Systems (Page 85) Intra- and Inter-Processor Hybrid Performance Modeling for MPSoC Architectures (Page 91) Session 3B: Exploration, Profiling and Tuning of Embedded Systems Dynamic Tuning of Configurable Architectures: The AWW Online Algorithm (Page 97) Static Analysis for Fast and Accurate Design Space Exploration of Caches (Page 103) Profiling of Lossless-Compression Algorithms for a Novel Biomedical-Implant Architecture (Page 109) Holistic Design and Caching in Mobile Computing (Page 115) |
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SPECIAL SESSION I: You Can Catch More Bugs with Transaction-Level Honey You Can Catch More Bugs With Transaction Level Honey (Page 121) Session 5A: Simulation and Verification of Embedded Systems Simulation and Embedded Software Development for Anton, a Parallel Machine with Heterogeneous Multicore ASICs (Page 125) Model Checking SystemC Designs Using Timed Automata (Page 131) Specification-based Compaction of Directed Tests for Functional Validation of Pipelined Processors (Page 137) Combination of Instruction Set Simulation and Abstract RTOS Model Execution for Fast and Accurate Target Software Evaluation (Page 143) |
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Session 5B: Case Studies and Industrial Practices Cache-aware Optimization of BAN Applications (Page 149) Don't Forget Memories — A Case Study Redesigning a Pattern Counting ASIC Circuit for FPGAs (Page 155) Reliable Performance Analysis of a Multicore Multithreaded System-On-Chip (Page 161) Extending Open Core Protocol to Support System-Level Cache Coherence (Page 167) |
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Session 6A: Models and Techniques for Performance Estimation and Solution Space Representation, and a Special Citation Analysis Performance Debugging of Esterel Specifications (Page 173) SPaC: A Symbolic Pareto Calculator (Page 179) Providing Accurate Event Models for the Analysis of Heterogeneous Multiprocessor Systems (Page 185) Highly-Cited Ideas in System Codesign and Synthesis (Page 191) Session 6B: Advanced NoC Design Techniques A Security Monitoring Service for NoCs (Page 197) ODOR: a Microresonator-based High-performance Low-cost Router for Optical Networks-on-Chip (Page 203) Asynchronous Transient Resilient Links for NoC (Page 209) Distributed Flit-Buffer Flow Control for Networks-on-Chip (Page 215) |
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Keynote Address Co-Design in the Wilderness (Page 221) |
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SPECIAL SESSION II: Design and Defect Tolerance Beyond CMOS Design and Defect Tolerance Beyond CMOS (Page 223) Session 8A: System Level Design: Throughput, Dependability, Coherence, and Yield Slack Analysis in the System Design Loop (Page 231) Symbolic Voter Placement for Dependability-Aware System Synthesis (Page 237) Speculative DMA for Architecturally Visible Storage in Instruction Set Extensions (Page 243) Yield Maximization for System-level Task Assignment and Configuration Selection of Configurable MultiProcessors (Page 249) |
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Session 8B: System Level Power Modeling and Optimization Methodology for Multi-Granularity Embedded Processor Power Model Generation for an ESL Design Flow (Page 255) Power Reduction via Macroblock Prioritization for Power Aware H.264 Video Applications (Page 261) Guaranteed Scheduling for Repetitive Hard Real-Time Tasks Under The Maximal Temperature Constraint (Page 267) System-Level Mitigation of WID Leakage Power Variability Using Body-Bias Islands (Page 273) |
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