ISLPED 2002 TABLE OF CONTENTS

Foreword

Keynote Speech

Low-Voltage Memories for Power Aware Systems [p. 1]

Kiyoo Itoh (Hitachi Ltd.)

Session 1: Low Power Modeling and Systems

1.1 Standby Power Management for a 0.18 um Microprocessor [p. 7]

L.T. Clark, S. Demmons, N. Deutscher, F. Ricci (Intel Corporation)

1.2 Physical Insight into Fractional Power Dependence of Saturation Current on Gate Voltage in Advanced Short Channel MOSFETs [p. 13]

H. Im (University of Tokyo, Dongguk University), M. Song (Dongguk University), T. Hiramoto (University of Tokyo, VLSI Design and Education Center), T. Sakurai (University of Tokyo)

1.3 Full-chip Sub-threshold Leakage Power Prediction Model for sub-0.18um CMOS [p. 19]

S. Narendra (Massachusetts Institute of Technology, Intel Laboratories), V. De, S. Borkar (Intel Laboratories), D. Antoniadis, A. Chandrakasan (Massachusetts Institute of Technology)

1.4 Power-Conscious Interconnect Buffer Optimization with Improved Modeling of Driver MOSFET and its Implications to Bulk and SOI CMOS Technology [p. 24]

K. Nose, T. Sakurai (University of Tokyo)

Session 2: Energy Efficient Communications

2.1 E²WFQ: An Energy-Efficient Fair Scheduling Policy for Wireless Systems [p. 30]

V. Raghunathan, S. Ganeriwal, C. Schurgers, M. Srivastava (University of California, Los Angeles)

2.2 A Framework for Energy-Scalable Communication in High-Density Wireless Networks [p. 36]

R. Min, A. Chandrakasan (Massachusetts Institute of Technology)

2.3 Contents Provider-Assisted Dynamic Voltage Scaling for Low Energy Multimedia Applications [p. 42]

E.-Y. Chung (CSL Stanford University), L. Benini (University of Bologna), G. De Micheli (CSL Stanford University)

Poster Session 1: Technology and Circuits

P1.1 Low-Leakage Asymmetric-Cell SRAM [p. 48]

N. Azizi, A. Moshovos, F.N. Najm (University of Toronto)

P1.2 Managing Leakage for Transient Data: Decay and Quasi-Static 4T Memory Cells [p. 52]

Z. Hu, P. Juang (Princeton University), P. Diodato, S. Kaxiras (Agere Systems), K. Skadron (University of Virginia), M. Martonosi, D. W. Clark (Princeton University)

P1.3 Conditional Pre-Charge Techniques for Power-Efficient Dual-Edge Clocking [p. 56]

N. Nedovic, M. Aleksic, V.G. Oklobdzija (University of California, Davis)

P1.4 Circuit-Level Techniques to Control Gate Leakage for sub-100nm CMOS [p. 60]

F. Hamzaoglu, M.R. Stan (University of Virginia)

P1.5 Modeling and Analysis of Leakage Power Considering Within-Die Process Variation [p. 64]

A. Srivastava, R. Bai, D. Blaauw, D. Sylvester (University of Michigan)

Poster Session 2: System and Software Design

P2.1 Low-Power Approach for Decoding Convolutional Codes with Adaptive Viterbi Algorithm Approximations [p. 68]

R. Henning, C. Chakrabarti (Arizona State University)

P2.2 Power-Aware Source Routing Protocol for Mobile Ad Hoc Networks [p. 72]

M. Maleki, K. Dantu, M. Pedram (University of Southern California)

P2.3 Analyzing Energy Friendly Steady State Phases of Dynamic Application Execution in Terms of Sparse Data Structures [p. 76]

E. G. Daylight (IMEC vzw, Katholieke University Leuven), S. Wuytack, C. Ykman-Couvreur (IMEC vzw), F. Catthoor (IMEC vzw, Katholieke University Leuven)

P2.4 Odd/Even Bus Invert with Two-Phase Transfer for Buses with Coupling [p. 80]

Y. Zhang, J. Lach, K. Skadron, M.R. Stan (University of Virginia)

P2.5 An Intra-Task Dynamic Voltage Scaling Method for SoC Design with Hierarchical FSM and Synchronous Dataflow Model [p. 84]

S. Lee (Seoul National University), S. Yoo (TIMA Lab), K. Choi (Seoul National University)

P2.6 Reducing Access Energy of On-Chip Data Memory Considering Active Data Bitwidth [p. 88]

T. Okuma, Y. Cao, M. Muroyama, H. Yasuura (Kyushu University)

Session 3: Low Power Circuit Techniques

3.1 Energy Recovering Static Memory [p. 92]

J. Kim, C.H. Ziesler, M.C. Papaefthymiou (University of Michigan)

3.2 Low Power Integrated Scan-Retention Mechanism [p. 98]

V. Zyuban, S.V. Kosonocky (IBM T.J. Watson Research Center)

3.3 Closed Loop Adaptive Voltage Scaling Controller for Standard-Cell ASICs [p. 103]

S. Dhar, D. Maksimovic (University of Colorado), B. Kranzen (National Semiconductor)

3.4 Design of a Branch-Based 64-bit Carry-Select Adder in 0.18um Partially Depleted SOI CMOS [p. 108]

A. N¶ve, D. Flandre (Universite Catholique de Louvain), H. Schettler, T. Ludwig, G. Hellner (IBM Entwicklung GmbH)

Session 4: Energy Efficient System Design

4.1 Low-Power Color TFT LCD Display for Hand-Held Embedded Systems [p. 112]

I. Choi, H. Shim, N. Chang (Seoul National University)

4.2 Discharge Current Steering for Battery Lifetime Optimization [p. 118]

L. Benini (Universita di Bologna), A. Macii, E. Macii (Politecnico di Torino), M. Poncino (Universita di Verona)

4.3 Towards Energy-Aware Software-Based Fault Tolerance in Real-Time Systems [p. 124]

O.S. Unsal, I. Koren, C.M. Krishna (University of Massachusetts, Amherst)

Session 5: Memory Subsystem

5.1 Fine-Grain CAM-Tag Cache Resizing Using Miss Tags [p. 130]

M. Zhang, K. Asanovic (MIT Laboratory for Computer Science)

5.2 An Adaptive Serial-Parallel CAM Architecture for Low-Power Cache Blocks [p. 136]

A. Efthymiou, J.D. Garside (University of Manchester)

5.3 Reducing Energy Consumption of Video Memory by Bit-Width Compression [p. 142]

V.G. Moshnyaga, K. Inoue, M. Fukagawa (Fukuoka University),

5.4 A History-Based I-Cache for Low-Energy Multimedia Applications [p. 148]

K. Inoue, V.G. Moshnyaga (Fukuoka University), K. Murakami (Kyushu University)

Session 6: Modeling and Design Issues

6.1 Battery Lifetime Prediction for Energy-Aware Computing [p. 154]

D. Rakhmatov, S. Vrudhula (University of Arizona), D.A. Wallach (Hewlett-Packard Western Research Laboratory)

6.2 Early Evaluation Techniques for Low Power Binding [p. 160]

E. Kursun, A. Srivastava, S.O. Memik, M. Sarrafzadeh (University of California Los Angeles)

6.3 Unified Methodology for Resolving Power-Performance Tradeoffs at the Microarchitectural and Circuit Levels [p. 166]

V. Zyuban, P. Strenski (IBM T.J. Watson Research Center)

Invited Talk

Is Nanoelectronics the Future of Microelectronics? [p. 172]

M. Lundstrom (Purdue University)

Session 7: Microarchitecture Techniques

7.1 Saving Energy with Just In Time Instruction Delivery [p. 178]

T. Karkhanis, J.E. Smith (University of Wisconsin-Madison), P. Bose (IBM T.J. Watson Research Center)

7.2 Tradeoffs in Power-Efficient Issue Queue Design [p. 184]

A. Buyuktosunoglu, D. H. Albonesi (University of Rochester), P. Bose, P.W. Cook, S E. Schuster (IBM T.J. Watson Research Center)

7.3 Reducing Transitions on Memory Buses using Sector-based Encoding Technique [p. 190]

Y. Aghaghiri (University of Southern California), F. Fallah (Fujitsu Laboratories of America), M. Pedram (University of Southern California)

7.4 Energy-Efficient Hybrid Wakeup Logic [p. 196]

M. Huang, J. Renau, J. Torrellas (University of Illinois at Urbana-Champaign)

Session 8: Technology-Driven Power Optimization

8.1 Automated Selective Multi-Threshold Design for Ultra-Low Standby Applications [p. 202]

K. Usami, N. Kawabe, M. Koizumi, K. Seta (Toshiba Corporation Semiconductor Company), T. Furusawa (Toshiba Microelectronics Corporation)

8.2 HA²TSD: Hierarchical Time Slack Distribution for Ultra-Low Power CMOS VLSI [p. 207]

K.-w. Choi, A. Chatterjee (Georgia Institute Technology)

8.3 Runtime Mechanisms for Leakage Current Reduction in CMOS VLSI Circuits [p. 213]

A. Abdollahi (University of Southern California), F. Fallah (Fujitsu Laboratories of America), M. Pedram (University of Southern California)

Embedded Tutorial 1

Future Directions in Clocking Multi-Ghz Systems [p. 219]

V.G. Oklobdzija (University of California), J. Sparso (Technical University of Denmark)

Embedded Tutorial 2

Compilers for Power and Energy Management [p. 220]

U. Kremer (Rutgers University)

Session 9: Analog Electronics

9.1 Oversampled Gain-Boosting [p. 221]

O. Oliaei (Motorola Labs)

9.2 ±0.5V ~ ±1.5V UHF CMOS LV/LP Four-Quadrant Analog Multiplier in Modified Bridged-Triode Scheme [p. 227]

S.C. Li, J.C. Cha (National Yunlin Univ. of Science and Technology)

9.3 A Power and Resolution Adaptive Flash Analog-to-Digital Converter [p. 233]

J. Yoo, D. Lee, K. Choi, J. Kim (Pennsylvania State University)

9.4 Design Techniques for Low Power High Bandwith Upconversion in CMOS [p. 237]

C. De Ranter, M. Steyaert (Katholieke Universiteit Leuven)

Session 10: Design Contest Presentation

Poster Session 3: Logic and Microarchitecture

P3.1 TLB and Snoop Energy-Reduction using Virtual Caches in Low- Power Chip Multiprocessors [p. 243]

M. Ekman (Chalmers University of Technology), F. Dahlgren (Ericsson Mobile Platforms), P. Stenstrûm (Chalmers University of Technology)

P3.2 A Preactivating Mechanism for a VT-CMOS Cache using Address Prediction [p. 247]

R. Fujioka, K. Katayama, R. Kobayashi, H. Ando, T. Shimada (Nagoya University)

P3.3 Dynamic Vt SRAM: A Leakage Tolerant Cache Memory for Low Voltage Microprocessors [p. 251]

C.H. Kim, K. Roy (Purdue University)

P3.4 Asymmetric-Frequency Clustering: A Power-Aware Back-End for High-Performance Processors [p. 255]

A. Baniasadi (Northwestern University), A. Moshovos (University of Toronto)

Poster Session 4: Analysis, Estimation and Optimization

P4.1 Power Analysis Techniques for SoC with Improved Wiring Models [p. 259]

T. Sakamoto, T. Yamada, M. Mukuno, Y. Matsushita, Y. Harada (Sanyo Electric), H. Yasuura (Kyushu University)

P4.2 A Microarchitectural-Level Step-Power Analysis Tool [p. 263]

W. El-Essawy, D.H. Albonesi (University of Rochester), B. Sinharoy (IBM Corporation)

P4.3 Power Estimation of Sequential Circuits using Hierarchical Colored Hardware Petri Net Modeling [p. 267]

A K. Murugavel, N. Ranganathan (University of South Florida)

P4.4 High-Level Area Estimation [p. 271]

K.M. Büyüksahin (University of Illinois at Urbana-Champaign), F. N. Najm (University of Toronto)

P4.5 Retiming-Based Logic Synthesis for Low-Power [p. 275]

Y.-L. Hsu, S.-J. Wang (National Chung-Hsing University)

P4.6 Activity-Sensitive Clock Tree Construction for Low Power [p. 279]

C. Chen, C. Kang (University of Windsor), M. Sarrafzadeh (University of California at Los Angeles)

Invited Talk

Session 11: Signal Processing

11.1 Low-Power VLSI Decoder Architectures for LDPC Codes [p. 284]

11.2 A Low Power Normalized-LMS Decision Feedback Equalizer for a Wireless Packet Modem [p. 290]

11.3 High Performance and Low Power FIR Filter Design based on Sharing Multiplication [p. 295]

11.4 A Low-Power Digital Matched Filter for Spread-Spectrum Systems [p. 301]