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The 11th Asia and South Pacific Design Automation Conference

Friday January 27, 2006

Session 9A High-Level Synthesis (16:00 - 18:05)
Location: Room 411+412
Chair(s): Shigeru Yamashita (NAIST, Japan), Youngsoo Shin (KAIST, Republic of Korea)

9A-1 (Time: 16:00 - 16:25)
TitleTAPHS: Thermal-Aware Unified Physical-Level and High-Level Synthesis
Author*Zhenyu (Peter) Gu (Northwestern Univ., United States), Yonghong Yang (Queen's Univ., Canada), Jia Wang, Robert P. Dick (Northwestern Univ., United States), Li Shang (Queen's Univ., Canada)
Pagepp. 879 - 885
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9A-2 (Time: 16:25 - 16:50)
TitleAn Automated, Efficient and Static Bit-width Optimization Methodology Towards Maximum Bit-width-to-Error Tradeoff With Affine Arithmetic Model
Author*Yu Pu, Yajun Ha (National Univ. of Singapore, Singapore)
Pagepp. 886 - 891
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9A-3 (Time: 16:50 - 17:15)
TitleAbridged Addressing: A Low Power Memory Addressing Strategy
Author*Preeti Ranjan Panda (Indian Inst. of Tech., Delhi, India)
Pagepp. 892 - 897
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9A-4 (Time: 17:15 - 17:40)
TitleUsing Speculative Computation and Parallelizing Techniques to Improve Scheduling of Control based Designs
AuthorRoberto Cordone (Univ. degli studi di Crema, Italy), *Fabrizio Ferrandi, Gianluca Palermo, Marco Domenico Santambrogio, Donatella Sciuto (Politecnico di Milano, Italy)
Pagepp. 898 - 904
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9A-5 (Time: 17:40 - 18:05)
TitleWorst Case Execution Time Analysis for Synthesized Hardware
Author*Jun-hee Yoo, Xingguang Feng, Kiyoung Choi (Seoul National Univ., Republic of Korea), Eui-Young Chung, Kyu-Myung Choi (Samsung Electronics, Republic of Korea)
Pagepp. 905 - 910
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