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The 11th Asia and South Pacific Design Automation Conference

Wednesday January 25, 2006

Session 3A Logic Synthesis (16:00 - 18:05)
Location: Room 411+412
Chair(s): Shinji Kimura (Waseda Univ., Japan), Shih-Chieh Chang (National Tsing Hua Univ., Taiwan)

3A-1 (Time: 16:00 - 16:25)
TitleAn Anytime Symmetry Detection Algorithm for ROBDDs
Author*Neil Kettle, Andy King (Univ. of Kent, Great Britain)
Pagepp. 243 - 248
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3A-2 (Time: 16:25 - 16:50)
TitleHigh Level Equivalence Symmetric Input Identification
Author*Ming-Hong Su, Chun-Yao Wang (National Tsing Hua Univ., Taiwan)
Pagepp. 249 - 253
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3A-3 (Time: 16:50 - 17:15)
TitleFast Multi-Domain Clock Skew Scheduling for Peak Current Reduction
Author*Shih-Hsu Huang, Chia-Ming Chang, Yow-Tyng Nieh (Chung Yuan Christian Univ., Taiwan)
Pagepp. 254 - 259
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3A-4 (Time: 17:15 - 17:40)
TitleLow Area Pipelined Circuits by Multi-clock Cycle Paths and Clock Scheduling
Author*Bakhtiar Affendi Rosdi, Atsushi Takahashi (Tokyo Inst. of Tech., Japan)
Pagepp. 260 - 265
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3A-5 (Time: 17:40 - 18:05)
TitleA Transduction-based Framework to Synthesize RSFQ Circuits
Author*Shigeru Yamashita (NAIST, Japan), Katsunori Tanaka (NEC, Japan), Hideyuki Takada (Kyoto Univ., Japan), Koji Obata, Kazuyoshi Takagi (Nagoya Univ., Japan)
Pagepp. 266 - 272
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