EECS 31/CSE 31/ICS 151 Homework 2 Questions

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Problem 1

Question

(Theorems of Boolean algebra) Give proofs to the following theorems.

  1. Theorem 3(a) and (b)
  2. Theorem 6(a) and (b)

Problem 2

Question

(Theorems and proofs) Using truth tables, prove the validity of the following identies.

  1. (xyz)' = x'+y'+z'

Problem 3

Question

(Boolean functions) Derive truth tables for the following Boolean functions.

  1. F(x, y, z) = (x+z)'
  2. F(x, y, z) = (x+z)'(x+y')

Problem 4

Question

(Boolean algebra) Prove by algebraic manipulation that the following expressions are equivalent.

  1. x'y'+xy = (xy'+x'y)'
  2. x'z+xy = x'y'z+yz+xy

Problem 5

Question

(Algebraic manipulation) Minimize the number of operators in the following Boolean expressions.

  1. x'y'+xy+xy'
  2. (x+y)(x+y')

Problem 6

Question

(Boolean implementations) Implement the XOR function by means of:

  1. NAND gates only
  2. NOR gates only
  3. AND, OR, and NOT gates

Problem 7

Question

(Boolean implementations) Implement x XOR y XOR z using the components in the basic logic library presented in Table 3.14. Find the implementation that has:

  1. The smallest cost
  2. The shortest delay

Problem 8

Question

(Logic Libraries) Using the basic logic library presented in Table3.14, implement the full subtractor that is specified by the following table:


  Xi   Yi   Bi |   Bi+1    Di
------------------------------
  0    0    0  |    0      0
  0    0    1  |    1      1
  0    1    0  |    1      1
  0    1    1  |    1      0
  1    0    0  |    0      1
  1    0    1  |    0      0
  1    1    0  |    0      0
  1    1    1  |    1      1

Find the implementation that has:

  1. The smallest cost
  2. The shortest delay

Problem 9

Question

(Logic Libraries) Redo Problem 3.15 using only the gates that are given in Table 3.15 and 3.16

Problem 10 (3.18)

Question

(Logic Libraries) Redo Problem 3.15 using any of the standard logic gates that are given in Table 3.14, 3.15 and 3.16

Problem 11 (3.19)

Question

(Gate arrays) Using a 3-input NAND gates, derive a logic schematic of a:

  1. full adder
  2. full subtractor