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<A HREF="../../../1997_ss.htm">1997 Compendium Index</A></BR>
DAC 97 :
[ <A HREF="dacabs.htm">Abstracts</A> ]
[ <A HREF="dacsess.htm">Session Index</A> ]
[ <A HREF="dacai.htm">Author Index</A> ]</H3>
<HR>
<H2>TABLE OF CONTENTS DAC 97</H2>
<B>
Sessions:
[<A HREF="#ceo">Panel</A>]
[<A HREF="#sess1">1</A>]
[<A HREF="#sess2">2</A>]
[<A HREF="#sess3">3</A>]
[<A HREF="#sess4">4</A>]
[<A HREF="#sess5">5</A>]
[<A HREF="#sess6">6</A>]
[<A HREF="#sess7">7</A>]
[<A HREF="#sess8">8</A>]
[<A HREF="#sess9">9</A>]
[<A HREF="#sess10">10</A>]
[<A HREF="#sess11">11</A>]
[<A HREF="#sess12">12</A>]
[<A HREF="#sess13">13</A>]
[<A HREF="#sess14">14</A>]
[<A HREF="#sess15">15</A>]
[<A HREF="#sess16">16</A>]
[<A HREF="#sess17">17</A>]
[<A HREF="#sess18">18</A>]
[<A HREF="#sess19">19</A>]
[<A HREF="#sess20">20</A>]
[<A HREF="#sess21">21</A>]
[<A HREF="#sess22">22</A>]
[<A HREF="#sess23">23</A>]
[<A HREF="#sess24">24</A>]
[<A HREF="#sess25">25</A>]
[<A HREF="#sess26">26</A>]
[<A HREF="#sess27">27</A>]
[<A HREF="#sess28">28</A>]
[<A HREF="#sess29">29</A>]
[<A HREF="#sess30">30</A>]
[<A HREF="#sess31">31</A>]
[<A HREF="#sess32">32</A>]
[<A HREF="#sess33">33</A>]
[<A HREF="#sess34">34</A>]
[<A HREF="#sess35">35</A>]
[<A HREF="#sess36">36</A>]
[<A HREF="#sess37">37</A>]
[<A HREF="#sess38">38</A>]
[<A HREF="#sess39">39</A>]
[<A HREF="#sess40">40</A>]
[<A HREF="#sess41">41</A>]
[<A HREF="#sess42">42</A>]
[<A HREF="#sess43">43</A>]
[<A HREF="#sess44">44</A>]
[<A HREF="#sess45">45</A>]
[<A HREF="#sess46">46</A>]
[<A HREF="#sess47">47</A>]
[<A HREF="#sess48">48</A>]
[<A HREF="#sess49">49</A>]
[<A HREF="#tutorials">Tutorials</A>]
<P>
<A HREF="../../psfiles/welcome.psz">General Chair's Welcome</A><BR>
<A HREF="../../psfiles/execom.psz">Executive Committee</A><BR>
<A HREF="../../psfiles/techcom.psz">Technical Program Committee</A><BR>
<A HREF="../../psfiles/bestppr.psz">1997 Best Paper Award</A><BR>
<A HREF="../../psfiles/bestppr.psz">ACSEE Undergraduate Scholarships</A><BR>
<A HREF="../../psfiles/cfp.psz">35th Call for Papers</A><BR>
<A HREF="../../psfiles/scholar.psz">Design Automation Conference Scholarship Awards</A><BR>
<A HREF="../../psfiles/scholar.psz">Meritorious Service Award</A><BR>
<A HREF="../../psfiles/reviewer.psz">Reviewers</A><BR>
<A HREF="../../psfiles/keynotem.psz">Opening Keynote Address - <I> Scott G. McNealy</I></A><BR>
<A HREF="../../psfiles/keynotea.psz">Opening Keynote Address - <I> Michael A. Aymar</I></A><BR>
<P>
<HR>
<H2>Panel :
<A HREF="../../pdffiles/98_0.pdf" NAME="ceo"><IMG SRC="../../../../../icons/pdficon.gif"></A>
<A HREF="../../psfiles/98_0.psz">
AN EXECUTIVE VIEW OF THE EDA INDUSTRY [p 1]<BR>
</A></H2>
Chair: <I>A. Richard Newton</I><BR>
Organizers: <I>Mike Murray</I><BR>
Panelists: <I>Joseph Costello, Aart de Geus, William Herman,
Gerald Hsu, Keith Lobo, Walden Rhines</I><P>
<HR>
<H2>Session 1:<A HREF="dacabs.htm#sess1" NAME="sess1">
SEQUENTIAL SYNTHESIS
</A></H2>
Chair: <I>Richard L. Rudell</I><BR>
Organizers: <I>Fabio Somenzi, Sharad Malik</I><P>
<DL>
<DT>
<A HREF="dacabs.htm#01_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/01_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
<a href="http://www.ee.iastate.edu/~sachin/DAC97.html"><img src="../../../../../icons/url.gif"></a>
<A HREF="../../psfiles/01_1.psz">
1.1 An Improved Algorithm For Minimum-Area Retiming [p 2]</A><BR>
<DD><I>Naresh Maheshwari, Sachin S. Sapatnekar</I><P>
<DT>
<A HREF="dacabs.htm#01_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/01_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
<A HREF="../../psfiles/01_2.psz">
1.2 Efficient Latch Optimization Using Exclusive Sets [p 8]</A><BR>
<DD><I>Ellen M. Sentovich, Horia Toma, Gérard Berry</I><P>
<DT>
<A HREF="dacabs.htm#01_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/01_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
<A HREF="../../psfiles/01_3.psz">
1.3 Sequence Compaction for Probabilistic Analysis of Finite-State Machines [p 12]</A><BR>
<DD><I>Diana Marculescu, Radu Marculescu, Massoud Pedram</I><P>
<DT>
<A HREF="dacabs.htm#01_4"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/01_4.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
<A HREF="../../psfiles/01_4.psz">
1.4 Synthesis of Speed-Independent Circuits from STG-unfolding Segment [p 16]</A><BR>
<DD><I>Alexei Semenov, Alexandre Yakovlev, Enric Pastor, Marco A. Pena,
Jordi Cortadella</I><P>
<DT>
<A HREF="dacabs.htm#01_5"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/01_5.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
<A HREF="../../psfiles/01_5.psz">
1.5 Telescopic Units: Increasing the Average Throughput of Pipelined Designs by
Adaptive Latency Control [p 22]</A><BR>
<DD><I>Luca Benini, Enrico Macii, Massimo Poncino</I><P>
</DL>
<HR>
<H2>Session 2:<A HREF="dacabs.htm#sess2" NAME="sess2">
INTERCONNECT MODELING
</A></H2>
Chair: <I>Lawrence T. Pileggi</I><BR>
Organizers: <I>Andrew Yang, Jacob White</I><P>
<DL>
<DT>
<A HREF="dacabs.htm#02_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/02_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
<A HREF="../../psfiles/02_1.psz">
2.1 Zeros and Passivity of Arnoldi-Reduced-Order Models for Interconnect Networks [p 28]</A><BR>
<DD><I>Ibrahim M. Elfadel, David D. Ling</I><P>
<DT>
<A HREF="dacabs.htm#02_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/02_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
<A HREF="../../psfiles/02_2.psz">
2.2 Preservation of Passivity During RLC Network Reduction via Split Congruence
Transformations [p 34]</A><BR>
<DD><I>Kevin J. Kerns, Andrew T. Yang</I><P>
<DT>
<A HREF="dacabs.htm#02_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/02_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
<A HREF="../../psfiles/02_3.psz">
2.3 Lumped Interconnect Models Via Gaussian Quadrature [p 40]</A><BR>
<DD><I>Keith Nabors, Tze-Ting Fang, Hung-Wen Chang, Kenneth S. Kundert, Jacob K. White</I><P>
<DT>
<A HREF="dacabs.htm#02_4"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/02_4.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
<A HREF="../../psfiles/02_4.psz">
2.4 Calculating Worst-Case Gate Delays Due to Dominant Capacitance Coupling [p 46]</A><BR>
<DD><I>Florentin Dartu, Lawrence T. Pileggi</I><P>
</DL>
<HR>
<H2>Session 3:<A HREF="dacabs.htm#sess3" NAME="sess3">
NOVEL TECHNIQUES FOR SOFTWARE SCHEDULING
</A></H2>
Chair: <I>Gaetano Borriello</I><BR>
Organizers: <I>Rajesh K. Gupta, Luciano Lavagno</I><P>
<DL>
<DT>
<A HREF="dacabs.htm#03_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/03_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
<A HREF="../../psfiles/03_1.psz">
3.1 Schedule Validation for Embedded Reactive Real-Time Systems [p 52]</A><BR>
<DD><I>Felice Balarin, Alberto Sangiovanni-Vincentelli</I><P>
<DT>
<A HREF="dacabs.htm#03_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/03_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
<A HREF="../../psfiles/03_2.psz">
3.2 Incorporating Imprecise Computation into System-Level Design Of
Application-Specific Heterogeneous Multiprocessors [p 58]</A><BR>
<DD><I>Yosef Gavriel Tirat-Gefen, Diogenes C. Silva, Alice C. Parker</I><P>
<DT>
<A HREF="dacabs.htm#03_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/03_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
<A HREF="../../psfiles/03_3.psz">
3.3 Data Memory Minimisation for Synchronous Data Flow Graphs Emulated on
DSP-FPGA Targets [p 64]</A><BR>
<DD><I>Marleen Adé, Rudy Lauwereins, J.A. Peperstraete</I><P>
<DT>
<A HREF="dacabs.htm#03_4"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/03_4.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
<A HREF="../../psfiles/03_4.psz">
3.4 An Efficient Implementation of Reactivity for Modeling Hardware in the
Scenic Design Environment [p 70]</A><BR>
<DD><I>Stan Liao, Steve Tjiang, Rajesh K. Gupta</I><P>
</DL>
<HR>
<H2>Session 4:<BR>
<A HREF="dacabs.htm#sess4" NAME="sess4"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/04_0.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
<A HREF="../../psfiles/04_0.psz">
PANEL: LOW-POWER DESIGN TOOLS: WHERE IS THE IMPACT? [p 76]
</A></H2>
Chair: <I>Jan M. Rabaey</I><BR>
Organizer: <I>Nanette Collins</I><BR>
Panelists: <I>Bill Bell, Jerry Frenkil, Vassilios Gerousis,
Massoud Pedram, Deo Singh, Jim Sproch</I><P>
<DL>
<DT>
<A HREF="dacabs.htm#04_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/04_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
<A HREF="../../psfiles/04_1.psz">
4.1 Embedded Tutorial: Tools and Methodologies for Low Power Design [p 82]</A><BR>
<DD><I>Jerry Frenkil</I><P>
</DL>
<HR>
<H2>Session 5:<A HREF="dacabs.htm#sess5" NAME="sess5">
SIMULATION TECHNIQUES FOR MICROPROCESSORS
</A></H2>
Chair: <I>Haruyuki Tago</I><BR>
Organizers: <I>Haruyuki Tago, Neil Weste</I><P>
<DL>
<DT>
<A HREF="dacabs.htm#05_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/05_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
<A HREF="../../psfiles/05_1.psz">
5.1 A C-Based RTL Design Verification Methodology for Complex Microprocessor [p 83]</A><BR>
<DD><I>Joon-Seo Yim, Yoon-Ho Hwang, Chang-Jae Park, Hoon Choi, Woo-Seung Yang,
Hun-Seung Oh, In-Cheol Park, Chong-Min Kyung</I><P>
<DT>
<A HREF="dacabs.htm#05_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/05_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
<A HREF="../../psfiles/05_2.psz">
5.2 Hierarchical Random Simulation Approach for the Verification Of S/390 CMOS
Multiprocessors [p 89]</A><BR>
<DD><I>Jörg Walter, Jens Leenstra, Gerhard Döttling, Bernd Leppla,
Hans-Jürgen Münster, Kevin Kark, Bruce Wile</I><P>
<DT>
<A HREF="dacabs.htm#05_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/05_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
<A HREF="../../psfiles/05_3.psz">
5.3 Efficient Testing of Clock Regenerator Circuits in Scan Designs [p 95]</A><BR>
<DD><I>Rajesh Raina, Robert Bailey, Charles Njinda, Robert Molyneaux, Charlie Beh</I><P>
<DT>
<A HREF="dacabs.htm#05_4"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/05_4.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
<A HREF="../../psfiles/05_4.psz">
5.4 A Real-Time RTL Engineering-Change Method Supporting On-Line Debugging for
Logic-Emulation Applications [p 101]</A><BR>
<DD><I>Wen-Jong Fang, Allen C.-H. Wu, Ti-Yen Yen</I><P>
</DL>
<HR>
<H2>Session 6:<A HREF="dacabs.htm#sess6" NAME="sess6">
COMBINATIONAL LOGIC SYNTHESIS
</A></H2>
Chair: <I>Hamid Savoj</I><BR>
Organizers: <I>Andreas Kuehlmann, Massoud Pedram</I><P>
<DL>
<DT>
<A HREF="dacabs.htm#06_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/06_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
<A HREF="../../psfiles/06_1.psz">
6.1 A Graph-Based Synthesis Algorithm for AND/XOR Networks [p 107]</A><BR>
<DD><I>Yibin Ye, Kaushik Roy</I><P>
<DT>
<A HREF="dacabs.htm#06_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/06_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
<A HREF="../../psfiles/06_2.psz">
6.2 Optimizing Designs Containing Black Boxes [p 113]</A><BR>
<DD><I>Tai-Hung Liu, Khurram Sajid, Adnan Aziz, Vigyan Singhal</I><P>
<DT>
<A HREF="dacabs.htm#06_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/06_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
<A HREF="../../psfiles/06_3.psz">
6.3 Solving Covering Problems Using LPR-Based Lower Bounds [p 117]</A><BR>
<DD><I>Stan Liao, Srinivas Devadas</I><P>
<DT>
<A HREF="dacabs.htm#06_4"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/06_4.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
<A HREF="../../psfiles/06_4.psz">
6.4 Exact Coloring of Real-Life Graphs is Easy [p 121]</A><BR>
<DD><I>Olivier Coudert</I><P>
</DL>
<HR>
<H2>Session 7:<A HREF="dacabs.htm#sess7" NAME="sess7">
INTERCONNECT PARASITIC EXTRACTION
</A></H2>
Chair: <I>Andrew T. Yang</I><BR>
Organizers: <I>Jacob White, Jason Cong</I><P>
<DL>
<DT>
<A HREF="dacabs.htm#07_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/07_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
<A HREF="../../psfiles/07_1.psz">
7.1 Hierarchical 2-D Field Solution for Capacitance Extraction for VLSI
Interconnect Modeling [p 127]</A><BR>
<DD><I>E. Aykut Dengi, Ronald A. Rohrer</I><P>
<DT>
<A HREF="dacabs.htm#07_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/07_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
<A HREF="../../psfiles/07_2.psz">
7.2 Bounds for BEM Capacitance Extraction [p 133]</A><BR>
<DD><I>Michael W. Beattie, Lawrence T. Pileggi</I><P>
<DT>
<A HREF="dacabs.htm#07_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/07_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
<A HREF="../../psfiles/07_3.psz">
7.3 SPIE: Sparse Partial Inductance Extraction [p 137]</A><BR>
<DD><I>Zhijiang He, Mustafa Celik, Lawrence Pileggi</I><P>
<DT>
<A HREF="dacabs.htm#07_4"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/07_4.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
<A HREF="../../psfiles/07_4.psz">
7.4 A Fast Method of Moments Solver For Efficient Parameter Extraction Of MCMs [p 141]</A><BR>
<DD><I>Sharad Kapur, Jinsong Zhao</I><P>
</DL>
<HR>
<H2>Session 8:<A HREF="dacabs.htm#sess8" NAME="sess8">
ADVANCES IN TIMING ANALYSIS FOR EMBEDDED SOFTWARE
</A></H2>
Chair: <I>Wendell Baker, Hiroto Yasuura</I><BR>
Organizers: <I>Rajesh K. Gupta, Luciano Lavagno</I><P>
<DL>
<DT>
<A HREF="dacabs.htm#08_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/08_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
<A HREF="../../psfiles/08_1.psz">
8.1 Embedded Tutorial: Static Timing Analysis of Embedded Software [p 147]</A><BR>
<DD><I>Sharad Malik, Margaret Martonosi, Yau-Tsun Steven Li</I><P>
<DT>
<A HREF="dacabs.htm#08_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/08_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
<a href="http://www.ee.princeton.edu/~wolf/codesign/"><img src="../../../../../icons/url.gif"></a>
<A HREF="../../psfiles/08_2.psz">
8.2 A Task-Level Hierarchical Memory Model for System Synthesis of
Multiprocessors [p 153]</A><BR>
<DD><I>Yanbing Li, Wayne Wolf</I><P>
<DT>
<A HREF="dacabs.htm#08_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/08_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
<A HREF="../../psfiles/08_3.psz">
8.3 Predicting Timing Behavior In Architectural Design Exploration of Real-Time
Embedded Systems [p 157]</A><BR>
<DD><I>Rajeshkumar Sambandam, Xiaobo Hu</I><P>
</DL>
<HR>
<H2>Session 9:<A HREF="dacabs.htm#sess9" NAME="sess9">
APPLICATIONS OF FORMAL VERIFICATION
</A></H2>
Chair: <I>Andreas Kuehlmann</I><BR>
Organizers: <I>Haruyuki Tago, Neil Weste</I><P>
<DL>
<DT>
<A HREF="dacabs.htm#09_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/09_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
<A HREF="../../psfiles/09_1.psz">
9.1 Formal Verification of a Superscalar Execution Unit [p 161]</A><BR>
<DD><I>Kyle L. Nelson, Alok Jain, Randal E. Bryant</I><P>
<DT>
<A HREF="dacabs.htm#09_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/09_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
<a href="http://www.cs.cmu.edu/~pandey/dac97.html"><img src="../../../../../icons/url.gif"></a>
<A HREF="../../psfiles/09_2.psz">
9.2 Formal Verification of Content Addressable Memories using Symbolic
Trajectory Evaluation [p 167]</A><BR>
<DD><I>Manish Pandey, Richard Raimi, Randal E. Bryant, Magdy S. Abadir</I><P>
<DT>
<A HREF="dacabs.htm#09_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/09_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
<A HREF="../../psfiles/09_3.psz">
9.3 Formal Verification of FIRE: A Case Study [p 173]</A><BR>
<DD><I>Jae-Young Jang, Shaz Qadeer, Matt Kaufmann, Carl Pixley</I><P>
</DL>
<HR>
<H2>Session 10:<A HREF="dacabs.htm#sess10" NAME="sess10">
SYSTEM-LEVEL EXPLORATION AND REFINEMENT
</A></H2>
Chair: <I>Ivo Bolsens</I><BR>
Organizers: <I>Ivo Bolsens, Anders Forsen</I><P>
<DL>
<DT>
<A HREF="dacabs.htm#10_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/10_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
<A HREF="../../psfiles/10_1.psz">
10.1 Interface-Based Design [p 178]</A><BR>
<DD><I>James A. Rowson, Alberto Sangiovanni-Vincentelli</I><P>
<DT>
<A HREF="dacabs.htm#10_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/10_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
<a href="http://csis.ee.virginia.edu/~rassp"><img src="../../../../../icons/url.gif"></a>
<A HREF="../../psfiles/10_2.psz">
10.2 An Integrated Design Environment for Performance and Dependability
Analysis [p 184]</A><BR>
<DD><I>Robert H. Klenke, Moshe Meyassed, James H. Aylor, Barry W. Johnson,
Ramesh Rao, Anup Ghosh</I><P>
<DT>
<A HREF="dacabs.htm#10_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/10_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
<A HREF="../../psfiles/10_3.psz">
10.3 A Dynamic Design Estimation and Exploration Environment [p 190]</A><BR>
<DD><I>Ole Bentz, Jan M. Rabaey, David B. Lidsky</I><P>
</DL>
<HR>
<H2>Session 11:<A HREF="dacabs.htm#sess11" NAME="sess11">
BINARY DECISION DIAGRAMS
</A></H2>
Chair: <I>Andreas Kuehlmann</I><BR>
Organizers: <I>Massoud Pedram, Andreas Kuehlmann</I><P>
<DL>
<DT>
<A HREF="dacabs.htm#11_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/11_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
<A HREF="../../psfiles/11_1.psz">
11.1 Remembrance of Things Past: Locality and Memory in BDDs [p 196]</A><BR>
<DD><I>Srilatha Manne, Dirk Grunwald, Fabio Somenzi</I><P>
<DT>
<A HREF="dacabs.htm#11_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/11_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
<A HREF="../../psfiles/11_2.psz">
11.2 Linear Sifting of Decision Diagrams [p 202]</A><BR>
<DD><I>Christoph Meinel, Fabio Somenzi, Thorsten Theobald</I><P>
<DT>
<A HREF="dacabs.htm#11_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/11_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
<A HREF="../../psfiles/11_3.psz">
11.3 Safe BDD Minimization Using Don't Cares [p 208]</A><BR>
<DD><I>Youpyo Hong, Peter Beerel, Jerry R. Burch, Kenneth L. McMillan</I><P>
</DL>
<HR>
<H2>Session 12:<A HREF="dacabs.htm#sess12" NAME="sess12">
TIMING ANALYSIS
</A></H2>
Chair: <I>Karem A. Sakallah</I><BR>
Organizers: <I>Karem Sakallah, Sharad Malik</I><P>
<DL>
<DT>
<A HREF="dacabs.htm#12_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/12_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
<A HREF="../../psfiles/12_1.psz">
12.1 Timing Optimization for Multi-Source Nets: Characterization and Optimal
Repeater Insertion [p 214]</A><BR>
<DD><I>John Lillis, Chung-Kuan Cheng</I><P>
<DT>
<A HREF="dacabs.htm#12_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/12_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
<A HREF="../../psfiles/12_2.psz">
12.2 Exact Required Time Analysis via False Path Detection [p 220]</A><BR>
<DD><I>Yuji Kukimoto, Robert K. Brayton</I><P>
<DT>
<A HREF="dacabs.htm#12_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/12_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
<a href="http://www.cs.swt.edu/papers/dac97/"><img src="../../../../../icons/url.gif"></a>
<A HREF="../../psfiles/12_3.psz">
12.3 Symbolic Timing Verification of Timing Diagrams using Presburger Formulas [p 226]</A><BR>
<DD><I>Tod Amon, Gaetano Borriello, Taokuan Hu, Jiwen Liu</I><P>
</DL>
<HR>
<H2>Session 13:<BR>
<A HREF="dacabs.htm#sess13" NAME="sess13"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/13_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
<A HREF="../../psfiles/13_1.psz">
EMBEDDED TUTORIAL: CODE GENERATION FOR CORE PROCESSORS [p 232]
</A></H2>
Chair: <I>Peter Marwedel</I><BR>
Organizers: <I>Giovanni DeMicheli</I><BR>
Presenter: <I>Peter Marwedel</I><P>
<HR>
<H2>Session 14: <BR>
<A HREF="dacabs.htm#sess14" NAME="sess14"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/14_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
<A HREF="../../psfiles/14_1.psz">
PANEL: PHYSICAL DESIGN AND SYNTHESIS: MERGE OR DIE ! [p 238]
</A></H2>
Chair: <I>Massoud Pedram</I><BR>
Organizer: <I>Massoud Pedram</I><BR>
Panelists: <I>Richard G. Bushroe, Raul Camposano, Giovanni
De Micheli, Antun Domic, Chi-Ping Hsu, Michael Jackson</I><P>
<HR>
<H2>Session 15:<A HREF="dacabs.htm#sess15" NAME="sess15">
SYSTEM-LEVEL OPTIMIZATION AND VERIFICATION
</A></H2>
Chair: <I>Phil Duncan</I><BR>
Organizers: <I>Ivo Bolsens, Jim Rowsen</I><P>
<DL>
<DT>
<A HREF="dacabs.htm#15_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/15_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
<A HREF="../../psfiles/15_1.psz">
15.1 Interface Timing Verification Drives System Design [p 240]</A><BR>
<DD><I>Ajay J. Daga, Peter R. Suaris</I><P>
<DT>
<A HREF="dacabs.htm#15_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/15_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
<A HREF="../../psfiles/15_2.psz">
15.2 Memory-CPU Size Optimization for Embedded System Designs [p 246]</A><BR>
<DD><I>Barry Shackleford, Mitsuhiro Yasuda, Etsuko Okushi, Hisao Koizumi,
Hiroyuki Tomiyama, Hiroto Yasuura</I><P>
<DT>
<A HREF="dacabs.htm#15_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/15_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
<A HREF="../../psfiles/15_3.psz">
15.3 Methodology for Behavioral Synthesis-based Algorithm-Level Design Space
Exploration: DCT Case Study [p 252]</A><BR>
<DD><I>Miodrag Potkonjak, Kyosun Kim, Ramesh Karri</I><P>
</DL>
<HR>
<H2>Session 16:<A HREF="dacabs.htm#sess16" NAME="sess16">
FORMAL VERIFICATION
</A></H2>
Chair: <I>Fabio Somenzi</I><BR>
Organizers: <I>Fabio Somenzi, Andreas Kuehlmann</I><P>
<DL>
<DT>
<A HREF="dacabs.htm#16_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/16_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
<A HREF="../../psfiles/16_1.psz">
16.1 Embedded Tutorial: Formal Verification in a Commercial Setting [p 258]</A><BR>
<DD><I>R.P. Kurshan</I><P>
<DT>
<A HREF="dacabs.htm#16_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/16_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
<A HREF="../../psfiles/16_2.psz">
16.2 Equivalence Checking Using Cuts and Heaps [p 263]</A><BR>
<DD><I>Andreas Kuehlmann, Florian Krohm</I><P>
</DL>
<HR>
<H2>Session 17:<A HREF="dacabs.htm#sess17" NAME="sess17">
ANALOG SIMULATION
</A></H2>
Chair: <I>Giorgio Casinovi</I><BR>
Organizers: <I>Jacob White, Hidetoshi Onodera</I><P>
<DL>
<DT>
<A HREF="dacabs.htm#17_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/17_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
<A HREF="../../psfiles/17_1.psz">
17.1 Efficient Methods for Simulating Highly Nonlinear Multi-Rate Circuits [p 269]</A><BR>
<DD><I>Jaijeet Roychowdhury</I><P>
<DT>
<A HREF="dacabs.htm#17_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/17_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
<A HREF="../../psfiles/17_2.psz">
17.2 Rapid Frequency-Domain Analog Fault Simulation Under Parameter Tolerances [p 275]</A><BR>
<DD><I>Michael W. Tian, C.-J. Richard Shi</I><P>
<DT>
<A HREF="dacabs.htm#17_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/17_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
<A HREF="../../psfiles/17_3.psz">
17.3 SWITTEST: Automatic Switch-Level Fault Simulation and Test Evaluation of
Switched-Capacitor Systems [p 281]</A><BR>
<DD><I>S. Mir, A. Rueda, T. Olbrich, E. Peralías, J.L. Huertas</I><P>
</DL>
<HR>
<H2>Session 18:<A HREF="dacabs.htm#sess18" NAME="sess18">
SOFTWARE SYNTHESIS FOR EMBEDDED SYSTEMS
</A></H2>
Chair: <I>Sharad Malik</I><BR>
Organizers: <I>Sharad Malik, Luciano Lavagno</I><P>
<DL>
<DT>
<A HREF="dacabs.htm#18_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/18_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
<A HREF="../../psfiles/18_1.psz">
18.1 Analysis and Evaluation of Address Arithmetic Capabilities in Custom DSP
Architectures [p 287]</A><BR>
<DD><I>Ashok Sudarsanam, Stan Liao, Srinivas Devadas</I><P>
<DT>
<A HREF="dacabs.htm#18_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/18_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
<a href="http://www.ert.rwth-aachen.de/Personen/willems.html"><img src="../../../../../icons/url.gif"></a>
<A HREF="../../psfiles/18_2.psz">
18.2 System Level Fixed-Point Design Based on an Interpolative Approach [p 293]</A><BR>
<DD><I>Markus Willems, Volker Bürsgens, Holger Keding, Thorsten Grötker, Heinrich Meyr</I><P>
<DT>
<A HREF="dacabs.htm#18_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/18_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
<a href="http://rle-vlsi.mit.edu/spam"><img src="../../../../../icons/url.gif"></a>
<A HREF="../../psfiles/18_3.psz">
18.3 ISDL: An Instruction Set Description Language for Retargetability [p 299]</A><BR>
<DD><I>George Hadjiyiannis, Silvina Hanono, Srinivas Devadas</I><P>
<DT>
<A HREF="dacabs.htm#18_4"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/18_4.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
<A HREF="../../psfiles/18_4.psz">
18.4 Generation of Software Tools from Processor Descriptions for
Hardware/Software Codesign [p 303]</A><BR>
<DD><I>Mark R. Hartoog, James A. Rowson, Prakash D. Reddy, Soumya Desai,
Douglas D. Dunlop, Edwin A. Harcourt, Neeti Khullar</I><P>
</DL>
<HR>
<H2>Session 19:<A HREF="dacabs.htm#sess19" NAME="sess19">
EXPERIENCES IN SYSTEM DESIGN AND EDUCATION AT UNIVERSITIES
</A></H2>
Chair: <I>Jan M. Rabaey, Anantha Chandrakasan</I><BR>
Organizers: <I>Jan M. Rabaey</I><P>
<DL>
<DT>
<A HREF="dacabs.htm#19_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/19_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
<A HREF="../../psfiles/19_1.psz">
19.1 Education for the Deep-Submicron Age: Business As Usual ? [p 307]</A><BR>
<DD><I>Hugo De Man</I><P>
<DT>
<A HREF="dacabs.htm#19_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/19_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
<A HREF="../../psfiles/19_2.psz">
19.2 InfoPad: An Experiment in System Level Design And Integration [p 313]</A><BR>
<DD><I>Robert W. Brodersen</I><P>
<DT>
<A HREF="dacabs.htm#19_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/19_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
<A HREF="../../psfiles/19_3.psz">
19.3 Very Rapid Prototyping of Wearable Computers: A Case Study of Custom
versus Off-the-Shelf Design Methodologies [p 315]</A><BR>
<DD><I>Asim Smailagic, Daniel P. Siewiorek, Richard Martin, John Stivoric</I><P>
</DL>
<HR>
<H2>Session 20:<A HREF="dacabs.htm#sess20" NAME="sess20">
STANDARD CELL AND PHYSICAL DESIGN METHODS
</A></H2>
Chair: <I>Neil Weste</I><BR>
Organizers: <I>Neil Weste, Randolph Harr</I><P>
<DL>
<DT>
<A HREF="dacabs.htm#20_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/20_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
<A HREF="../../psfiles/20_1.psz">
20.1 CAD at the Design-Manufacturing Interface [p 321]</A><BR>
<DD><I>H.T. Heineken, J. Khare, W. Maly, P.K. Nag, C. Ouyang, W.A. Pleskacz</I><P>
<DT>
<A HREF="dacabs.htm#20_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/20_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
<A HREF="../../psfiles/20_2.psz">
20.2 CELLERITY - A Fully Automatic Layout Synthesis System for Standard Cell
Libraries [p 327]</A><BR>
<DD><I>Mohan Guruswamy, Robert L. Maziasz, Daniel Dulitz, Srilata Raman,
Venkat Chiluvuri, Andrea Fernandez, Larry G. Jones</I><P>
<DT>
<A HREF="dacabs.htm#20_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/20_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
<A HREF="../../psfiles/20_3.psz">
20.3 Developing a Concurrent Methodology For Standard-Cell Library Generation [p 333]</A><BR>
<DD><I>Donald G. Baltus, Thomas Varga, Robert Armstrong, John Duh, T.G. Matheson</I><P>
<DT>
<A HREF="dacabs.htm#20_4"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/20_4.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
<A HREF="../../psfiles/20_4.psz">
20.4 A Fast And Accurate Technique to Optimize Characterization Tables for
High-Level Synthesis [p 337]</A><BR>
<DD><I>John F. Croix, Martin D.F Wong</I><P>
</DL>
<HR>
<H2>Session 21:<A HREF="dacabs.htm#sess21" NAME="sess21">
MODELING AND TRANSFORMATIONS IN SYNTHESIS
</A></H2>
Chair: <I>David Ku</I><BR>
Organizers: <I>Kazutoshi Wakabayashi, Raul Camposano</I><P>
<DL>
<DT>
<A HREF="dacabs.htm#21_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/21_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
<a href="http://www.ics.uci.edu/~jian/papers/DAC97-21-1.html"><img src="../../../../../icons/url.gif"></a>
<A HREF="../../psfiles/21_1.psz">
21.1 Limited Exception Modeling and its Use in Presynthesis Optimizations [p 341]</A><BR>
<DD><I>Jian Li, Rajesh K. Gupta</I><P>
<DT>
<A HREF="dacabs.htm#21_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/21_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
<A HREF="../../psfiles/21_2.psz">
21.2 Potential-Driven Statistical Ordering Of Transformations [p 347]</A><BR>
<DD><I>Inki Hong, Darko Kirovski, and Miodrag Potkonjak</I><P>
<DT>
<A HREF="dacabs.htm#21_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/21_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
<A HREF="../../psfiles/21_3.psz">
21.3 Synthesis of Application Specific Programmable Processors [p 353]</A><BR>
<DD><I>Kyosun Kim, Ramesh Karri, Miodrag Potkonjak</I><P>
<DT>
<A HREF="dacabs.htm#21_4"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/21_4.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
<A HREF="../../psfiles/21_4.psz">
21.4 Symbolic Evaluation of Performance Models for Tradeoff Visualization [p 359]</A><BR>
<DD><I>Jeffrey Walrath, Ranga Vemuri</I><P>
</DL>
<HR>
<H2>Session 22:<A HREF="dacabs.htm#sess22" NAME="sess22">
STATISTICAL POWER ESTIMATION TECHNIQUES
</A></H2>
Chair: <I>Luca Benini</I><BR>
Organizers: <I>Massoud Pedram, Andrew Yang</I><P>
<DL>
<DT>
<A HREF="dacabs.htm#22_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/22_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
<A HREF="../../psfiles/22_1.psz">
22.1 Power Macromodeling for High Level Power Estimation [p 365]</A><BR>
<DD><I>Subodh Gupta, Farid N. Najm</I><P>
<DT>
<A HREF="dacabs.htm#22_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/22_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
<A HREF="../../psfiles/22_2.psz">
22.2 Statistical Estimation of the Cumulative Distribution Function for Power
Dissipation in VLSI Circuits [p 371]</A><BR>
<DD><I>Chih-Shun Ding, Qing Wu, Cheng-Ta Hsieh, Massoud Pedram</I><P>
<DT>
<A HREF="dacabs.htm#22_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/22_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
<A HREF="../../psfiles/22_3.psz">
22.3 Statistical Estimation of Average Power Dissipation in Sequential Circuits [p 377]</A><BR>
<DD><I>Li-Pen Yuan, Chin-Chi Teng, Sung-Mo Kang</I><P>
<DT>
<A HREF="dacabs.htm#22_4"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/22_4.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
<A HREF="../../psfiles/22_4.psz">
22.4 Vector Generation for Maximum Instantaneous Current Through Supply Lines
for CMOS Circuits [p 383]</A><BR>
<DD><I>Angela Krstic, Kwang-Ting Cheng</I><P>
</DL>
<HR>
<H2>Session 23:<A HREF="dacabs.htm#sess23" NAME="sess23">
CO-SIMULATION
</A></H2>
Chair: <I>Kunle Olukotun</I><BR>
Organizers: <I>Rajesh Gupta, Kunle Olukton</I><P>
<DL>
<DT>
<A HREF="dacabs.htm#23_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/23_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
<A HREF="../../psfiles/23_1.psz">
23.1 Fast Hardware/Software Co-Simulation for Virtual Prototyping and Trade-Off
Analysis [p 389]</A><BR>
<DD><I>Claudio Passerone, Luciano Lavagno, Massimiliano Chiodo, Alberto
Sangiovanni-Vincentelli</I><P>
<DT>
<A HREF="dacabs.htm#23_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/23_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
<A HREF="../../psfiles/23_2.psz">
23.2 Dynamic Communication Models in Embedded System Co-Simulation [p 395]</A><BR>
<DD><I>Ken Hines, Gaetano Borriello</I><P>
</DL>
<HR>
<H2>Session 24:<BR>
<A HREF="dacabs.htm#sess24" NAME="sess"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/24_0.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
<A HREF="../../psfiles/24_0.psz">
PANEL: CHALLENGES IN WORLDWIDE IP REUSE [p 401]
</A></H2>
Chair: <I>Rita Glover</I><BR>
Organizers: <I>Takahide Inoue, Rita Glover, John Teets</I><BR>
Panelists: <I>Doug Fairbairn, Larry Cooke, Steve Schulz, Takahide Inoue, Raj Raghavan,
Jean-Louis Bories, Wally Rhines</I><P>
<DL>
<DT>
24.1 Embedded Tutorial: Applying VSIA Standards to System on Chip Design<BR>
</DL>
<HR>
<H2>Session 25:<A HREF="dacabs.htm#sess25" NAME="sess25">
EMERGING TECHNOLOGIES AND ARCHITECTURES FOR LOW POWER
</A></H2>
Chair: <I>Vivek Tiwari</I><BR>
Organizers: <I>Anatha Chandrakasan, Robert C. Frye</I><P>
<DL>
<DT>
<A HREF="dacabs.htm#25_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/25_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
<A HREF="../../psfiles/25_1.psz">
25.1 Device-Circuit Optimization for Minimal Energy and Power Consumption in
CMOS Random Logic Networks [p 403]</A><BR>
<DD><I>Pankaj Pant, Vivek De, Abhijit Chatterjee</I><P>
<DT>
<A HREF="dacabs.htm#25_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/25_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
<A HREF="../../psfiles/25_2.psz">
25.2 Transisitor Sizing Issues and Tool For Multi-Threshold CMOS Technology [p 409]</A><BR>
<DD><I>James Kao, Anantha Chandrakasan, Dimitri Antoniadis</I><P>
<DT>
<A HREF="dacabs.htm#25_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/25_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
<A HREF="../../psfiles/25_3.psz">
25.3 Architectural Exploration Using Verilog-Based Power Estimation: A Case
Study Of The IDCT [p 415]</A><BR>
<DD><I>Thucydides Xanthopoulos, Yoshifumi Yaoi, Anantha Chandrakasan</I><P>
<DT>
<A HREF="dacabs.htm#25_4"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/25_4.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
<A HREF="../../psfiles/25_4.psz">
25.4 A Power Estimation Framework for Designing Low Power Portable Video
Applications [p 421]</A><BR>
<DD><I>Chi-Ying Tsui, Kai-Keung Chan, Qing Wu, Chih-Shun Ding, Massoud Pedram</I><P>
<DT>
<A HREF="dacabs.htm#25_5"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/25_5.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
<A HREF="../../psfiles/25_5.psz">
25.5 An Investigation of Power Delay Trade-offs On PowerPC Circuits [p 425]</A><BR>
<DD><I>Qi Wang, Sarma B.K. Vrudhula, Shantanu Ganguly</I><P>
</DL>
<HR>
<H2>Session 26:<A HREF="dacabs.htm#sess26" NAME="sess26">
HIGH LEVEL SYNTHESIS FOR LOW POWER
</A></H2>
Chair: <I>Kazutoshi Wakabayashi</I><BR>
Organizers: <I>Raul Camposano, Kazutoshi Wakabayashi</I><P>
<DL>
<DT>
<A HREF="dacabs.htm#26_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/26_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
<a href="http://www.ee.princeton.edu/~anand"><img src="../../../../../icons/url.gif"></a>
<A HREF="../../psfiles/26_1.psz">
26.1 Power Management Techniques for Control-Flow Intensive Designs [p 429]</A><BR>
<DD><I>Anand Raghunathan, Sujit Dey, Niraj K. Jha, Kazutoshi Wakabayashi</I><P>
<DT>
<A HREF="dacabs.htm#26_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/26_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
<A HREF="../../psfiles/26_2.psz">
26.2 Low Energy Memory and Register Allocation Using Network Flow [p 435]</A><BR>
<DD><I>Catherine H. Gebotys</I><P>
<DT>
<A HREF="dacabs.htm#26_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/26_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
<A HREF="../../psfiles/26_3.psz">
26.3 Power-Conscious High Level Synthesis Using Loop Folding [p 441]</A><BR>
<DD><I>Daehong Kim, Kiyoung Choi</I><P>
</DL>
<HR>
<H2>Session 27:<A HREF="dacabs.htm#sess27" NAME="sess27">
MODULE GENERATION
</A></H2>
Chair: <I>Dwight D. Hill</I><BR>
Organizers: <I>Antun Domic, Patrick Groeneveld</I><P>
<DL>
<DT>
<A HREF="dacabs.htm#27_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/27_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
<a href="http://www.cadabratech.com/dac97/"><img src="../../../../../icons/url.gif"></a>
<A HREF="../../psfiles/27_1.psz">
27.1 Embedded Tutorial: The Future of Custom Cell Generation in Physical
Synthesis [p 446]</A><BR>
<DD><I>Martin Lefebvre, David Marple, Carl Sechen</I><P>
<DT>
<A HREF="dacabs.htm#27_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/27_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
<a href="http://www.eecs.umich.edu/~avigupta/phd.html"><img src="../../../../../icons/url.gif"></a>
<A HREF="../../psfiles/27_2.psz">
27.2 CLIP: An Optimizing Layout Generator for Two-Dimensional CMOS Cells [p 452]</A><BR>
<DD><I>Avaneendra Gupta, John P. Hayes</I><P>
<DT>
<A HREF="dacabs.htm#27_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/27_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
<A HREF="../../psfiles/27_3.psz">
27.3 An Efficient Transistor Folding Algorithm for Row-Based CMOS Layout Design [p 456]</A><BR>
<DD><I>Jaewon Kim, Sung-Mo Kang</I><P>
<DT>
<A HREF="dacabs.htm#27_4"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/27_4.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
<A HREF="../../psfiles/27_4.psz">
27.4 Technology Retargeting For IC Layout [p 460]</A><BR>
<DD><I>John Lakos</I><P>
</DL>
<HR>
<H2>Session 28:<A HREF="dacabs.htm#sess28" NAME="sess28">
BIST AND DFT
</A></H2>
Chair: <I>Yervant Zorian</I><BR>
Organizers: <I>Janusz Rajski, Yervant Zorian</I><P>
<DL>
<DT>
<A HREF="dacabs.htm#28_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/28_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
<A HREF="../../psfiles/28_1.psz">
28.1 A Test Synthesis Approach to Reducing BALLAST DFT Overhead [p 466]</A><BR>
<DD><I>Douglas Chang, Mike Tien-Chien Lee, Malgorzata Marek-Sadowska,
Takashi Aikyo, Kwang-Ting Cheng</I><P>
<DT>
<A HREF="dacabs.htm#28_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/28_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
<A HREF="../../psfiles/28_2.psz">
28.2 STARBIST: Scan Autocorrelated Random Pattern Generation [p 472]</A><BR>
<DD><I>K.H. Tsai, Sybille Hellebrand, Janusz Rajski, Malgorzata Marek-Sadowska</I><P>
<DT>
<A HREF="dacabs.htm#28_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/28_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
<A HREF="../../psfiles/28_3.psz">
28.3 A Hybrid Algorithm for Test Point Selection for Scan-Based BIST [p 478]</A><BR>
<DD><I>Huan-Chih Tsai, Kwang-Ting Cheng, Chih-Jen Lin, Sudipta Bhawmik</I><P>
</DL>
<HR>
<H2>Session 29:<BR>
<A HREF="dacabs.htm#sess29" NAME="sess29"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/29_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
<A HREF="../../psfiles/29_1.psz">
PANEL: HARDWARE/SOFTWARE CO-VERIFICATION [p 484]
</A></H2>
Chair: <I>Gary Smith</I><BR>
Organizers: <I>Michel Courtoy, Marion Kenefick</I><BR>
Panelists: <I>Brian Bailey, Kurt Keutzer, Amr Mohsen, Richard Moseley,
Jim Rowson, Geoff Bunza, Willis Hendley</I><P>
<HR>
<H2>Session 30:<A HREF="dacabs.htm#sess30" NAME="sess30">
DSP & TELECOMMUNICATION SYSTEM DESIGN
</A></H2>
Chair: <I>Rajeev Jain</I><BR>
Organizers: <I>Phil Duncan, Teresa Meng</I><P>
<DL>
<DT>
<A HREF="dacabs.htm#30_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/30_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
<A HREF="../../psfiles/30_1.psz">
30.1 Design and Synthesis of Array Structured Telecommunication Processing
Applications [p 486]</A><BR>
<DD><I>Wolfgang Meyer, Andrew Seawright, Fumiya Tada</I><P>
<DT>
<A HREF="dacabs.htm#30_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/30_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
<A HREF="../../psfiles/30_2.psz">
30.2 RASSP Virtual Prototyping of DSP Systems [p 492]</A><BR>
<DD><I>Carl Hein, Junius Pridgen, Bill Kline</I><P>
<DT>
<A HREF="dacabs.htm#30_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/30_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
<A HREF="../../psfiles/30_3.psz">
30.3 A Parallel/Serial Trade-Off Methodology for Look-Up Table Based Decoders [p 498]</A><BR>
<DD><I>Claus Schneider</I><P>
</DL>
<HR>
<H2>Session 31: <BR>
<A HREF="dacabs.htm#31_1" NAME="sess31"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/31_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
<A HREF="../../psfiles/31_1.psz">
EMBEDDED TUTORIAL: HIGH LEVEL POWER MODELING, ESTIMATION AND OPTIMIZATION [p 504]
</A></H2>
Chair: <I>Massoud Pedram</I><BR>
Organizers: <I>Giovanni De Micheli, Massoud Pedram</I><BR>
Presenters: <I>Enrico Macii, Massoud Pedram, Fabio Somenzi</I><P>
<HR>
<H2>Session 32: <A HREF="dacabs.htm#sess32" NAME="sess32">
ADVANCES IN PARTITIONING
</A></H2>
Chair: <I>Martin D.F Wong</I><BR>
Organizers: <I>Antun Domic, Patrick Groeneveld</I><P>
<DL>
<DT>
<A HREF="dacabs.htm#32_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/32_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
<A HREF="../../psfiles/32_1.psz">
32.1 A Network Flow Approach for Hierarchical Tree Partitioning [p 512]</A><BR>
<DD><I>Ming-Ter Kuo, Chung-Kuan Cheng</I><P>
<DT>
<A HREF="dacabs.htm#32_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/32_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
<A HREF="../../psfiles/32_2.psz">
32.2 Multi-Way FPGA Partitioning by Fully Exploiting Design Hierarchy [p 518]</A><BR>
<DD><I>Wen-Jong Fang, Allen C.-H. Wu</I><P>
<DT>
<A HREF="dacabs.htm#32_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/32_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
<A HREF="../../psfiles/32_3.psz">
32.3 A Hierarchy-Driven FPGA Partitioning Method [p 522]</A><BR>
<DD><I>Helena Krupnova, Ali Abbara, Gabrièle Saucier</I><P>
<DT>
<A HREF="dacabs.htm#32_4"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/32_4.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
<A HREF="../../psfiles/32_4.psz">
32.4 Multilevel Hypergraph Partitioning: Application in VLSI Domain [p 526]</A><BR>
<DD><I>George Karypis, Rajat Aggarwal, Vipin Kumar, Shashi Shekhar</I><P>
<DT>
<A HREF="dacabs.htm#32_5"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/32_5.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
<A HREF="../../psfiles/32_5.psz">
32.5 Multilevel Circuit Partitioning [p 530]</A><BR>
<DD><I>Charles J. Alpert, Jen-Hsin Huang, Andrew B. Kahng</I><P>
</DL>
<HR>
<H2>Session 33:<A HREF="dacabs.htm#sess33" NAME="sess33">
PROCESSOR TEST TECHNIQUES
</A></H2>
Chair: <I>Janusz Rajski</I><BR>
Organizers: <I>Yervant Zorian, Janusz Rajski</I><P>
<DL>
<DT>
<A HREF="dacabs.htm#33_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/33_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
<A HREF="../../psfiles/33_1.psz">
33.1 Hierarchical Test Generation and Design for Testability of ASPPs and ASIPs [p 534]</A><BR>
<DD><I>Indradeep Ghosh, Anand Raghunathan, Niraj K. Jha</I><P>
<DT>
<A HREF="dacabs.htm#33_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/33_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
<A HREF="../../psfiles/33_2.psz">
33.2 Frequency-Domain Compatibility in Digital Filter BIST [p 540]</A><BR>
<DD><I>Laurence Goodby, Alex Orailoglu</I><P>
<DT>
<A HREF="dacabs.htm#33_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/33_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
<A HREF="../../psfiles/33_3.psz">
33.3 A Scheme for Integrated Controller-Datapath Fault Testing [p 546]</A><BR>
<DD><I>M. Nourani, J. Carletta, C. Papachristou</I><P>
</DL>
<HR>
<H2>Session 34:<BR>
<A HREF="dacabs.htm#sess34" NAME="sess34"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/34_0.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
<A HREF="../../psfiles/34_0.psz">
PANEL: THE NEXT GENERATION HDL [p 552]
</A></H2>
Chair: <I>Steve E. Schulz</I><BR>
Organizers: <I>Richard Goering, Nanette Collins</I><BR>
Panelists: <I>Kurt Keutzer, James A. Rowson, Larry Saunders,
Alberto Sangiovanni-Vincentelli, Maq Mannan, Gerard Berry</I><P>
<HR>
<H2>Session 35:<A HREF="dacabs.htm#sess35" NAME="sess35">
DESIGN PROCESSES AND FRAMEWORKS
</A></H2>
Chair: <I>Teresa Meng</I><BR>
Organizers: <I>Teresa Meng, Jan M. Rabaey</I><P>
<DL>
<DT>
<A HREF="dacabs.htm#35_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/35_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
<a href="http://www.cbl.ncsu.edu/publications/1997-DAC-Lavana"><img src="../../../../../icons/url.gif"></a>
<A HREF="../../psfiles/35_1.psz">
35.1 Executable Workflows: A Paradigm for Collaborative Design on the Internet [p 553]</A><BR>
<DD><I>Hemang Lavana, Amit Khetawat, Franc Brglez, Krzysztof Kozminski</I><P>
<DT>
<A HREF="dacabs.htm#35_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/35_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
<A HREF="../../psfiles/35_2.psz">
35.2 Electronic Component Information Exchange (ECIX) [p 559]</A><BR>
<DD><I>Donald Cottrell</I><P>
<DT>
<A HREF="dacabs.htm#35_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/35_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
<A HREF="../../psfiles/35_3.psz">
35.3 Modeling Design Tasks and Tools - The Link between Product and Flow Model [p 564]</A><BR>
<DD><I>Bernd Schürmann, Joachim Altmeyer</I><P>
</DL>
<HR>
<H2>Session 36:<A HREF="dacabs.htm#sess36" NAME="sess36">
PROBABILISTIC MODELS OF INPUT DATA FOR EFFICIENT POWER ESTIMATION
</A></H2>
Chair: <I>Farid N. Najm</I><BR>
Organizers: <I>Fabio Somenzi, Andrew Yang</I><P>
<DL>
<DT>
<A HREF="dacabs.htm#36_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/36_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
<A HREF="../../psfiles/36_1.psz">
36.1 Hierarchical Sequence Compaction for Power Estimation [p 570]</A><BR>
<DD><I>Radu Marculescu, Diana Marculescu, Massoud Pedram</I><P>
<DT>
<A HREF="dacabs.htm#36_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/36_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
<A HREF="../../psfiles/36_2.psz">
36.2 Profile-Driven Program Synthesis for Evaluation of System Power
Dissipation [p 576]</A><BR>
<DD><I>Cheng-Ta Hsieh, Massoud Pedram, Gaurav Mehta, Fred Rastgar</I><P>
<DT>
<A HREF="dacabs.htm#36_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/36_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
<A HREF="../../psfiles/36_3.psz">
36.3 Analytical Estimation Of Transition Activity From Word-Level Signal
Statistics [p 582]</A><BR>
<DD><I>Sumant Ramprasad, Naresh R. Shanbhag, Ibrahim N. Hajj</I><P>
</DL>
<HR>
<H2>Session 37:<A HREF="dacabs.htm#sess37" NAME="sess37">
HOT TOPICS IN ROUTING
</A></H2>
Chair: <I>Carl Sechen</I><BR>
Organizers: <I>Patrick Groeneveld, Antun Domic</I><P>
<DL>
<DT>
<A HREF="dacabs.htm#37_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/37_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
<A HREF="../../psfiles/37_1.psz">
37.1 Wire Segmenting for Improved Buffer Insertion [p 588]</A><BR>
<DD><I>Charles J. Alpert, Anirudh Devgan</I><P>
<DT>
<A HREF="dacabs.htm#37_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/37_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
<A HREF="../../psfiles/37_2.psz">
37.2 More Practical Bounded-Skew Clock Routing [p 594]</A><BR>
<DD><I>Andrew B. Kahng, C.-W. Albert Tsao</I><P>
<DT>
<A HREF="dacabs.htm#37_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/37_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
<a href="http://ballade.cs.ucla.edu/~cchang/cad/publications/DAC97-37.3.html"><img src="../../../../../icons/url.gif"></a>
<A HREF="../../psfiles/37_3.psz">
37.3 An Efficient Approach to Multi-layer Layer Assignment with Application to
Via Minimization [p 600]</A><BR>
<DD><I>Chin-Chih Chang, Jason Cong</I><P>
<DT>
<A HREF="dacabs.htm#37_4"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/37_4.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
<A HREF="../../psfiles/37_4.psz">
37.4 Optimal Wire-Sizing Function with Fringing Capacitance Consideration [p 604]</A><BR>
<DD><I>Chung-Ping Chen, D.F. Wong</I><P>
</DL>
<HR>
<H2>Session 38:<A HREF="dacabs.htm#sess38" NAME="sess38">
TEST GENERATION AND FAULT SIMULATION
</A></H2>
Chair: <I>Vishwani Agrawal</I><BR>
Organizers: <I>Yervant Zorian, Janusz Rajski</I><P>
<DL>
<DT>
<A HREF="dacabs.htm#38_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/38_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
<A HREF="../../psfiles/38_1.psz">
38.1 Fault Simulation under the Multiple Observation Time Approach using
Backward Implications [p 608]</A><BR>
<DD><I>Irith Pomeranz, Sudhakar M. Reddy</I><P>
<DT>
<A HREF="dacabs.htm#38_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/38_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
<A HREF="../../psfiles/38_2.psz">
38.2 ATPG for Heat Dissipation Minimization during Scan Testing [p 614]</A><BR>
<DD><I>Seongmoon Wang, Sandeep K. Gupta</I><P>
<DT>
<A HREF="dacabs.htm#38_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/38_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
<a href="http://www.ac.upc.es/homes/oriol/Publications/DAC97_38_3.html"><img src="../../../../../icons/url.gif"></a>
<A HREF="../../psfiles/38_3.psz">
38.3 Automatic Generation of Synchronous Test Patterns for Asynchronous Circuits [p 620]</A><BR>
<DD><I>Oriol Roig, Jordi Cortadella, Marco A. Pena, Enric Pastor</I><P>
</DL>
<HR>
<H2>Session 39:<BR>
<A HREF="dacabs.htm#sess39" NAME="sess39"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/39_0.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
<A HREF="../../psfiles/39_0.psz">
PANEL: THE ROAD AHEAD IN CPLD & FPGA DESIGN METHODOLOGY [p 626]
</A></H2>
Chair: <I>Rhondalee Rohleder</I><BR>
Organizers: <I>John Birkner</I><BR>
Panelists: <I>Don Faria, Steve Golson, Robert K. Beachler, Bruce Kleinman,
Mike Dini, Bob Donaldson, Dave Kohlmeier</I><P>
<HR>
<H2>Session 40:<A HREF="dacabs.htm#sess40" NAME="sess40">
DEEP SUBMICRON MODELING AND ANALYSIS
</A></H2>
Chair: <I>Robert C. Frye</I><BR>
Organizers: <I>Vivek Tiwari, Anantha Chandrakasan</I><P>
<DL>
<DT>
<A HREF="dacabs.htm#40_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/40_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
<A HREF="../../psfiles/40_1.psz">
40.1 Analysis and Justification of a Simple, Practical 2 1/2-D Capacitance
Extraction Methodology [p 627]</A><BR>
<DD><I>Jason Cong, Lei He, Andrew B. Kahng, David Noice, Nagesh Shirali, Steve
H.-C. Steven Yen</I><P>
<DT>
<A HREF="dacabs.htm#40_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/40_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
<A HREF="../../psfiles/40_2.psz">
40.2 Accurate And Efficient Macromodel of Submicron Digital Standard Cells [p 633]</A><BR>
<DD><I>Cristiano Forzan, Bruno Franzini, Carlo Guardiani</I><P>
<DT>
<A HREF="dacabs.htm#40_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/40_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
<A HREF="../../psfiles/40_3.psz">
40.3 Power Supply Noise Analysis Methodology for Deep-Submicron VLSI Chip Design [p 638]</A><BR>
<DD><I>Howard H. Chen, David D. Ling</I><P>
</DL>
<HR>
<H2>Session 41:<A HREF="dacabs.htm#sess41" NAME="sess41">
TECHNOLOGY-DEPENDENT OPTIMIZATION FOR PERFORMANCE AND POWER
</A></H2>
Chair: <I>Gabriele Saucier</I><BR>
Organizers: <I>Jason Cong, Gabrielle Saucier</I><P>
<DL>
<DT>
<A HREF="dacabs.htm#41_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/41_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
<A HREF="../../psfiles/41_1.psz">
41.1 FPGA Synthesis with Retiming and Pipelining for Clock Period Minimization
of Sequential Circuits [p 644]</A><BR>
<DD><I>Jason Cong, Chang Wu</I><P>
<DT>
<A HREF="dacabs.htm#41_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/41_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
<A HREF="../../psfiles/41_2.psz">
41.2 Technology-dependent Transformations for Low-Power Synthesis [p 650]</A><BR>
<DD><I>Rajendran Panda, Farid N. Najm</I><P>
<DT>
<A HREF="dacabs.htm#41_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/41_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
<A HREF="../../psfiles/41_3.psz">
41.3 Low Power FPGA Design - A Re-engineering Approach [p 656]</A><BR>
<DD><I>Chau-Shen Chen, TingTing Hwang, C.L. Liu</I><P>
<DT>
<A HREF="dacabs.htm#41_4"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/41_4.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
<A HREF="../../psfiles/41_4.psz">
41.4 Post-Layout Logic Restructuring for Performance Optimization [p 662]</A><BR>
<DD><I>Yi-Min Jiang, Angela Krstic, Kwang-Ting Cheng, Malgorzata Marek-Sadowska</I><P>
<DT>
<A HREF="dacabs.htm#41_5"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/41_5.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
<A HREF="../../psfiles/41_5.psz">
41.5 Layout Driven Re-synthesis for Low Power Consumption LSIs [p 666]</A><BR>
<DD><I>Masako Murofushi, Takashi Ishioka, Masami Murakata, Takashi Mitsuhashi</I><P>
</DL>
<HR>
<H2>Session 42:<A HREF="dacabs.htm#sess42" NAME="sess42">
CAD ISSUES FOR MICRO-ELECTRO-MECHANICAL SYSTEMS
</A></H2>
Chair: <I>Randolph E. Harr</I><BR>
Organizers: <I>Randy Harr, Jacob White</I><P>
<DL>
<DT>
<A HREF="dacabs.htm#42_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/42_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
<A HREF="../../psfiles/42_1.psz">
42.1 Embedded Tutorial: Overview of Microelectromechanical Systems and Design
Processes [p 670]</A><BR>
<DD><I>William C. Tang</I><P>
<DT>
<A HREF="dacabs.htm#42_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/42_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
<A HREF="../../psfiles/42_2.psz">
42.2 CAD and Foundries for Microsystems [p 674]</A><BR>
<DD><I>J.M. Karam, B. Courtois, H. Boutamine, P. Drake, A. Poppe,
V. Szekely, M. Rencz, K. Hofmann, M. Glesner</I><P>
<DT>
<A HREF="dacabs.htm#42_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/42_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
<A HREF="../../psfiles/42_3.psz">
42.3 Structured Design of Microelectromechanicl Systems [p 680]</A><BR>
<DD><I>Tamal Mukherjee, Gary K. Fedder</I><P>
<DT>
<A HREF="dacabs.htm#42_4"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/42_4.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
<A HREF="../../psfiles/42_4.psz">
42.4 Algorithms for Coupled Domain MEMS Simulation [p 686]</A><BR>
<DD><I>N. Aluru, J. White</I><P>
</DL>
<HR>
<H2>Session 43:<A HREF="dacabs.htm#sess43" NAME="sess43">
HARDWARE/SOFTWARE PARTITIONING
</A></H2>
Chair: <I>Rolf Ernst</I><BR>
Organizers: <I>Luciano Lavagno, Rajesh Gupta</I><P>
<DL>
<DT>
<A HREF="dacabs.htm#43_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/43_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
<A HREF="../../psfiles/43_1.psz">
43.1 A Hardware/Software Partitioner using a Dynamically Determined Granularity [p 691]</A><BR>
<DD><I>Jörg Henkel, Rolf Ernst</I><P>
<DT>
<A HREF="dacabs.htm#43_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/43_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
<a href="http://www.cs.ucla.edu/~darko/DAC97/main.html"><img src="../../../../../icons/url.gif"></a>
<A HREF="../../psfiles/43_2.psz">
43.2 System-Level Synthesis of Low-Power Hard Real-Time Systems [p 697]</A><BR>
<DD><I>Darko Kirovski, Miodrag Potkonjak</I><P>
<DT>
<A HREF="dacabs.htm#43_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/43_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
<A HREF="../../psfiles/43_3.psz">
43.3 COSYN: Hardware-Software Co-Synthesis of Embedded Systems [p 703]</A><BR>
<DD><I>Bharat P. Dave, Ganesh Lakshminarayana, Niraj K. Jha</I><P>
<DT>
<A HREF="dacabs.htm#43_4"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/43_4.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
<A HREF="../../psfiles/43_4.psz">
43.4 Data-Flow Assisted Behavioral Partitioning for Embedded Systems [p 709]</A><BR>
<DD><I>Samir Agrawal, Rajesh K. Gupta</I><P>
<DT>
<A HREF="dacabs.htm#43_5"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/43_5.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
<A HREF="../../psfiles/43_5.psz">
43.5 Hardware/Software Partitioning and Pipelining [p 713]</A><BR>
<DD><I>Smita Bakshi, Daniel D. Gajski</I><P>
</DL>
<HR>
<H2>Session 44:<BR>
<A HREF="dacabs.htm#sess44" NAME="sess44"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/44_0.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
<A HREF="../../psfiles/44_0.psz">
PANEL: NOISE AND SIGNAL INTEGRITY IN DEEP SUBMICRON DESIGN [p 717]
</A></H2>
Chair: <I>William E. Guthrie</I><BR>
Organizers: <I>Massoud Pedram</I><BR>
Panelists: <I>Rakesh Chadha, Jason Cong,
Charlie Xiaoli Huang, Anirudh Devgan, Tom Mozdzen, Andrew Yang</I><P>
<DL>
<DT>
<A HREF="dacabs.htm#44_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/44_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
<A HREF="../../psfiles/44_1.psz">
44.1 Embedded Tutorial: Chip Parasitic Extraction And Signal Integrity
Verification [p 720]</A><BR>
<DD><I>Wayne W.-M. Dai</I><P>
</DL>
<HR>
<H2>Session 45:<A NAME="sess45">
DESIGNING HIGH PERFORMANCE AND LOW POWER MICROPROCESSORS USING FULL CUSTOM
TECHNIQUES</A></H2>
Chair: <I>Anantha Chandrakasan</I><BR>
Organizer: <I>Anantha Chandrakasan</I><BR>
<DL><DT>
<A HREF="dacabs.htm#45_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/45_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
<A HREF="../../psfiles/45_1.psz">
45.1 Designing High Performance CMOS Microprocessors Using Full Custom
Techniques [p 722]</A><BR>
<DD><I>William J. Grundmann, Dan Dobberpuhl, Randy L. Allmon, Nicholas L. Rethman</I><P>
</DL>
<HR>
<H2>Session 46:<A HREF="dacabs.htm#sess46" NAME="sess46">
FORMAL VERIFICATION TECHNIQUES
</A></H2>
Chair: <I>Rich Goldman</I><BR>
Organizers: <I>Andreas Kuehlmann, Fabio Somenzi</I><P>
<DL>
<DT>
<A HREF="dacabs.htm#46_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/46_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
<A HREF="../../psfiles/46_1.psz">
46.1 Disjunctive Partitioning and Partial Iterative Squaring: An Effective
Approach for Symbolic Traversal of Large Circuits [p 728]</A><BR>
<DD><I>Gianpiero Cabodi, Paolo Camurati, Luciano Lavagno, Stefano Quer</I><P>
<DT>
<A HREF="dacabs.htm#46_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/46_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
<A HREF="../../psfiles/46_2.psz">
46.2 An Efficient Assertion Checker for Combinational Properties [p 734]</A><BR>
<DD><I>Gagan Hasteer, Anmol Mathur, Prithviraj Banerjee</I><P>
<DT>
<A HREF="dacabs.htm#46_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/46_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
<A HREF="../../psfiles/46_3.psz">
46.3 Toward Formalizing a Validation Methodology Using Simulation Coverage [p 740]</A><BR>
<DD><I>Aarti Gupta, Sharad Malik, Pranav Ashar</I><P>
</DL>
<HR>
<H2>Session 47:<A HREF="dacabs.htm#sess47" NAME="sess47">
PLACEMENT TECHNIQUES
</A></H2>
Chair: <I>Malgorzata Marek-Sadowska</I><BR>
Organizers: <I>Patrick Groeneveld, Antun Domic</I><P>
<DL>
<DT>
<A HREF="dacabs.htm#47_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/47_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
<A HREF="../../psfiles/47_1.psz">
47.1 Algorithms for Large-Scale Flat Placement [p 746]</A><BR>
<DD><I>Jens Vygen</I><P>
<DT>
<A HREF="dacabs.htm#47_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/47_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
<A HREF="../../psfiles/47_2.psz">
47.2 Quadratic Placement Revisited [p 752]</A><BR>
<DD><I>C.J. Alpert, T. Chan, D.J.-H. Huang, I. Markov, K. Yan</I><P>
<DT>
<A HREF="dacabs.htm#47_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/47_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
<A HREF="../../psfiles/47_3.psz">
47.3 Unification of Budgeting and Placement [p 758]</A><BR>
<DD><I>Majid Sarrafzadeh, David Knol, Gustavo Tellez</I><P>
<DT>
<A HREF="dacabs.htm#47_4"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/47_4.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
<A HREF="../../psfiles/47_4.psz">
47.4 Cluster Refinement for Block Placement [p 762]</A><BR>
<DD><I>Jin Xu, Pei-Ning Guo, Chung-Kuan Cheng</I><P>
</DL>
<HR>
<H2>Session 48:<BR>
<A HREF="dacabs.htm#48_0" NAME="sess48"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/48_0.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
<A HREF="../../psfiles/48_0.psz">
PANEL: THE EDA STARTUP EXPERIENCE: FINANCING THE VENTURE [p 766]
</A></H2>
Chair: <I>A.K. Kalekos</I><BR>
Organizers: <I>Mike Murray</I><BR>
Panelists: <I>Marty Walker, Penny Herscher, Lucio Lanza, Peter Odryna,
John Cooper, Gerrald Langeler</I><P>
<HR>
<H2>Session 49:<A HREF="dacabs.htm#sess49" NAME="sess49">
HETEROGENEOUS SYSTEM ANALYSIS
</A></H2>
Chair: <I>Randolph E. Harr, Richard Smith</I><BR>
Organizers: <I>David Blaauw, Jan M. Rabaey </I><P>
<DL>
<DT>
<A HREF="dacabs.htm#49_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/49_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
<A HREF="../../psfiles/49_1.psz">
49.1 Computer-Aided Design of Free-Space Opto-Electronic Systems [p 768]</A><BR>
<DD><I>S.P. Levitan, P.J. Marchand, T.P. Kurzweg, M.A. Rempel, D.M. Chiarulli,
C. Fan, F.B. McCormick</I><P>
<DT>
<A HREF="dacabs.htm#49_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/49_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
<A HREF="../../psfiles/49_2.psz">
49.2 Hardware/Software Co-Simulation in a VHDL-based Test Bench Approach [p 774]</A><BR>
<DD><I>Matthias Bauer, Wolfgang Ecker </I><P>
<DT>
<A HREF="dacabs.htm#49_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/49_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
<A HREF="../../psfiles/49_3.psz">
49.3 An Embedded System Case Study: The Firmware Development Environment for a
Multimedia Audio Processor [p 780]</A><BR>
<DD><I>Clifford Liem, Marco Cornero, Miguel Santana, Pierre Paulin, Ahmed
Jerraya, Jean-Marc Gentit, Jean Lopez, Xavier Figari, Laurent Bergher</I><P>
</DL>
<HR>
<H2><A NAME="tutorials">
FULL-DAY TUTORIALS
</A></H2>
<DT>
Tutorial 1: Low-Power Design<BR>
<DD><I>Kaushik Roy, Brock Barton, Sayfe Kiaei</I><P>
<DT>
Tutorial 2: System-Design Using IC Cores: Design, Test And Sign-Off<BR>
<DD><I>Rajesh K. Gupta, Ramsey Haddad, Rob Roy</I><P>
<DT>
Tutorial 3: Reconfigurable Systems: Logic Emulation, Custom Computing, And Beyond<BR>
<DD><I>Scott Hauck, Michael Butts, James Gateley, Brad Hutchings, Mark Shand</I><P>
<DT>
Tutorial 4: Interconnect-Driven Performance Optimization For Deep Submicron
Layout Systems<BR>
<DD><I>Jason Cong, David Blaauw, Ren-Song Tsay</I><P>
<DT>
Tutorial 5: ASIC Delay And Power Calculation<BR>
<DD><I>Jay Abraham, Steve Mecham, Karla Reynolds</I><P>
<DT>
Tutorial 6: Introduction To JAVA Programming<BR>
<DD><I>Jean Brouwers, Patricia Meyer, David Plotkin, Morgan Herrington</I><P>
<DT>
Tutorial 7: Advanced JAVA Topics<BR>
<DD><I>Jean Brouwers, Patricia Meyer</I><P>
</DL>
</B>
]]>