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<H3><A HREF="../../../../../MAIN_DH.HTM;1">Main Page</A></BR>
DATE'98 :
[ <A HREF="DATEABS.HTM;1">Abstracts</A> ]
[ <A HREF="DATESESS.HTM;1">Session Index</A> ]
[ <A HREF="DATEAI.HTM;1">Author Index</A> ]</H3>
<HR>
<H2>DATE'98 TABLE OF CONTENTS</H2>
<B>
Sessions:
[<A HREF="#sess1a">1A</A>]
[<A HREF="#sess1b">1B</A>]
[<A HREF="#sess1c">1C</A>]
[<A HREF="#sess1d">1D</A>]
[<A HREF="#sess2a">2A</A>]
[<A HREF="#sess2b">2B</A>]
[<A HREF="#sess2c">2C</A>]
[<A HREF="#sess2d">2D</A>]
[<A HREF="#sess3a">3A</A>]
[<A HREF="#sess3b">3B</A>]
[<A HREF="#sess3c">3C</A>]
[<A HREF="#sess3d">3D</A>]
[<A HREF="#sess3e">3E</A>]
[<A HREF="#sess4a">4A</A>]
[<A HREF="#sess4b">4B</A>]
[<A HREF="#sess4c">4C</A>]
[<A HREF="#sess4d">4D</A>]
[<A HREF="#sess5a">5A</A>]
[<A HREF="#sess5b">5B</A>]
[<A HREF="#sess5c">5C</A>]
[<A HREF="#sess5d">5D</A>]
[<A HREF="#sess6a">6A</A>]
[<A HREF="#sess6b">6B</A>]
[<A HREF="#sess6c">6C</A>]
[<A HREF="#sess6d">6D</A>]
[<A HREF="#sess7a">7A</A>]
[<A HREF="#sess7b">7B</A>]
[<A HREF="#sess7c">7C</A>]
[<A HREF="#sess7d">7D</A>]
[<A HREF="#sess8a">8A</A>]
[<A HREF="#sess8b">8B</A>]
[<A HREF="#sess8c">8C</A>]
[<A HREF="#sess8d">8D</A>]
[<A HREF="#sess9a">9A</A>]
[<A HREF="#sess9b">9B</A>]
[<A HREF="#sess9c">9C</A>]
[<A HREF="#sess9d">9D</A>]
[<A HREF="#sess10a">10A</A>]
[<A HREF="#sess10b">10B</A>]
[<A HREF="#sess10c">10C</A>]
[<A HREF="#sess10d">10D</A>]
[<A HREF="#sess11a">11A</A>]
[<A HREF="#sess11b">11B</A>]
[<A HREF="#sess11c">11C</A>]
[<A HREF="#sess11d">11D</A>]
[<A HREF="#poster">Poster</A>]
<P>
<A HREF="../../PDFFILES/EVENT.PDF;1">Event Steering Board</A><BR>
<A HREF="../../PDFFILES/COMMITTE.PDF;1">Conference Organizing Committe</A><BR>
<A HREF="../../PDFFILES/PROGRAM.PDF;1">Programme Topic Chairs</A><BR>
<A HREF="../../PDFFILES/VENDORS.PDF;1">Vendors Committee</A><BR>
<A HREF="../../PDFFILES/TECHCOM.PDF;1">Technical Programme Committee</A><BR>
<A HREF="../../PDFFILES/WELCOME.PDF;1">Welcome to DATE'98</A><BR>
<A HREF="../../PDFFILES/KEYNOTE.PDF;1">Keynote Addresses Summaries</A><BR>
<A HREF="../../PDFFILES/TUTORIAL.PDF;1">Tutorials</A><BR>
<A HREF="../../PDFFILES/REVIEWER.PDF;1">List of Reviewers</A><P>
</B>
<HR>
<H2>Session 1A:<A HREF="DATEABS.HTM;1#sess1a" NAME="sess1a">
Design Optimization of Building Blocks
</A></H2>
Moderators: <I>Y. Zorian, LogicVision, USA,<BR>
P. Plaza, Telefonca I+D, Spain</I><P>
<DL>
<DT>
<A HREF="DATEABS.HTM;1#01a_1"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/01A_1.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Collapsing the Transistor Chain to an Effective Single Equivalent Transistor [p 2]
<DD><I>A. Chatzigeorgiou and S. Nikolaidis</I><P>
<DT>
<A HREF="DATEABS.HTM;1#01a_2"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/01A_2.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Design of Fault-Secure Parity-Prediction Booth Multipliers [p 7]
<DD><I>M. Nicolaidis and R.O. Duarte</I><P>
<DT>
<A HREF="DATEABS.HTM;1#01a_3"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/01A_3.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
PASTEL: A Parameterized Memory Characterization System [p 15]
<DD><I>K. Ogawa, M. Kohno, and F. Kitamura</I><P>
</DL>
<HR>
<H2>Session 1B:<A HREF="DATEABS.HTM;1#sess1b" NAME="sess1b">
HW/SW Partitioning and Communication Synthesis
</A></H2>
Moderators: <I>K. Buchenrieder, Siemens AG, Germany,<BR>
A. Jerraya, TIMA, Grenoble, France</I><P>
<DL>
<DT>
<A HREF="DATEABS.HTM;1#01b_1"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/01B_1.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Hardware Resource Allocation for Hardware/Software Partitioning in the LYCOS
System [p 22]
<DD><I>J. Grode, P.V. Knudsen, and J. Madsen</I><P>
<DT>
<A HREF="DATEABS.HTM;1#01b_2"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/01B_2.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Hardware Software Partitioning with Integrated Hardware Design
Space Exploration [p 28]
<DD><I>V. Srinivasan, S. Radhakrishnan, and R. Vemuri</I><P>
<DT>
<A HREF="DATEABS.HTM;1#01b_3"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/01B_3.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Generation of Interconnect Topologies for Communication Synthesis [p 36]
<DD><I>M. Gasteier, M. Münch, and M. Glesner</I><P>
</DL>
<HR>
<H2>Session 1C:<A HREF="DATEABS.HTM;1#sess1c" NAME="sess1c">
Asynchronous and Hybrid VHDL-Based Design
</A></H2>
Moderators: <I>A. Vachoux, Ecole Polytechnique Federale de Lausanne, Switzerland,<BR>
T. Kazmierski, University of Southampton, UK </I><P>
<DL>
<DT>
<A HREF="DATEABS.HTM;1#01c_1"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/01C_1.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
The Design of an Asynchronous VHDL Synthesizer [p 44]
<DD><I>S.-Y. Tan, S.B. Furber, and W.-F. Yen</I><P>
<DT>
<A HREF="DATEABS.HTM;1#01c_2"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/01C_2.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Repartitioning and Technology Mapping of Electronic Hybrid Systems [p 52]
<DD><I>C. Grimm and K. Waldschmidt</I><P>
<DT>
<A HREF="DATEABS.HTM;1#01c_3"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/01C_3.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
VHDL-AMS: The Missing Link in System Design - Experiments with Unified
Modelling in Automotive Engineering [p 59]
<DD><I>E. Moser and N. Mittwollen</I><P>
</DL>
<HR>
<H2>Session 1D:<A HREF="DATEABS.HTM;1#sess1d" NAME="sess1d">
Data Path and FPGA Testing
</A></H2>
Moderators: <I> H.-J. Wunderlich, University of Stuttgart, Germany,<BR>
M. Nicolaidis, TIMA, Grenoble, France</I><P>
<DL>
<DT>
<A HREF="DATEABS.HTM;1#01d_1"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/01D_1.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Scheduling and Module Assignment for Reducing BIST Resources [p 66]
<DD><I>I. Parulkar, S.K. Gupta, and M.A. Breuer</I><P>
<DT>
<A HREF="DATEABS.HTM;1#01d_2"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/01D_2.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
An Efficient Algorithm to Integrate Scheduling and Allocation in High-Level
Test Synthesis [p 74]
<DD><I>T. Yang and Z. Peng</I><P>
<DT>
<A HREF="DATEABS.HTM;1#01d_3"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/01D_3.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
RAM-Based FPGA's: A Test Approach for the Configurable Logic [p 82]
<DD><I>M. Renovell, J.M. Portal, J. Figueras, and Y. Zorian</I><P>
<DT>
<A HREF="DATEABS.HTM;1#01d_4"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/01D_4.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Novel Technique for Testing FPGAs [p 89]
<DD><I>C. Metra, G. Mojoli, S. Pastore, D. Salvi, and G. Sechi</I><P>
</DL>
<HR>
<H2>Session 2A:<A HREF="DATEABS.HTM;1#sess2a" NAME="sess2a">
Design Methods for High Performance Applications
</A></H2>
Moderators: <I>Y. Torroja, Polytechnical University of Madrid, Spain,<BR>
R. Sarmiento, University of Las Palmas de Gran Canaria, Spain </I><P>
<DL>
<DT>
<A HREF="DATEABS.HTM;1#02a_1"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/02A_1.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
ATM Traffic Shaper: ATS [p 96]
<DD><I>J.C. Diaz, P. Plaza, and J. Crespo</I><P>
<DT>
<A HREF="DATEABS.HTM;1#02a_2"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/02A_2.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
XFVHDL: A Tool for the Synthesis of Fuzzy Logic Controllers [p 102]
<DD><I>E. Lago, C.J. Jiménez, D.R. López,
S. Sánchez-Solano, and A. Barriga</I><P>
<DT>
<A HREF="DATEABS.HTM;1#02a_3"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/02A_3.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
High Speed Neural Network Chip for Trigger Purposes in High Energy Physics
[p 108]
<DD><I>W. Eppler, T. Fischer, H. Gemmeke, and A. Menchikov</I><P>
</DL>
<HR>
<H2>Session 2B:<A HREF="DATEABS.HTM;1#sess2b" NAME="sess2b">
Scheduling in Embedded Systems
</A></H2>
Moderators: <I> S.A. Huss, Darmstadt University of Technology, Germany,<BR>
H.-P. Amann, University of Neuchatel, Switzerland</I><P>
<DL>
<DT>
<A HREF="DATEABS.HTM;1#02b_1"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/02B_1.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
CASPER: Concurrent Hardware-Software Co-Synthesis of Hard Real-Time
Aperiodic and Periodic Specifications of Embedded System Architectures [p 118]
<DD><I>B.P. Dave and N.K. Jha</I><P>
<DT>
<A HREF="DATEABS.HTM;1#02b_2"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/02B_2.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Stream Communication Between Real-Time Tasks in a High-Performance
Multiprocessor [p 125]
<DD><I>J.A.J. Leijten, J.L. van Meerbergen, A.H. Timmer, and J.A.G. Jess</I><P>
<DT>
<A HREF="DATEABS.HTM;1#02b_3"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/02B_3.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Scheduling of Conditional Process Graphs for the Synthesis of
Embedded Systems [p 132]
<DD><I>P. Eles, K. Kuchcinski, Z. Peng, A. Doboli, and P. Pop</I><P>
</DL>
<HR>
<H2>Session 2C:<A HREF="DATEABS.HTM;1#sess2c" NAME="sess2c">
Advanced Techniques for VHDL Design
</A></H2>
Moderators: <I>E. Villar, University of Cantabria, Spain,<BR>
D. Sciuto, Politecnico di Milano, Italy</I><P>
<DL>
<DT>
<A HREF="DATEABS.HTM;1#02c_1"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/02C_1.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Model Abstraction for Formal Verification [p 140]
<DD><I>Y.-W. Hsieh and S.P. Levitan</I><P>
<DT>
<A HREF="DATEABS.HTM;1#02c_2"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/02C_2.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
VHDL Modelling and Analysis of Fault Secure Systems [p 148]
<DD><I>J. Coppens, D. Al-Khalili, and C. Rozon</I><P>
<DT>
<A HREF="DATEABS.HTM;1#02c_3"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/02C_3.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Register Transfer Level VHDL Models without Clocks [p 153]
<DD><I>M. Mutz</I><P>
<DT>
<A HREF="DATEABS.HTM;1#02c_4"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/02C_4.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Parallel VHDL Simulation [p 159]
<DD><I>E. Naroska</I><P>
</DL>
<HR>
<H2>Session 2D:<A HREF="DATEABS.HTM;1#sess2d" NAME="sess2d">
Novel BIST Approaches
</A></H2>
Moderators: <I>E. Aas, Norwegian University of Science and Technology, Norway,<BR>
Z. Peng, Linköping University, Sweden</I><P>
<DL>
<DT>
<A HREF="DATEABS.HTM;1#02d_1"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/02D_1.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Testing DSP Cores Based on Self-Test Programs [p 166]
<DD><I>W. Zhao and C. Papachristou</I><P>
<DT>
<A HREF="DATEABS.HTM;1#02d_2"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/02D_2.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Self-Adjusting Output Data Compression: An Efficient BIST Technique for RAMs
[p 173]
<DD><I>V.N. Yarmolik, S. Hellebrand, and H.-J. Wunderlich</I><P>
<DT>
<A HREF="DATEABS.HTM;1#02d_3"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/02D_3.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Built-In Self-Test with an Alternating Output [p 180]
<DD><I>T. Bogue, M. Gössel, H. Jürgensen, and Y. Zorian</I><P>
</DL>
<HR>
<H2>Session 3A:<A HREF="DATEABS.HTM;1#sess3a" NAME="sess3a">
Architectures for Image Processing
</A></H2>
Moderators: <I>I. Bolsens, IMEC, Belgium,<BR>
A. Nunez, University of Las Palmas de Gran Canaria, Spain</I><P>
<DL>
<DT>
<A HREF="DATEABS.HTM;1#03a_1"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/03A_1.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
From Algorithms to Hardware Architectures: A Comparison of Regular
and Irregular Structured IDCT Algorithms [p 186]
<DD><I>C. Schneider, M. Kayss, T. Hollstein, and J. Deicke</I><P>
<DT>
<A HREF="DATEABS.HTM;1#03a_2"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/03A_2.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Smart Pixel Implementation of a 2-D Parallel Nucleic Wavelet
Transform for Mobile Multimedia Communications [p 191]
<DD><I>A.M. Rassau, K. Eshraghian, H. Cheung, S.W. Lachowicz, T.C.B. Yu,
W.A. Crossland, and T.D. Wilkinson</I><P>
<DT>
<A HREF="DATEABS.HTM;1#03a_3"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/03A_3.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
VLSI Architecture for Lossless Compression of Medical Images Using
the Discrete Wavelet Transform [p 196]
<DD><I>I. Urriza, J.I. Artigas, J.I. García, L.A. Barragán,
and D. Navarro</I><P>
</DL>
<HR>
<H2>Session 3B:<A HREF="DATEABS.HTM;1#sess3b" NAME="sess3b">
Scheduling and Analysis of HW/SW Systems
</A></H2>
Moderators: <I>R. Ernst, Technical University of Braunschweig, Germany, <BR>
P. van der Wolf, Philips Research Laboratories, The Netherlands</I><P>
<DL>
<DT>
<A HREF="DATEABS.HTM;1#03b_1"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/03B_1.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
A Model for System-Level Timed Analysis and Profiling [p 204]
<DD><I>A. Allara, W. Fornaciari, F. Salice, and D. Sciuto</I><P>
<DT>
<A HREF="DATEABS.HTM;1#03b_2"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/03B_2.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Efficient Compilation of Process-Based Concurrent Programs without
Run-Time Scheduling [p 211]
<DD><I>B. Lin</I><P>
<DT>
<A HREF="DATEABS.HTM;1#03b_3"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/03B_3.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
A Macroscopic Time and Cost Estimation Model Allowing Task Parallelism
and Hardware Sharing for the Codesign Partitioning Process [p 218]
<DD><I>J.A. Maestro, D. Mozos, and H. Mecha</I><P>
<DT>
<A HREF="DATEABS.HTM;1#03b_4"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/03B_4.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
A Scalable Methodology for Cost Estimation in a Transformational
High-Level Design Space Exploration Environment [p 226]
<DD><I>J. Gerlach and W. Rosenstiel</I><P>
</DL>
<HR>
<H2>Session 3C:<A HREF="DATEABS.HTM;1#sess3c" NAME="sess3c">
Extensions to VHDL
</A></H2>
Moderators: <I>S. Maginot, LEDA, France, W. Ecker, Siemens AG, Germany</I><P>
<DL>
<DT>
<A HREF="DATEABS.HTM;1#03c_1"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/03C_1.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Object-Oriented Modelling of Parallel Hardware Systems [p 234]
<DD><I>G. Schumacher and W. Nebel</I><P>
<DT>
<A HREF="DATEABS.HTM;1#03c_2"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/03C_2.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
A Flexible Message Passing Mechanism for Objective VHDL [p 242]
<DD><I>W. Putzke-Röming, M. Radetzki, and W. Nebel</I><P>
<DT>
<A HREF="DATEABS.HTM;1#03c_3"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/03C_3.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Enhanced Reuse and Teamwork Capabilities for an Object-Oriented Extension of
VHDL [p 250]
<DD><I>M. Mrva</I><P>
<DT>
<A HREF="DATEABS.HTM;1#03c_4"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/03C_4.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Formal Specification in VHDL for Hardware Verification [p 257]
<DD><I>R. Reetz, K. Schneider, and T. Kropf</I><P>
</DL>
<HR>
<H2>Session 3D:<A HREF="DATEABS.HTM;1#sess3d" NAME="sess3d">
Error Detection and Design Validation
</A></H2>
Moderators: <I>T. Vierhaus, Technical University of Cottbus, Germany,<BR>
R. Segers, Philips Semiconductors, The Netherlands</I><P>
<DL>
<DT>
<A HREF="DATEABS.HTM;1#03d_1"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/03D_1.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
A Low-Redundancy Approach to Semi-Concurrent Error Detection in Data Paths [p 266]
<DD><I>A. Antola, V. Piuri, and M. Sami</I><P>
<DT>
<A HREF="DATEABS.HTM;1#03d_2"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/03D_2.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Measuring the Effectiveness of Various Design Validation Approaches
for PowerPC<SUP>TM</SUP> Microprocessor Arrays [p 273]
<DD><I>L.-C. Wang, M.S. Abadir, and J. Zeng</I><P>
<DT>
<A HREF="DATEABS.HTM;1#03d_3"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/03D_3.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Functional Scan Chain Testing [p 278]
<DD><I>D. Chang, M.T.-C. Lee, K.-T. Cheng, and M. Marek-Sadowska</I><P>
</DL>
<HR>
<H2>Session 3E:<A HREF="DATEABS.HTM;1#sess3e" NAME="sess3e">
Hot Topic: IP Based System-on-a-Chip Design
</A></H2>
Co-ordinators: <I>Carlo Guardiani, SGS-Thomson, Italy<BR>
Wolfgang Nebel, Oldenburg University and OFFIS, Germany<P></I>
Moderator: <I>Alberto Sangiovanni-Vincentelli, University of California at Berkeley, USA<P></I>
Speakers: <I>Grant Martin, Cadence, USA<BR>
Mike Muller, ARM, UK<BR>
Bart De Loore, Philips Semiconductors, The Netherlands<P></I>
Panelists: <I>Doug Fairbairn, VSI Alliance, USA<BR>
Pietro Erratico, SGS-Thomson, Italy<BR>
Faysal Soheil, Synopsys, USA
</I><P>
<DL>
<DT>
<A HREF="DATEABS.HTM;1#03e_1"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/03E_1.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Design Methodologies for System Level IP [p 286]
<DD><I>G. Martin</I><P>
<DT>
<A HREF="DATEABS.HTM;1#03e_2"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/03E_2.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
IP-Based System-on-a-Chip Design [p 290]
<DD><I>B. De Loore</I><P>
</DL>
<HR>
<H2>Session 4A:<A HREF="DATEABS.HTM;1#sess4a" NAME="sess4a">
Design Reuse Methodologies
</A></H2>
Moderators: <I>J. Heaton, ICL, UK, R. Seepold, FZI Karlsruhe, Germany</I><P>
<DL>
<DT>
<A HREF="DATEABS.HTM;1#04a_1"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/04A_1.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
A Systematic Analysis of Reuse Strategies for Design of
Electronic Circuits [p 292]
<DD><I>M. Koegst, P. Conradi, D. Garte, and M. Wahl</I><P>
<DT>
<A HREF="DATEABS.HTM;1#04a_2"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/04A_2.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
VHDL Teamwork, Organization Units and Workspace Management [p 297]
<DD><I>S. Olcoz, L. Ayuda, I. Izaguirre, and O. Penalba</I><P>
<DT>
<A HREF="DATEABS.HTM;1#04a_3"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/04A_3.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
An Object-Oriented Model for Specification, Prototyping, Implementation
and Reuse [p 303]
<DD><I>J. Böttger, K. Agsteiner, D. Monjau, and S. Schulze</I><P>
</DL>
<HR>
<H2>Session 4B:<A HREF="DATEABS.HTM;1#sess4b" NAME="sess4b">
Flat and Timing-Driven Processor Design
</A></H2>
Moderators: <I>E. Barke, University of Hannover, Germany,<BR>
I. Rugen-Herzig, Temic Telefunken Microelectronic GmbH, Germany</I><P>
<DL>
<DT>
<A HREF="DATEABS.HTM;1#04b_1"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/04B_1.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
A Flat, Timing-Driven Design System for a High-Performance CMOS
Processor Chipset [p 312]
<DD><I>J. Koehl, U. Baur, T. Ludwig, B. Kick, and T. Pflueger</I><P>
<DT>
<A HREF="DATEABS.HTM;1#04b_2"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/04B_2.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Algorithms for Detailed Placement of Standard Cells [p 321]
<DD><I>J. Vygen</I><P>
<DT>
<A HREF="DATEABS.HTM;1#04b_3"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/04B_3.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Timing Analysis and Optimization of a High-Performance CMOS
Processor Chipset [p 325]
<DD><I>U. Fassnacht and J. Schietke</I><P>
<DT>
<A HREF="DATEABS.HTM;1#04b_4"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/04B_4.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
A Sequential Detailed Router for Huge Grid Graphs [p 332]
<DD><I>A. Hetzel</I><P>
</DL>
<HR>
<H2>Session 4C:<A HREF="DATEABS.HTM;1#sess4c" NAME="sess4c">
Hot Topic: Reconfigurable Systems
</A></H2>
Co-ordinator: <I>Ivo Bolsens, IMEC, Belgium</I><P>
Moderator: <I>Nadir Bagherzadeh, University of California at Irvine, USA</I><P>
Speakers: <I>W. Shields Neely, National Semiconductor, USA<BR>
Jan Rabaey, University of California at Berkeley, USA<BR>
Ian Page, University of Oxford, UK
</I><P>
<DL>
<DT>
<A HREF="DATEABS.HTM;1#04c_1"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/04C_1.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Reconfigurable Logic for Systems on a Chip [p 340]
<DD><I>W. Shields Neely</I><P>
<DT>
<A HREF="DATEABS.HTM;1#04c_2"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/04C_2.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
An Energy-Conscious Exploration Methodology for Reconfigurable DSPs [p 341]
<DD><I>J. Rabaey and M. Wan</I><P>
<DT>
<A HREF="DATEABS.HTM;1#04c_3"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/04C_3.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Design of Future Systems [p 343]
<DD><I>I. Page</I><P>
</DL>
<HR>
<H2>Session 4D:<A HREF="DATEABS.HTM;1#sess4d" NAME="sess4d">
Digital Simulation and Estimation
</A></H2>
Moderators: <I>Peter Schwarz, Fraunhofer EAS Dresden, Germany,<BR>
H. Fleurkens, Philips Research Laboratories, The Netherlands</I><P>
<DL>
<DT>
<A HREF="DATEABS.HTM;1#04d_1"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/04D_1.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
AFTA: A Formal Delay Model for Functional Timing Analysis [p 350]
<DD><I>V. Chandramouli, J.P. Whittemore, and K.A. Sakallah</I><P>
<DT>
<A HREF="DATEABS.HTM;1#04d_2"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/04D_2.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Power-Simulation of Cell Based ASICs: Accuracy- and Performance Trade-Offs
[p 356]
<DD><I>D. Rabe, G. Jochens, L. Kruse, and W. Nebel</I><P>
<DT>
<A HREF="DATEABS.HTM;1#04d_3"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/04D_3.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Advanced Optimistic Approaches in Logic Simulation [p 362]
<DD><I>S. Schmerler, Y. Tanurhan, and K.D. Müller-Glaser</I><P>
</DL>
<HR>
<H2>Session 5A:<A HREF="DATEABS.HTM;1#sess5a" NAME="sess5a">
Synthesis of Reprogrammable and Reconfigurable Architectures
</A></H2>
Moderators: <I>F. Kurdahi, University of California, Irvine, USA,<BR>
A. Jerraya, TIMA, Grenoble, France</I><P>
<DL>
<DT>
<A HREF="DATEABS.HTM;1#05a_1"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/05A_1.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
PSCP: A Scalable Parallel ASIP Architecture for Reactive Systems [p 370]
<DD><I>A. Pyttel, A. Sedlmeier, and C. Veith</I><P>
<DT>
<A HREF="DATEABS.HTM;1#05a_2"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/05A_2.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
A Constraint Driven Approach to Loop Pipelining and Register Binding [p 377]
<DD><I>B. Mesman, M. Strik, A.H. Timmer, J.L. van Meerbergen, and
J.A.G.Jess</I><P>
<DT>
<A HREF="DATEABS.HTM;1#05a_3"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/05A_3.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Multiple Behavior Module Synthesis Based on Selective Groupings [p 384]
<DD><I>J.-H. Yi, H. Choi, I.-C. Park, S.H. Hwang, and C.-M. Kyung</I><P>
<DT>
<A HREF="DATEABS.HTM;1#05a_4"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/05A_4.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Optimal Temporal Partitioning and Synthesis for Reconfigurable Architectures
[p 389]
<DD><I>M. Kaul and R. Vemuri</I><P>
</DL>
<HR>
<H2>Session 5B:<A HREF="DATEABS.HTM;1#sess5b" NAME="sess5b">
Partitioning and Routing
</A></H2>
Moderators: <I>M.D.F. Wong, University of Texas at Austin, USA, <BR>
F.M. Johannes, Technical University of Munich, Germany</I><P>
<DL>
<DT>
<A HREF="DATEABS.HTM;1#05b_1"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/05B_1.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
An Effective General Connectivity Concept for Clustering [p 398]
<DD><I>J. Song, Z. Shen, and W. Zhuang</I><P>
<DT>
<A HREF="DATEABS.HTM;1#05b_2"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/05B_2.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Improved Approximation Bounds for the Group Steiner Problem [p 406]
<DD><I>C.S. Helvig, G. Robins, and A. Zelikovsky</I><P>
<DT>
<A HREF="DATEABS.HTM;1#05b_3"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/05B_3.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
An Interactive Router for Analog IC Design [p 414]
<DD><I>T. Adler and J. Scheible</I><P>
</DL>
<HR>
<H2>Session 5C:<A HREF="DATEABS.HTM;1#sess5c" NAME="sess5c">
Panel - Formal Verification: A New Standard CAD Tool for the Industrial
Design Flow
</A></H2>
Organizers: <I>Wolfgang Rosenstiel, University of Tübingen, Germany
Gerry Musgrave, Brunel University, UK</I><P>
Moderator: <I>Gerry Musgrave, Brunel University, UK<P></I>
Panelists: <I>Dominique Borrione, TIMA-UJF, France<BR>
Antun Domic, Synopsys, USA<BR>
Ramayya Kumar, Verysys, Germany<BR>
Alan Page, Abstract Design Automation, UK<BR>
Michael Payer, Siemens, Germany
</I><P>
<DL>
<DT>
<A HREF="DATEABS.HTM;1#05c_1"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/05C_1.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Formal Verification: A New Standard CAD Tool for the Industrial Design Flow
[p 422]
<DD><I>W. Rosenstiel</I><P>
</DL>
<HR>
<H2>Session 5D:<A HREF="DATEABS.HTM;1#sess5d" NAME="sess5d">
Simulation for High-Level Design
</A></H2>
Moderators: <I>J. Forrest, UMIST, Manchester, UK<BR>
M. Pfaff, Johannes Kepler University Linz, Austria</I><P>
<DL>
<DT>
<A HREF="DATEABS.HTM;1#05d_1"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/05D_1.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
A System-Level Co-Verification Environment for ATM Hardware Design [p 424]
<DD><I>G. Post, A. Müller, and T. Grötker</I><P>
<DT>
<A HREF="DATEABS.HTM;1#05d_2"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/05D_2.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
FRIDGE: A Fixed-Point Design and Simulation Environment [p 429]
<DD><I>H. Keding, M. Willems, M. Coors, and H. Meyr</I><P>
<DT>
<A HREF="DATEABS.HTM;1#05d_3"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/05D_3.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Verification by Simulation Comparison Using Interface Synthesis [p 436]
<DD><I>C. Hansen, A. Kunzmann, and W. Rosenstiel</I><P>
</DL>
<HR>
<H2>Session 6A:<A HREF="DATEABS.HTM;1#sess6a" NAME="sess6a">
Architectural Synthesis
</A></H2>
Moderators: <I>P. Marwedel, University of Dortmund, Germany, <BR>
A. Timmer, Philips Research Laboratories, The Netherlands</I><P>
<DL>
<DT>
<A HREF="DATEABS.HTM;1#06a_1"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/06A_1.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Layout-Driven High Level Synthesis for FPGA Based Architectures [p 446]
<DD><I>M. Xu and F.J. Kurdahi</I><P>
<DT>
<A HREF="DATEABS.HTM;1#06a_2"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/06A_2.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Cross-Level Hierarchical High-Level Synthesis [p 451]
<DD><I>O. Bringmann and W. Rosenstiel</I><P>
<DT>
<A HREF="DATEABS.HTM;1#06a_3"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/06A_3.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
An Algorithm to Determine Mutually Exclusive Operations in Behavioral
Descriptions [p 457]
<DD><I>J. Li and R.K. Gupta</I><P>
</DL>
<HR>
<H2>Session 6B:<A HREF="DATEABS.HTM;1#sess6b" NAME="sess6b">
Timing and Crosstalk in Interconnect
</A></H2>
Moderators: <I>R. Peset Llopis, Philips Research Laboratories, The Netherlands,<BR>
B. Schürmann, University of Kaiserslautern, Germany</I><P>
<DL>
<DT>
<A HREF="DATEABS.HTM;1#06b_1"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/06B_1.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
A Performance-Driven MCM Router with Special Consideration of
Crosstalk Reduction [p 466]
<DD><I>D. Wang and E.S. Kuh</I><P>
<DT>
<A HREF="DATEABS.HTM;1#06b_2"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/06B_2.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Interconnect Tuning Strategies for High-Performance ICs [p 471]
<DD><I>A.B. Kahng, S. Muddu, E. Sarto, and R. Sharma</I><P>
<DT>
<A HREF="DATEABS.HTM;1#06b_3"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/06B_3.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
A Polynomial Time Optimal Algorithm for Simultaneous Buffer
and Wire Sizing [p 479]
<DD><I>C.C.N. Chu and D.F. Wong</I><P>
</DL>
<HR>
<H2>Session 6C:<A HREF="DATEABS.HTM;1#sess6c" NAME="sess6c">
Panel: Next Generation System Design Tools
</A></H2>
Co-ordinators: <I>Wolfgang Rosenstiel, University of Tübingen, Germany
Joachim Kunkel, Synopsys, USA</I><P>
Moderator: <I>Joachim Kunkel, Synopsys, USA</I><P>
Panelists: <I>Misha Burich, Cadance/Alta, USA<BR>
Raul Camposano, Synopsys, USA<BR>
Mark Genoe, Alcatel, Belgium<BR>
Lev Markov, Mentor Graphics, USA<BR>
Steve Schulz, Texas Instruments, USA
</I><P>
<DL>
<DT>
<A HREF="DATEABS.HTM;1#06c_1"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/06C_1.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Next Generation System Level Design Tools [p 488]
<DD><I>W. Rosenstiel</I><P>
</DL>
<HR>
<H2>Session 6D:<A HREF="DATEABS.HTM;1#sess6d" NAME="sess6d">
IDDQ and Memory Testing
</A></H2>
Moderators: <I>M. Sachdev, Philips Research Laboratories, The Netherlands,<BR>
B. Straube, FhG IIS/EAS Dresden, Germany</I><P>
<DL>
<DT>
<A HREF="DATEABS.HTM;1#06d_1"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/06D_1.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Estimation of the Defective I<SUB>DDQ</SUB> Caused by Shorts in
Deep-Submicron CMOS ICs [p 490]
<DD><I>R. Rodríguez-Montanés and J. Figueras</I><P>
<DT>
<A HREF="DATEABS.HTM;1#06d_2"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/06D_2.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
A Fully Digital Controlled Off-Chip I<SUB>DDQ</SUB> Measurement Unit [p 495]
<DD><I>B. Straka, H. Manhaeve, J. Vanneuville, and M. Svajda</I><P>
<DT>
<A HREF="DATEABS.HTM;1#06d_3"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/06D_3.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
March Tests for Word-Oriented Memories [p 501]
<DD><I>A.J. van de Goor and I.B.S. Tlili</I><P>
</DL>
<HR>
<H2>Session 7A:<A HREF="DATEABS.HTM;1#sess7a" NAME="sess7a">
Microsystems
</A></H2>
Moderators: <I>J. Bausells, CNM, Barcelona, Spain, <BR>
M. Glesner, Technical University of Darmstadt, Germany</I><P>
<DL>
<DT>
<A HREF="DATEABS.HTM;1#07a_1"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/07A_1.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
A Modeling Approach to Include Mechanical Microsystem Components
into the System Simulation [p 510]
<DD><I>R. Neul, U. Becker, G. Lorenz, P. Schwarz, J. Haase, and
S. Wünsche</I><P>
<DT>
<A HREF="DATEABS.HTM;1#07a_2"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/07A_2.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Fast Field Solvers for Thermal and Electrostatic Analysis [p 518]
<DD><I>V. Székely and M. Rencz</I><P>
<DT>
<A HREF="DATEABS.HTM;1#07a_3"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/07A_3.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Microsystems Testing: An Approach and Open Problems [p 524]
<DD><I>M. Lubaszewski, E.F. Cota, and B. Courtois</I><P>
</DL>
<HR>
<H2>Session 7B:<A HREF="DATEABS.HTM;1#sess7b" NAME="sess7b">
Interconnect Modeling
</A></H2>
Moderators: <I>F.M. Johannes, Technical University of Munich, Germany,<BR>
J. Koehl, IBM Deutschland Entwicklung GmbH, Germany</I><P>
<DL>
<DT>
<A HREF="DATEABS.HTM;1#07b_1"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/07B_1.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Reduced-Order Modeling of Large Linear Passive Multi-Terminal Circuits
Using Matrix-Padé Approximation [p 530]
<DD><I>R.W. Freund and P. Feldmann</I><P>
<DT>
<A HREF="DATEABS.HTM;1#07b_2"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/07B_2.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
An Efficient Algorithm for Fast Parasitic Extraction and Passive
Order Reduction of 3D Interconnect Models [p 538]
<DD><I>N. Marques, M. Kamon, J. White, and L.M. Silveira</I><P>
<DT>
<A HREF="DATEABS.HTM;1#07b_3"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/07B_3.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
MCM Interconnect Design Using Two-Pole Approximation [p 544]
<DD><I>J. Shao and R.M.M. Chen</I><P>
</DL>
<HR>
<H2>Session 7C:<A HREF="DATEABS.HTM;1#sess7c" NAME="sess7c">
Design for Manufacturability - Embedded Tutorial
</A></H2>
Moderators: <I>M. Servit, Czech Technical University, Czech Republic,<BR>
R. Peset Llopis, Philips Research Laboratories, The Netherlands</I><P>
<DL>
<DT>
<A HREF="DATEABS.HTM;1#07c_1"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/07C_1.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Design-Manufacturing Interface: Part I - Vision [p 550]
<DD><I>W. Maly, H.T. Heineken, J. Khare, and P.K. Nag</I><P>
<DT>
<A HREF="DATEABS.HTM;1#07c_2"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/07C_2.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Design-Manufacturing Interface: Part II - Applications [p 557]
<DD><I>W. Maly, H.T. Heineken, J. Khare, P.K. Nag, P. Simon, and C. Ouyang</I><P>
<DT>
<A HREF="DATEABS.HTM;1#07c_3"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/07C_3.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Performance - Manufacturability Tradeoffs in IC Design [p 563]
<DD><I>H.T. Heineken and W. Maly</I><P>
</DL>
<HR>
<H2>Session 7D:<A HREF="DATEABS.HTM;1#sess7d" NAME="sess7d">
Sequential Circuit Testing
</A></H2>
Moderators: <I> C. Landrault, LIRMM, France,<BR>
D. Medina, Italtel, Italy</I><P>
<DL>
<DT>
<A HREF="DATEABS.HTM;1#07d_1"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/07D_1.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Fast Sequential Circuit Test Generation Using High-Level and
Gate-Level Techniques [p 570]
<DD><I>E.M. Rudnick, R. Vietti, A. Ellis, F. Corno,
P. Prinetto, and M. Sonza Reorda</I><P>
<DT>
<A HREF="DATEABS.HTM;1#07d_2"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/07D_2.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
State Relaxation Based Subsequence Removal for Fast Static Compaction
in Sequential Circuits [p 577]
<DD><I>M.S. Hsiao and S.T. Chakradhar</I><P>
<DT>
<A HREF="DATEABS.HTM;1#07d_3"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/07D_3.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Procedures for Static Compaction of Test Sequences for Synchronous
Sequential Circuits Based on Vector Restoration [p 583]
<DD><I>R. Guo, I. Pomeranz, and S.M. Reddy</I><P>
</DL>
<HR>
<H2>Session 8A:<A HREF="DATEABS.HTM;1#sess8a" NAME="sess8a">
Issues in Behavioral Synthesis
</A></H2>
Moderators: <I>J. van Meerbergen, Philips Research Laboratories, <BR>
The Netherlands, H. Hermanani, Lebanese American University, Lebanon</I><P>
<DL>
<DT>
<A HREF="DATEABS.HTM;1#08a_1"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/08A_1.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Architectural Simulation in the Context of Behavioral Synthesis [p 590]
<DD><I>A. Jemai, P. Kission, and A.A. Jerraya</I><P>
<DT>
<A HREF="DATEABS.HTM;1#08a_2"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/08A_2.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Scheduling of Outputs in Grammar-Based Hardware Synthesis of Data
Communication Protocols [p 596]
<DD><I>J. Öberg, A. Kumar, and A. Hemani</I><P>
<DT>
<A HREF="DATEABS.HTM;1#08a_3"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/08A_3.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Concurrent Error Recovery with Near-Zero Latency in Synthesized ASICs [p 604]
<DD><I>S.N. Hamilton and A. Orailoglu</I><P>
</DL>
<HR>
<H2>Session 8B:<A HREF="DATEABS.HTM;1#sess8b" NAME="sess8b">
Formal Equivalence Checking Using Decision Diagrams
</A></H2>
Moderators: <I>T. Filkorn, Siemens AG, Germany,<BR>
H. Eveking, Darmstadt University of Technology, Germany</I><P>
<DL>
<DT>
<A HREF="DATEABS.HTM;1#08b_1"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/08B_1.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Dynamic Minimization of Word-Level Decision Diagrams [p 612]
<DD><I>S. Höreth and R. Drechsler</I><P>
<DT>
<A HREF="DATEABS.HTM;1#08b_2"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/08B_2.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Sequential Equivalence Checking without State Space Traversal [p 618]
<DD><I>C.A.J. van Eijk</I><P>
<DT>
<A HREF="DATEABS.HTM;1#08b_3"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/08B_3.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
On the Reuse of Symbolic Simulation Results for Incremental Equivalence
Verification of Switch-Level Circuits [p 624]
<DD><I>L. Ribas-Xirgo and J. Carrabina-Bordoll</I><P>
</DL>
<HR>
<H2>Session 8C:<A HREF="DATEABS.HTM;1#sess8c" NAME="sess8c">
Hot Topic: Silicon Debug of Systems-on-Chips
</A></H2>
Organizer & Moderator: <I>Erik Jan Marinissen, Philips Research Labs, The
Netherlands co-organized in cooperation with IEEE's Design & Test of
Computers</I><P>
Speakers: <I>Karel van Doorselaer, Alcatel Telecom, Belgium<BR>
Sridhar Narayanan, Sun Microsystems, USA<BR>
Gert Jan van Rootselaar, Philips Research Labs, The Netherlands
</I><P>
<DL>
<DT>
<A HREF="DATEABS.HTM;1#08c_1"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/08C_1.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Silicon Debug of Systems-on-Chips [p 632]
</DL>
<HR>
<H2>Session 8D:<A HREF="DATEABS.HTM;1#sess8d" NAME="sess8d">
Characterization and Verification of Analogue Circuits
</A></H2>
Moderators: <I>G. Gielen, Katholieke Universiteit Leuven, Belgium,<BR>
C. Descleves, Dolphin Integration, France</I><P>
<DL>
<DT>
<A HREF="DATEABS.HTM;1#08d_1"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/08D_1.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Hierarchical Characterization of Analog Integrated CMOS Circuits [p 636]
<DD><I>J. Ecküller, M. Gröpl, and H. Gräb</I><P>
<DT>
<A HREF="DATEABS.HTM;1#08d_2"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/08D_2.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
EASY - A System for Computer-Aided Examination of Analog Circuits [p 644]
<DD><I>G. Dröge, M. Thole, and E.-H. Horneber</I><P>
<DT>
<A HREF="DATEABS.HTM;1#08d_3"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/08D_3.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
A Formal Approach to Verification of Linear Analog Circuits with
Parameter Tolerances [p 649]
<DD><I>L. Hedrich and E. Barke</I><P>
</DL>
<HR>
<H2>Session 9A:<A HREF="DATEABS.HTM;1#sess9a" NAME="sess9a">
Benchmark Circuits, Technology Mapping and Scan Chains
</A></H2>
Moderators: <I>A. ten Berg, Philips Research Laboratories, The Netherlands,<BR>
M. Berkelaar, Eindhoven University of Technology, The Netherlands</I><P>
<DL>
<DT>
<A HREF="DATEABS.HTM;1#09a_1"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/09A_1.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Synthesis of Wiring Signature-Invariant Equivalence Class Circuit
Mutants and Applications to Benchmarking [p 656]
<DD><I>D. Ghosh, N. Kapur, J. Harlow III, and F. Brglez</I><P>
<DT>
<A HREF="DATEABS.HTM;1#09a_2"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/09A_2.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Technology Mapping for Minimizing Gate and Routing Area [p 664]
<DD><I>A. Lu, G. Stenz, and F.M. Johannes</I><P>
<DT>
<A HREF="DATEABS.HTM;1#09a_3"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/09A_3.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Exploiting Symbolic Techniques for Partial Scan Flip Flop Selection [p 670]
<DD><I>F. Corno, P. Prinetto, M. Sonza Reorda, and M. Violante</I><P>
</DL>
<HR>
<H2>Session 9B:<A HREF="DATEABS.HTM;1#sess9b" NAME="sess9b">
Physical to Gate Level Design for Low-Power
</A></H2>
Moderators: <I>C. Piguet, CSEM, Switzerland,<BR>
E. Macii, Politecnico di Torino, Italy</I><P>
<DL>
<DT>
<A HREF="DATEABS.HTM;1#09b_1"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/09B_1.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Temperature Effect on Delay for Low Voltage Applications [p 680]
<DD><I>J.M. Daga, E. Ottaviano, and D. Auvergne</I><P>
<DT>
<A HREF="DATEABS.HTM;1#09b_2"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/09B_2.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Data Driven Power Optimization of Sequential Circuits [p 686]
<DD><I>Q. Wang and S.B.K. Vrudhula</I><P>
<DT>
<A HREF="DATEABS.HTM;1#09b_3"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/09B_3.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Gated Clock Routing Minimizing the Switched Capacitance [p 692]
<DD><I>J. Oh and M. Pedram</I><P>
<DT>
<A HREF="DATEABS.HTM;1#09b_4"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/09B_4.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Exact and Approximate Estimation for Maximum Instantaneous Current
of CMOS Circuits [p 698]
<DD><I>Y.-M. Jiang and K.-T. Cheng</I><P>
</DL>
<HR>
<H2>Session 9C:<A HREF="DATEABS.HTM;1#sess9c" NAME="sess9c">
Hot Topic: Embedded Memory and Embedded Logic
</A></H2>
Co-ordinator: <I>Ivo Bolsens, IMEC, Belgium</I><P>
Moderator: <I>Ivo Bolsens, IMEC, Belgium</I><P>
Speakers: <I>Norbert Wehn, University of Kaiserslautern, Germany<BR>
Soren Hein, Siemens, Germany<BR>
Francky Catthoor, IMEC, Belgium<BR>
Roelof Salters, Philips Research Labs, The Netherlands
</I><P>
<DL>
<DT>
<A HREF="DATEABS.HTM;1#09c_1"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/09C_1.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Embedded DRAM Architectural Trade-Offs [p 704]
<DD><I>N. Wehn and S. Hein</I><P>
<DT>
<A HREF="DATEABS.HTM;1#09c_2"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/09C_2.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Energy-Delay Efficient Data Storage and Transfer Architectures: Circuit
Technology Versus Design Methodology Solutions [p 709]
<DD><I>F. Catthoor</I><P>
</DL>
<HR>
<H2>Session 9D:<A HREF="DATEABS.HTM;1#sess9d" NAME="sess9d">
Analogue Circuit Modeling and Design Methodology
</A></H2>
Moderators: <I>J. Franca, IST, Lisbon, Portugal,<BR>
H. Kerkhoff, University of Twente, The Netherlands</I><P>
<DL>
<DT>
<A HREF="DATEABS.HTM;1#09d_1"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/09D_1.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Hierarchical Top-Down Design of Analog Sensor Interfaces: From
System-Level Specifications Down to Silicon [p 716]
<DD><I>J. Vandenbussche, S. Donnay, F. Leyn, G. Gielen, and W. Sansen</I><P>
<DT>
<A HREF="DATEABS.HTM;1#09d_2"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/09D_2.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
A Systems Theoretic Approach to Behavioural Modeling and Simulation
of Analog Functional Blocks [p 721]
<DD><I>R. Rosenberger and S.A. Huss</I><P>
<DT>
<A HREF="DATEABS.HTM;1#09d_3"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/09D_3.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Switching Response Modeling of the CMOS Inverter for Sub-Micron Devices [p 729]
<DD><I>L. Bisdounis, S. Nikolaidis, O. Koufopavlou, and C.E. Goutis</I><P>
</DL>
<HR>
<H2>Session 10A:<A HREF="DATEABS.HTM;1#sess10a" NAME="sess10a">
Combinational Logical Synthesis
</A></H2>
Moderators: <I>M. Berkelaar, Eindhoven University of Technology, <BR>
The Netherlands, L. Stok, IBM T.J. Watson Research Center, USA</I><P>
<DL>
<DT>
<A HREF="DATEABS.HTM;1#10a_1"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/10A_1.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
On Removing Multiple Redundancies in Combinational Circuits [p 738]
<DD><I>S.-C. Chang, D.I. Cheng, and C.-W. Yeh</I><P>
<DT>
<A HREF="DATEABS.HTM;1#10a_2"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/10A_2.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Multi-Output Functional Decomposition with Exploitation of Don't Cares
[p 743]
<DD><I>C. Scholl</I><P>
<DT>
<A HREF="DATEABS.HTM;1#10a_3"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/10A_3.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
An Efficient Divide and Conquer Algorithm for Exact Hazard Free
Logic Minimization [p 749]
<DD><I>J.W.J.M. Rutten, M.R.C.M. Berkelaar, C.A.J. van Eijk, and M.A.J.
Kolsteren</I><P>
<DT>
<A HREF="DATEABS.HTM;1#10a_4"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/10A_4.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Restructuring Logic Representations with Easily Detectable Simple
Disjunctive Decompositions [p 755]
<DD><I>H. Sawada, S. Yamashita, and A. Nagoya</I><P>
</DL>
<HR>
<H2>Session 10B:<A HREF="DATEABS.HTM;1#sess10b" NAME="sess10b">
High Level Power Estimation
</A></H2>
Moderators: <I>W. Nebel, University of Oldenburg and OFFIS, Germany,<BR>
J. Benkoski, Synopsys, France</I><P>
<DL>
<DT>
<A HREF="DATEABS.HTM;1#10b_1"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/10B_1.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Power Estimation of Behavioral Descriptions [p 762]
<DD><I>F. Ferrandi, F. Fummi, E. Macii, M. Poncino, and D. Sciuto</I><P>
<DT>
<A HREF="DATEABS.HTM;1#10b_2"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/10B_2.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Characterization-Free Behavioral Power Modeling [p 767]
<DD><I>A. Bogliolo, L. Benini, and G. De Micheli</I><P>
<DT>
<A HREF="DATEABS.HTM;1#10b_3"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/10B_3.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Trace-Driven Steady-State Probability Estimation in FSMs with
Application to Power Estimation [p 774]
<DD><I>D. Marculescu, R. Marculescu, and M. Pedram</I><P>
</DL>
<HR>
<H2>Session 10C:<A HREF="DATEABS.HTM;1#sess10c" NAME="sess10c">
Petri Nets and Dedicated Formalisms
</A></H2>
Moderators: <I>L. Claesen, IMEC, Belgium, C. Delgado Kloos, <BR>
ETSI Telecommunicacion, Spain</I><P>
<DL>
<DT>
<A HREF="DATEABS.HTM;1#10c_1"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/10C_1.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Efficient Verification Using Generalized Partial Order Analysis [p 782]
<DD><I>S. Vercauteren, D. Verkest, G. de Jong, and B. Lin</I><P>
<DT>
<A HREF="DATEABS.HTM;1#10c_2"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/10C_2.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Efficient Encoding Schemes for Symbolic Analysis of Petri Nets [p 790]
<DD><I>E. Pastor and J. Cortadella</I><P>
<DT>
<A HREF="DATEABS.HTM;1#10c_3"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/10C_3.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Propagation of Last-Transition-Time Constraints in Gate-Level
Timing Analysis [p 796]
<DD><I>M. Kassab, E. Cerny, S. Aourid, and T. Krodel</I><P>
<DT>
<A HREF="DATEABS.HTM;1#10c_4"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/10C_4.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Combinational Verification Based on High-Level Functional Specifications
[p 803]
<DD><I>E.I. Goldberg, Y. Kukimoto, and R.K. Brayton</I><P>
</DL>
<HR>
<H2>Session 10D:<A HREF="DATEABS.HTM;1#sess10d" NAME="sess10d">
Mixed-Signal Test and DFT
</A></H2>
Moderators: <I>A. Richardson, University of Lancaster, UK,<BR>
M. Sachdev, Philips Research Laboratories, The Netherlands</I><P>
<DL>
<DT>
<A HREF="DATEABS.HTM;1#10d_1"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/10D_1.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Switch-Level Fault Coverage Analysis for Switched-Capacitor Systems [p 810]
<DD><I>S. Mir, A. Rueda, D. Vázquez, and J.L. Huertas</I><P>
<DT>
<A HREF="DATEABS.HTM;1#10d_2"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/10D_2.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Optimized Implementations of the Multi-Configuration DFT Technique
for Analog Circuits [p 815]
<DD><I>M. Renovell, F. Azaïs, and Y. Bertrand</I><P>
<DT>
<A HREF="DATEABS.HTM;1#10d_3"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/10D_3.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Analog Test Design with IDD Measurements for the Detection of
Parametric and Catastrophic Faults [p 822]
<DD><I>W.M. Lindermeir, T.J. Vogels, and H.E. Graeb</I><P>
</DL>
<HR>
<H2>Session 11A:<A HREF="DATEABS.HTM;1#sess11a" NAME="sess11a">
Sequential Logic Synthesis
</A></H2>
Moderators: <I>L. Stok, IBM T.J. Watson Research Center, USA<BR>
A. ten Berg, Philips Research Laboratories, The Netherlands</I><P>
<DL>
<DT>
<A HREF="DATEABS.HTM;1#11a_1"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/11A_1.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
A New Paradigm for Dichotomy-Based Constrained Encoding [p 830]
<DD><I>O. Coudert</I><P>
<DT>
<A HREF="DATEABS.HTM;1#11a_2"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/11A_2.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
A Dynamic Model for the State Assignment Problem [p 835]
<DD><I>M. Martínez, M.J. Avedillo, J.M. Quintana, and J.L. Huertas</I><P>
<DT>
<A HREF="DATEABS.HTM;1#11a_3"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/11A_3.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Efficient Minarea Retiming of Large Level-Clocked Circuits [p 840]
<DD><I>N. Maheshwari and S.S. Sapatnekar</I><P>
</DL>
<HR>
<H2>Session 11B:<A HREF="DATEABS.HTM;1#sess11b" NAME="sess11b">
High-Level Power Optimization
</A></H2>
Moderators: <I>M. Pedram, University of Southern California, USA,<BR>
M. Poncino, Politecnico di Torino, Italy</I><P>
<DL>
<DT>
<A HREF="DATEABS.HTM;1#11b_1"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/11B_1.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
IMPACT: A High-Level Synthesis System for Low Power Control-Flow
Intensive Circuits [p 848]
<DD><I>K.S. Khouri, G. Lakshminarayana, and N.K. Jha</I><P>
<DT>
<A HREF="DATEABS.HTM;1#11b_2"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/11B_2.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Instruction Scheduling for Power Reduction in Processor-Based System Design [p 855]
<DD><I>H. Tomiyama, T. Ishihara, A. Inoue, and H. Yasuura</I><P>
<DT>
<A HREF="DATEABS.HTM;1#11b_3"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/11B_3.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Address Bus Encoding Techniques for System-Level Power Optimization [p 861]
<DD><I>L. Benini, G. De Micheli, E. Macii, D. Sciuto, and C. Silvano</I><P>
</DL>
<HR>
<H2>Session 11C:<A HREF="DATEABS.HTM;1#sess11c" NAME="sess11c">
System Architecture Design
</A></H2>
Moderators: <I>M. Kovac, University of Zagreb, Croatia,<BR>
W. Glauert, University of Erlangen-Nurnberg, Germany</I><P>
<DL>
<DT>
<A HREF="DATEABS.HTM;1#11c_1"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/11C_1.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
A Scalable Architecture for Multi-Threaded JAVA Applications [p 868]
<DD><I>M. Mrva, K. Buchenrieder, and R. Kress</I><P>
<DT>
<A HREF="DATEABS.HTM;1#11c_2"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/11C_2.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Hardware/Software Co-Design of a Fuzzy RISC Processor [p 875]
<DD><I>V. Salapura and M. Gschwind</I><P>
<DT>
<A HREF="DATEABS.HTM;1#11c_3"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/11C_3.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Innovative System-Level Design Environment Based on FORM for
Transport Processing System [p 883]
<DD><I>K. Higuchi and K. Shirakawa</I><P>
</DL>
<HR>
<H2>Session 11D:<A HREF="DATEABS.HTM;1#sess11d" NAME="sess11d">
Simulation and Test Tools for Analogue Circuits
</A></H2>
Moderators: <I>J.L. Huertas, Centro Nacional de Microelectronica, Spain,<BR>
J. Pikkarainen, Nokia Mobile Phones, Finland</I><P>
<DL>
<DT>
<A HREF="DATEABS.HTM;1#11d_1"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/11D_1.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Efficient Techniques for Accurate Modeling and Simulation of Substrate
Coupling in Mixed-Signal IC's [p 892]
<DD><I>J.P. Costa, M. Chou, and L.M. Silveira</I><P>
<DT>
<A HREF="DATEABS.HTM;1#11d_2"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/11D_2.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Efficient DC Fault Simulation of Nonlinear Analog Circuits [p 899]
<DD><I>M.W. Tian and C.-J.R. Shi</I><P>
<DT>
<A HREF="DATEABS.HTM;1#11d_3"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/11D_3.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
An Approach to Realistic Fault Prediction and Layout Design for
Testability in Analog Circuits [p 905]
<DD><I>J.A. Prieto, A. Rueda, I. Grout, E. Peralías,
J.L. Huertas, and A.M.D. Richardson</I><P>
</DL>
<HR>
<H2><A HREF="DATEABS.HTM;1#poster" NAME="poster">Poster Session:</A></H2>
<DL>
<DT>
<A HREF="DATEABS.HTM;1#poster01"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/POSTER01.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Synthesis of Communicating Controllers for Concurrent
Hardware/Software Systems [p 912]
<DD><I>R. Niemann and P. Marwedel</I><P>
<DT>
<A HREF="DATEABS.HTM;1#poster02"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/POSTER02.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
A Knowledge-Based System for Hardware-Software Partitioning [p 914]
<DD><I>M.L. López, C.A. Iglesias, and J.C. López</I><P>
<DT>
<A HREF="DATEABS.HTM;1#poster03"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/POSTER03.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
A Formal Description of VHDL-AMS Analogue Systems [p 916]
<DD><I>T. Kazmierski</I><P>
<DT>
<A HREF="DATEABS.HTM;1#poster04"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/POSTER04.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Scanning Datapaths: A Fast and Effective Partial Scan Selection Technique [p 921]
<DD><I>M.L. Flottes, R. Pires, B. Rouzeyre, and L. Volpe</I><P>
<DT>
<A HREF="DATEABS.HTM;1#poster05"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/POSTER05.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Universal Strong Encryption FPGA Core Implementation [p 923]
<DD><I>D. Runje and M. Kovac</I><P>
<DT>
<A HREF="DATEABS.HTM;1#poster06"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/POSTER06.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Data Cache Sizing for Embedded Processor Applications [p 925]
<DD><I>P.R. Panda, N.D. Dutt, and A. Nicolau</I><P>
<DT>
<A HREF="DATEABS.HTM;1#poster07"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/POSTER07.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
A Programmable Multi-Language Generator for CoDesign [p 927]
<DD><I>J.P. Calvez, D. Heller, F. Muller, O. Pasquier</I><P>
<DT>
<A HREF="DATEABS.HTM;1#poster08"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/POSTER08.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Register-Constrained Address Computation in DSP Programs [p 929]
<DD><I>A. Basu, R. Leupers, and P. Marwedel</I><P>
<DT>
<A HREF="DATEABS.HTM;1#poster09"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/POSTER09.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Graphical Entry of FSMDs Revisited: Putting Graphical Models
on a Solid Base [p 931]
<DD><I>T. Müller-Wipperfürth and R. Hagelauer</I><P>
<DT>
<A HREF="DATEABS.HTM;1#poster10"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/POSTER10.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
AGENDA: An Attribute Grammar Driven Environment for the Design
Automation of Digital Systems [p 933]
<DD><I>G. Economakos, G. Papakonstantinou, and P. Tsanakas</I><P>
<DT>
<A HREF="DATEABS.HTM;1#poster11"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/POSTER11.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Static Analysis Tools for Soft-Core Reviews and Audits [p 935]
<DD><I>S. Olcoz, A. Castellví, M. García, and J.-A. Gómez
</I><P>
<DT>
<A HREF="DATEABS.HTM;1#poster12"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/POSTER12.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
A VHDL SGRAM Model for the Validation Environment of a High Performance
Graphic Processor [p 937]
<DD><I>M.G. Wahl and H. Völkel</I><P>
<DT>
<A HREF="DATEABS.HTM;1#poster13"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/POSTER13.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
A Comparing Study of Technology Mapping for FPGA [p 939]
<DD><I>H.-G. Martin and W. Rosenstiel</I><P>
<DT>
<A HREF="DATEABS.HTM;1#poster14"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/POSTER14.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Fuzzy-Logic Digital-Analogue Interfaces for Accurate Mixed-Signal
Simulation [p 941]
<DD><I>T.J. Kazmierski</I><P>
<DT>
<A HREF="DATEABS.HTM;1#poster15"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/POSTER15.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Optimized Timed Hardware Software Cosimulation without Roll-Back [p 945]
<DD><I>W. Sung and S. Ha</I><P>
<DT>
<A HREF="DATEABS.HTM;1#poster16"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/POSTER16.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
A Cell and Macrocell Compiler for GaAs VLSI Full-Custom Design [p 947]
<DD><I>J.A. Montiel-Nelson, V. de Armas, R. Sarmiento, and A. Núnez</I><P>
<DT>
<A HREF="DATEABS.HTM;1#poster17"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/POSTER17.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Architectural Rule Checking for High-Level Synthesis [p 949]
<DD><I>J. Gong, C.-T. Chen, and K. Kücükcakar</I><P>
<DT>
<A HREF="DATEABS.HTM;1#poster18"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/POSTER18.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
A Unified Technique for PCB/MCM Design by Combining Electromagnetic
Field Analysis with Circuit Simulator [p 951]
<DD><I>H. Kimura and N. Iyenaga</I><P>
<DT>
<A HREF="DATEABS.HTM;1#poster19"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/POSTER19.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Core Interconnect Testing Hazards [p 953]
<DD><I>P. Nordholz, H. Grabinski, D. Treytnar, J. Otterstedt,
D. Niggemeyer, U. Arz, and T.W. Williams</I><P>
<DT>
<A HREF="DATEABS.HTM;1#poster20"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/POSTER20.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Quality Estimation of Test Vectors and Functional Validation Procedures
Based on Fault and Error Models [p 955]
<DD><I>T. Riesgo, Y. Torroja, E. de la Torre, and J. Uceda</I><P>
<DT>
<A HREF="DATEABS.HTM;1#poster21"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/POSTER21.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Fault Analysis in Networks with Concurrent Error Detection Properties [p 957]
<DD><I>C. Bolchini, F. Salice, and D. Sciuto</I><P>
<DT>
<A HREF="DATEABS.HTM;1#poster22"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/POSTER22.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
IOCIMU - An Integrated Off-Chip I<SUB>DDQ</SUB> Measurement Unit [p 959]
<DD><I>M. Svajda, B. Straka, and H. Manhaeve</I><P>
<DT>
<A HREF="DATEABS.HTM;1#poster23"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/POSTER23.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Automatic Topology Optimization for Analog Module Generators [p 961]
<DD><I>M. Wolf and U. Kleine</I><P>
<DT>
<A HREF="DATEABS.HTM;1#poster24"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/POSTER24.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Asynchronous Scheduling and Allocation [p 963]
<DD><I>A. Prihozhy</I><P>
<DT>
<A HREF="DATEABS.HTM;1#poster25"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/POSTER25.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Path Verification Using Boolean Satisfiability [p 965]
<DD><I>M. Ringe, T. Lindenkreuz, and E. Barke</I><P>
<DT>
<A HREF="DATEABS.HTM;1#poster26"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/POSTER26.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
PowerShake: A Low Power Driven Clustering and Factoring Methodology
for Boolean Expressions [p 967]
<DD><I>S. Roy, H. Arts, and P. Banerjee</I><P>
<DT>
<A HREF="DATEABS.HTM;1#poster27"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/POSTER27.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Power and Timing Modeling for ASIC Designs [p 969]
<DD><I>W. Roethig, A.M. Zarkesh, and M. Andrews</I><P>
<DT>
<A HREF="DATEABS.HTM;1#poster28"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/POSTER28.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Constraints Space Management for the Layout of Analog IC's [p 971]
<DD><I>B.G. Arsintescu and R.H.J.M. Otten</I><P>
<DT>
<A HREF="DATEABS.HTM;1#poster29"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/POSTER29.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
A Synthesis Procedure for Flexible Logic Functions [p 973]
<DD><I>I. Pomeranz and S.M. Reddy</I><P>
<DT>
<A HREF="DATEABS.HTM;1#poster30"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/POSTER30.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Denotational Semantics of a Behavioral Subset of VHDL [p 975]
<DD><I>F. Nicoli</I><P>
<DT>
<A HREF="DATEABS.HTM;1#poster31"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/POSTER31.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Correct High-Level Synthesis: A Formal Perspective [p 977]
<DD><I>J.M. Mendías, R. Hermida, and M. Fernández</I><P>
<DT>
<A HREF="DATEABS.HTM;1#poster32"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/POSTER32.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
A Bypass Scheme for Core-Based System Fault Testing [p 979]
<DD><I>M. Nourani and C. Papachristou</I><P>
<DT>
<A HREF="DATEABS.HTM;1#poster33"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/POSTER33.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Highly Testable and Compact 1-out-of-n Code Checker with Single Output
[p 981]
<DD><I>C. Metra, M. Favalli, and B. Ricco</I><P>
<DT>
<A HREF="DATEABS.HTM;1#poster34"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/POSTER34.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Design-for-Testability for Synchronous Sequential Circuits Using
Locally Available Lines [p 983]
<DD><I>I. Pomeranz and S.M. Reddy</I><P>
<DT>
<A HREF="DATEABS.HTM;1#poster35"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/POSTER35.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
CMOS Combinational Circuit Sizing by Stage-Wise Tapering [p 985]
<DD><I>S. Pullela, R. Panda, A. Dharchoudhury, G. Vijayan, and D. Blaauw</I><P>
<DT>
<A HREF="DATEABS.HTM;1#poster36"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/POSTER36.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Fault Detection for Linear Analog Circuits Using Current Injection [p 987]
<DD><I>J. Velasco-Medina, T. Calin, and M. Nicolaidis</I><P>
</DL>
</B>
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