<![CDATA[
<BODY>
<H3><A HREF="../../../../../MAIN_DH.HTM;1">Main Page</A></BR>
DATE 2001 :
[ <A HREF="DATEABS.HTM;1">Abstracts</A> ]
[ <A HREF="DATESESS.HTM;1">Session Index</A> ]
[ <A HREF="DATEAI.HTM;1">Author Index</A> ]</H3>
<HR>
<H2>DATE 2001 TABLE OF CONTENTS</H2>
<B>
Sessions:
[<A HREF="#keynote">Keynote</A>]
[<A HREF="#sess1a">1A</A>]
[<A HREF="#sess1b">1B</A>]
[<A HREF="#sess1c">1C</A>]
[<A HREF="#sess1e">1E</A>]
[<A HREF="#sess2a">2A</A>]
[<A HREF="#sess2b">2B</A>]
[<A HREF="#sess2c">2C</A>]
[<A HREF="#sess2e">2E</A>]
[<A HREF="#sess3a">3A</A>]
[<A HREF="#sess3b">3B</A>]
[<A HREF="#sess3c">3C</A>]
[<A HREF="#sess3e">3E</A>]
[<A HREF="#sess4a">4A</A>]
[<A HREF="#sess4b">4B</A>]
[<A HREF="#sess4c">4C</A>]
[<A HREF="#sess4e">4E</A>]
[<A HREF="#sess4f">4F</A>]
[<A HREF="#sess5a">5A</A>]
[<A HREF="#sess5b">5B</A>]
[<A HREF="#sess5c">5C</A>]
[<A HREF="#sess5e">5E</A>]
[<A HREF="#sess5f">5F</A>]
[<A HREF="#sess6a">6A</A>]
[<A HREF="#sess6b">6B</A>]
[<A HREF="#sess6c">6C</A>]
[<A HREF="#sess6e">6E</A>]
[<A HREF="#sess6f">6F</A>]
[<A HREF="#sess7a">7A</A>]
[<A HREF="#sess7b">7B</A>]
[<A HREF="#sess7c">7C</A>]
[<A HREF="#sess7e">7E</A>]
[<A HREF="#sess7f">7F</A>]
[<A HREF="#sess8a">8A</A>]
[<A HREF="#sess8b">8B</A>]
[<A HREF="#sess8c">8C</A>]
[<A HREF="#sess8e">8E</A>]
[<A HREF="#sess8f">8F</A>]
[<A HREF="#sess9a">9A</A>]
[<A HREF="#sess9b">9B</A>]
[<A HREF="#sess9c">9C</A>]
[<A HREF="#sess9e">9E</A>]
[<A HREF="#sess9f">9F</A>]
[<A HREF="#sess9l">9L</A>]
[<A HREF="#sess10a">10A</A>]
[<A HREF="#sess10b">10B</A>]
[<A HREF="#sess10c">10C</A>]
[<A HREF="#sess10e">10E</A>]
[<A HREF="#sess10f">10F</A>]
[<A HREF="#poster">Posters</A>]<P>
<A HREF="../../PDFFILES/EXECOM.PDF;1">DATE Executive Committee</A><BR>
<A HREF="../../PDFFILES/TECHPGM.PDF;1">Technical Program Chairs</A><BR>
<A HREF="../../PDFFILES/VENSPON.PDF;1">Vendors Committee</A><BR>
<A HREF="../../PDFFILES/VENSPON.PDF;1">DATE Sponsor Committee</A><BR>
<A HREF="../../PDFFILES/TECHCOM.PDF;1">Technical Program Committee</A><BR>
<A HREF="../../PDFFILES/REVIEWER.PDF;1">Reviewers</A><BR>
<A HREF="../../PDFFILES/WELCOME.PDF;1">Welcome to DATE 2001</A><BR>
<A HREF="../../PDFFILES/BESTPPR.PDF;1">Best Paper Awards</A><BR>
<A HREF="../../PDFFILES/TUTORIAL.PDF;1">Tutorials</A><BR>
<A HREF="../../PDFFILES/CFP.PDF;1">Call for Papers DATE 2002</A><P>
</B>
<HR>
<A HREF="DATEABS.HTM;1#keynote" NAME="keynote">
<H2>Plenary - Keynote Session<BR>
</A></H2>
<I> Moderator: A. Jerraya, TIMA, Grenoble, F</I><P>
<DL>
<DT>
The Semiconductor Dynamic in the Information Age - Driving New
Technologies, Trends and Markets
<DD><I>
U. Schumacher, CEO, Infineon, Munich, D
</I><P>
</DL>
<HR>
<H2>1A: <A HREF="DATEABS.HTM;1#sess1a" NAME="sess1a">
Complementary Approaches to Designing Correct Circuits
</A></H2>
<I>Moderators: T. Kropf, Robert Bosch GmbH, D; H. Eveking, TU Darmstadt, D</I><P>
<DL>
<DT>
<A HREF="DATEABS.HTM;1#01a_1"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/01A_1.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Abstraction of Word-Level Linear Arithmetic Functions from Bit-Level Component
Descriptions [p. 4]
<DD><I>
P. Dasgupta, P. Chakrabarti, A. Nandi, S. Krishna, and A. Chakrabarti
</I><P>
<DT>
<A HREF="DATEABS.HTM;1#01a_2"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/01A_2.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Biasing Symbolic Search by Means of Dynamic Activity Profiles [p. 9]
<DD><I>
G. Cabodi, P. Camurati, and S. Quer
</I><P>
</DL>
<HR>
<H2>1B: <A HREF="DATEABS.HTM;1#sess1b" NAME="sess1b">
New Design Methods with SystemC
</A></H2>
<I>Moderators: W. Rosenstiel, FZI/Tuebingen U, D; E. Villar, Cantabria U, ES
</I><P>
<DL>
<DT>
<A HREF="DATEABS.HTM;1#01b_1"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/01B_1.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
A Methodology for Interfacing Open Source SystemC with a Third Party Software
[p. 16]
<DD><I>
L. Charest, M. Reid, E. Aboulhamid, and G. Bois
</I><P>
<DT>
<A HREF="DATEABS.HTM;1#01b_2"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/01B_2.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Behavioral Synthesis with SystemC [p. 21]
<DD><I>
G. Economakos, P. Oikonomakos, I. Panagopoulos, I. Poulakis, and G.
Papakonstantinou
</I><P>
<DT>
<A HREF="DATEABS.HTM;1#01b_3"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/01B_3.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
SystemC<SUP>SV</SUP> - An Extension of SystemC for Mixed Multi-Level
Communication Modeling and Interface-Based System Design [p. 26]
<DD><I>
R. Siegmund and D. Müller
</I><P>
</DL>
<HR>
<H2>1C: <A HREF="DATEABS.HTM;1#sess1c" NAME="sess1c">
Embedded Tutorial: TRP: Integrating Embedded Test and ATE
</A></H2>
<I>
Organizer: Y. Zorian, LogicVision, USA<BR>
Moderator: P. Prinetto, Politecnico di Torino, IT<BR>
Speakers: J. Teixeira, IST/INESC, PT; I. Teixeira, IST/INESC, PT; C. Pereira,
UFRGS, BR; O. Dias, IST/INESC, PT; J. Semiao, IST/INESC, PT; P. Muhmenthaler,
Infineon, D; Y. Zorian, LogicVision, USA; W. Radermacher, Agilent, USA
</I><P>
<DL>
<DT>
<A HREF="DATEABS.HTM;1#01c_1"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/01C_1.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Test Resource Partitioning: A Design and Test Issue [p. 34]
</DL>
<HR>
<H2>1E: <A HREF="DATEABS.HTM;1#sess1e" NAME="sess1e">
Embedded Tutorial: Current Trends in the Design of
Automotive Electronic Systems
</A></H2>
<I>Organizer and Moderator: P. van Staa, Robert Bosch GmbH, D<BR>
Speaker: T. Beck, ETAS GmbH, D</I><P>
<DL>
<DT>
<A HREF="DATEABS.HTM;1#01e_1"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/01E_1.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Current Trends in the Design of Automotive Electronic Systems [p. 38]
</DL>
<HR>
<H2>2A: <A HREF="DATEABS.HTM;1#sess2a" NAME="sess2a">
Platforms and IP-Based Design
</A></H2>
<I> Moderators: G. Martin, Cadence, USA; R. Seepold, FZI, D</I><P>
<DL>
<DT>
<A HREF="DATEABS.HTM;1#02a_1"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/02A_1.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Component Selection and Matching for IP-Based Design [p. 40]
<DD><I>
T. Zhang, L. Benini, and G. De Micheli
</I><P>
<DT>
<A HREF="DATEABS.HTM;1#02a_2"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/02A_2.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
A Universal Communication Model for an Automotive System Integration Platform [p. 47]
<DD><I>
T. Demmeler and P. Giusto
</I><P>
<DT>
<A HREF="DATEABS.HTM;1#02a_3"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/02A_3.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
An Efficient Architecture Model for Systematic Design of Application-Specific
Multiprocessor SoC [p. 55]
<DD><I>
A. Baghdadi, D. Lyonnard, N. Zergainoh, and A. Jerraya
</I><P>
</DL>
<HR>
<H2>2B: <A HREF="DATEABS.HTM;1#sess2b" NAME="sess2b">
Approaching Semantics of Design Languages
</A></H2>
<I>
Moderators: N. Fristacky, Slovak TU, SLK; F. Rammig, C-LAB/Paderborn U, D
</I><P>
<DL>
<DT>
<A HREF="DATEABS.HTM;1#02b_1"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/02B_1.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
The Simulation Semantics of SystemC [p. 64]
<DD><I>
J. Ruf, D. Hoffmann, J. Gerlach, T. Kropf, W. Rosenstiehl, and W. Mueller
</I><P>
<DT>
<A HREF="DATEABS.HTM;1#02b_2"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/02B_2.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
MetaRTL: Raising the Abstraction Level of RTL Design [p. 71]
<DD><I>
J. Zhu
</I><P>
<DT>
<A HREF="DATEABS.HTM;1#02b_3"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/02B_3.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
A Model for Describing Communication between Aggregate Objects in the
Specification and Design of Embedded Systems [p. 77]
<DD><I>
K. Svarstad, G. Nicolescu, and A. Jerraya
</I><P>
</DL>
<HR>
<H2>2C: <A HREF="DATEABS.HTM;1#sess2c" NAME="sess2c">
BIST and Diagnosis
</A></H2>
<I>
Moderators: P. Harrod, ARM, UK; B. Becker, Freiburg U, D
</I><P>
<DL>
<DT>
<A HREF="DATEABS.HTM;1#02c_1"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/02C_1.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Circuit Partitioning for Efficient Logic BIST Synthesis [p. 86]
<DD><I>
A. Irion, G. Kiefer, H. Vranken, and H. Wunderlich
</I><P>
<DT>
<A HREF="DATEABS.HTM;1#02c_2"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/02C_2.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Deterministic Software -Based Self-Testing of Embedded Processor Cores [p. 92]
<DD><I>
A. Paschalis, D. Gizopoulos, N. Kranitis, M. Psarakis, and Y. Zorian
</I><P>
<DT>
<A HREF="DATEABS.HTM;1#02c_3"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/02C_3.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Memory Fault Diagnosis by Syndrome Compression [p. 97]
<DD><I>
J. Li and C. Wu
</I><P>
<DT>
<A HREF="DATEABS.HTM;1#02c_4"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/02C_4.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Diagnosis for Scan-Based BIST: Reaching Deep into the Signatures [p. 102]
<DD><I>
I. Bayraktaroglu and A. Orailoglu
</I><P>
</DL>
<HR>
<H2>2E: <A HREF="DATEABS.HTM;1#sess2e" NAME="sess2e">
Hot Topic : EUCAR Session
</A></H2>
<I>
Organizer: P. van Staa, Robert Bosch GmbH, D<BR>
Moderator: S. Reiniger, DaimlerChrysler, D
</I><P>
<DL>
<DT>
<A HREF="DATEABS.HTM;1#02e_2"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/02E_2.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Vehicle Electric/Electronic Architecture - One of the Most Important
Challenges for OEM's [p. 112]
<DD><I>
G. Hettich and T. Thurner
</I><P>
<DT>
<A HREF="DATEABS.HTM;1#02e_3"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/02E_3.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
AIL: description of a global electronic architecture at the vehicle scale
<DD><I>
Arjun Panday, Damien Couderc, Simon Marichalar
</I><P>
<DT>
<A HREF="DATEABS.HTM;1#02e_4"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/02E_4.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Methods and Tools for Systems Engineering of Automotive Electronic
Architectures
<DD><I>Jakob Axelsson
</I><P>
</DL>
<HR>
<H2>3A: <A HREF="DATEABS.HTM;1#sess3a" NAME="sess3a">
SAT Based Verification Techniques
</A></H2>
<I>Moderators: W. Damm, Oldenburg U/OFFIS, D; C. Delgado Kloos, U Carlos III de
Madrid, ES
</I><P>
<DL>
<DT>
<A HREF="DATEABS.HTM;1#03a_1"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/03A_1.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Using SAT for Combinational Equivalence Checking [p. 114]
<DD><I>
E. Goldberg, M. Prasad, and R. Brayton
</I><P>
<DT>
<A HREF="DATEABS.HTM;1#03a_2"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/03A_2.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Combinational Equivalence Checking Using Boolean Satisfiability and Binary
Decision Diagrams [p. 122]
<DD><I>
S. Reda and A. Salem
</I><P>
<DT>
<A HREF="DATEABS.HTM;1#03a_3"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/03A_3.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
An Efficient Learning Procedure for Multiple Implication Checks [p. 127]
<DD><I>
Y. Novikov and E. Goldberg
</I><P>
</DL>
<HR>
<H2>3B: <A HREF="DATEABS.HTM;1#sess3b" NAME="sess3b">
Panel Session : C/C ++ : Progress or Deadlock in SLD Specification?
</A></H2>
<I>
Organizers: D. Gajski, UC Irvine, USA; E. Villar, Cantabria U, ES<BR>
Moderator: E. Villar, Cantabria U, ES<BR>
Panellists: W. Rosenstiel, FZI/Tuebingen U, D; V. Gerousis, Infineon, D; D. Barton, Averstar, USA; J. Plantin, Ericsson, SE; P. Cavalloro, Italtel, IT; D.
Gajski, UC Irvine, USA; G. de Jong, Telelogic, B
</I><P>
<DL>
<DT>
<A HREF="DATEABS.HTM;1#03b_1"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/03B_1.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
C/C ++ : Progress or Deadlock in System-Level Specification [p. 136]
</DL>
<HR>
<H2>3C: <A HREF="DATEABS.HTM;1#sess3c" NAME="sess3c">
Advances in SoC Testing
</A></H2>
<I>
Moderators: P. Muhmenthaler, Infineon Technologies, D; E.J. Marinissen, Philips Research, NL
</I><P>
<DL>
<DT>
<A HREF="DATEABS.HTM;1#03c_1"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/03C_1.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
An Integrated System-On-Chip Test Framework [p. 138]
<DD><I>
E. Larsson and Z. Peng
</I><P>
<DT>
<A HREF="DATEABS.HTM;1#03c_2"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/03C_2.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Efficient Test Data Compression and Decompression for System-on-a-Chip Using
Internal Scan Chains and Golomb Coding [p. 145]
<DD><I>
A. Chandra and K. Chakrabarty
</I><P>
<DT>
<A HREF="DATEABS.HTM;1#03c_3"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/03C_3.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Testing TAPed Cores and Wrapped Cores with the Same Test Access Mechanism
[p. 150]
<DD><I>
M. Benabdenbi, W. Maroufi, and M. Marzouki
</I><P>
<DT>
<A HREF="DATEABS.HTM;1#03c_4"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/03C_4.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
On Applying the Set Covering Model to Reseeding [p. 156]
<DD><I>
S. Chiusano, S. Di Carlo, P. Prinetto, and H. Wunderlich
</I><P>
</DL>
<HR>
<H2>3E: <A HREF="DATEABS.HTM;1#sess3e" NAME="sess3e">
Panel Session: Data Management: Limiter or Accelerator for Electronic
Design Creativity?
</A></H2>
<I>
Organizer: P. van Staa, Robert Bosch GmbH, D<BR>
Moderator: H. Heidbrink, Descon GmbH, D<BR>
Panellists: B. Potock, Mentor Graphics Corp, USA; J. Mueller, Rosemann
&Lauridsen GmbH, D; U. Ahle, Siemens Business Services, D; C. Basille,
Aerospatiale Matra Missiles, F; W. Kisselmann, Infineon Technologies, D;
W. Herden, Robert Bosch GmbH, D
</I><P>
<DL>
<DT>
<A HREF="DATEABS.HTM;1#03e_1"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/03E_1.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Data Management - Limiter or Accelerator for Electronic Design Creativity
[p. 162]
</DL>
<HR>
<H2>4A: <A HREF="DATEABS.HTM;1#sess4a" NAME="sess4a">
Analysis of Communication Systems
</A></H2>
<I>
Moderators: H. Gräb, TU Munich, D; J. Eckmüller, Infineon
Technologies, D
</I><P>
<DL>
<DT>
<A HREF="DATEABS.HTM;1#04a_1"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/04A_1.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Efficient Bit-Error-Rate Estimation of Multicarrier Transceivers [p. 164]
<DD><I>
G. Vandersteen, P. Wambacq, Y. Rolain, J. Schoukens, S. Donnay,
M. Engels, I. Bolsens
</I><P>
<DT>
<A HREF="DATEABS.HTM;1#04a_2"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/04A_2.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Efficient Time -Domain Simulation of Telecom Frontends Using a Complex Damped
Exponential Signal Model [p. 169]
<DD><I>
P. Vanassche, G. Gielen, and W. Sansen
</I><P>
<DT>
<A HREF="DATEABS.HTM;1#04a_3"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/04A_3.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Simulation Method to Extract Characteristics for Digital Wireless Communication Systems [p. 176]
<DD><I>
L. Nguyen and V. Janicot
</I><P>
</DL>
<HR>
<H2>4B: <A HREF="DATEABS.HTM;1#sess4b" NAME="sess4b">
Design of Low Power Systems I
</A></H2>
<I>
Moderators: G. Stamoulis, Intel, USA; K. Roy, Purdue U, USA
</I><P>
<DL>
<DT>
<A HREF="DATEABS.HTM;1#04b_1"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/04B_1.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Microprocessor Power Analysis by Labeled Simulation [p. 182]
<DD><I>
C. Hsieh, L. Chen, and M. Pedram
</I><P>
<DT>
<A HREF="DATEABS.HTM;1#04b_2"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/04B_2.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Power Aware Microarchitecture Resource Scaling [p. 190]
<DD><I>
A. Iyer and D. Marculescu
</I><P>
<DT>
<A HREF="DATEABS.HTM;1#04b_3"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/04B_3.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Extending Lifetime of Portable Systems by Battery Scheduling [p. 197]
<DD><I>
L. Benini, G. Castelli, A. Macii, E. Macii, M. Poncino, and R. Scarsi
</I><P>
</DL>
<HR>
<H2>4C: <A HREF="DATEABS.HTM;1#sess4c" NAME="sess4c">
Test Generation and Evaluation
</A></H2>
<I>
Moderators: R. Galivanche, Intel, USA; B. Straube, FhG IIS/EAS Dresden, D
</I><P>
<DL>
<DT>
<A HREF="DATEABS.HTM;1#04c_1"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/04C_1.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Efficient Spectral Techniques for Sequential ATPG [p. 204]
<DD><I>
A. Giani, S. Sheng, M. Hsiao, and V. Agrawal
</I><P>
<DT>
<A HREF="DATEABS.HTM;1#04c_2"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/04C_2.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
On the Test of Microprocessor IP Cores [p. 209]
<DD><I>
F. Corno, M. Sonza Reorda, S. Squillero, and M. Violante
</I><P>
<DT>
<A HREF="DATEABS.HTM;1#04c_3"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/04C_3.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Sequence Reordering to Improve the Levels of Compaction Achievable by Static
Compaction Procedures [p. 214]
<DD><I>
I. Pomeranz and S. Reddy
</I><P>
<DT>
<A HREF="DATEABS.HTM;1#04c_4"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/04C_4.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
SEU Effect Analysis in an Open-Source Router via a Distributed Fault Injection
Environment [p. 219]
<DD><I>
A. Benso, S. Di Carlo, G. Di Natale, and P. Prinetto
</I><P>
</DL>
<HR>
<H2>4E: <A HREF="DATEABS.HTM;1#sess4e" NAME="sess4e">
Panel Session: The Programmable Platform: Does One Size Fit All?
</A></H2>
<I>
Organizer: A. Lock, Synopsys, USA<BR>
Moderator: R. Camposano, Synopsys, USA<BR>
Panellists: R. Camposano, Synopsys, USA; A. Cuomo, STMicrolectronics, IT;
R. Subramanian, MorphICs., USA; H. Meyr, TU Aachen, D
</I><P>
<DL>
<DT>
<A HREF="DATEABS.HTM;1#04e_1"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/04E_1.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
The Programmable Platform: Does One Size Fit All? [p. 226]
</DL>
<HR>
<H2>4F: <A HREF="DATEABS.HTM;1#sess4f" NAME="sess4f">
Planning Support
</A></H2>
<I>
Moderators: F. Johannes, TU Munich, D; R. Otten, TU Delft, NL
</I><P>
<DL>
<DT>
<A HREF="DATEABS.HTM;1#04f_1"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/04F_1.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Slicing Tree is a Complete Floorplan Representation [p. 228]
<DD><I>
M. Lai and D. Wong
</I><P>
<DT>
<A HREF="DATEABS.HTM;1#04f_2"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/04F_2.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Further Improve Circuit Partitioning Using GBAW Logic Perturbation Techniques
[p. 233]
<DD><I>
C. Cheung, Y. Wu, and D. Cheng
</I><P>
<DT>
<A HREF="DATEABS.HTM;1#04f_3"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/04F_3.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Clustering Based Fast Clock Scheduling for Light Clock-Tree [p. 240]
<DD><I>
M. Saitoh, M. Azuma, and A. Takahashi
</I><P>
</DL>
<HR>
<H2>5A: <A HREF="DATEABS.HTM;1#sess5a" NAME="sess5a">
Low-Power Channel Decoding and VLIW Architectures
</A></H2>
<I>
Moderators: N. Wehn, Kaiserslautern U, D; M. Bolle, Systemonic, D
</I><P>
<DL>
<DT>
<A HREF="DATEABS.HTM;1#05a_1"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/05A_1.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Power-Efficient Layered Turbo Decoder Processor [p. 246]
<DD><I>
J. Dielissen, J. van Meerbergen, M. Bekooij, F. Harmsze,
S. Sawitzki, J. Huisken, and A. van der Werf
</I><P>
<DT>
<A HREF="DATEABS.HTM;1#05a_2"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/05A_2.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Exploiting Data Forwarding to Reduce the Power Budget of VLIW Embedded Processors [p. 252]
<DD><I>
M. Sami, D. Sciuto, C. Silvano, V. Zaccaria, and R. Zafalon
</I><P>
<DT>
<A HREF="DATEABS.HTM;1#05a_3"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/05A_3.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Design of Low-Power High-Speed Maximum a Priori Decoder Architectures [p. 258]
<DD><I>
A. Worm, H. Lamm, and N. Wehn
</I><P>
</DL>
<HR>
<H2>5B: <A HREF="DATEABS.HTM;1#sess5b" NAME="sess5b">
Design of Low-Power Systems II
</A></H2>
<I>
Moderators: E. Macii, Politecnico di Torino, IT; D. Marculescu, Carnegie
Mellon U, USA
</I><P>
<DL>
<DT>
<A HREF="DATEABS.HTM;1#05b_1"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/05B_1.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Low Complexity FIR Filters Using Factorization of Perturbed Coefficients
[p. 268]
<DD><I>
C. Neau, K. Muhammad, and K. Roy
</I><P>
<DT>
<A HREF="DATEABS.HTM;1#05b_2"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/05B_2.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
An Adaptive Algorithm for Low-Power Streaming Multimedia Processing [p. 273]
<DD><I>
A. Acquaviva, L. Benini, and B. Riccó
</I><P>
<DT>
<A HREF="DATEABS.HTM;1#05b_3"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/05B_3.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
A Static Power Estimation Methodology for IP-Based Design [p. 280]
<DD><I>
X. Liu and C. Papaefthymiou
</I><P>
</DL>
<HR>
<H2>5C: <A HREF="DATEABS.HTM;1#sess5c" NAME="sess5c">
On-Line Testing Techniques
</A></H2>
<I>
Moderators: C. Metra, DEIS-Bologna U, IT; R. Leveugle, TIMA, Grenoble, F
</I><P>
<DL>
<DT>
<A HREF="DATEABS.HTM;1#05c_1"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/05C_1.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Optimization of Error Detecting Codes for the Detection of Crosstalk Originated Errors [p. 290]
<DD><I>
M. Favalli and C. Metra
</I><P>
<DT>
<A HREF="DATEABS.HTM;1#05c_2"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/05C_2.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
System Safety through Automatic High-Level Code Transformations: An Experimental Evaluation [p. 297]
<DD><I>
P. Cheynet, B. Nicolescu, R. Velazco, M. Rebaudengo, M. Sonza Reorda,
and M. Violante
</I><P>
<DT>
<A HREF="DATEABS.HTM;1#05c_3"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/05C_3.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
From DFT to Systems Test - A Model Based Cost Optimization Tool [p. 302]
<DD><I>
M. Wahl, T. Ambler, C. Maaß and M. Rahman
</I><P>
<DT>
<A HREF="DATEABS.HTM;1#05c_4"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/05C_4.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Efficient On-Line Testing Method for a Floating-Point Adder [p. 307]
<DD><I>
A. Drozd and M. Lobachev
</I><P>
</DL>
<HR>
<H2>5E: <A HREF="DATEABS.HTM;1#sess5e" NAME="sess5e">
Design Methodology for PicoRadio Networks
</A></H2>
<I>
Organizer: J. Rabaey, UC Berkeley, USA<BR>
Moderator: M. Engels, IMEC, B
</I><P>
<DL>
<DT>
<A HREF="DATEABS.HTM;1#05e_1"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/05E_1.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Design Methodology for PicoRadio Networks [p. 314]
<DD><I>
J. da Silva Jr., J. Shamberger, M. Ammer, C. Guo, S. Li,
R. Shah, T. Tuan, M. Sheets, J. Rabaey,
B. Nikolic, A. Sangiovanni-Vincentelli, and P. Wright
</I><P>
</DL>
<HR>
<H2>5F: <A HREF="DATEABS.HTM;1#sess5f" NAME="sess5f">
EMC on Chip and High Density Package Level
</A></H2>
<I>
Moderators: W. John, Fraunhofer Institute Berlin/Paderborn, D;
F. Sabath, Armed Forces Institute for Protection Technologies, USA
</I><P>
<DL>
<DT>
<A HREF="DATEABS.HTM;1#05f_1"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/05F_1.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
High-Level Simulation of Substrate Noise Generation from
Large Digital Circuits with Multiple Supplies [p. 326]
<DD><I>
M. Badaroglu, M. van Heijningen, V. Gravot, S. Donnay, H. De Man, G. Gielen
M. Engels, and I. Bolsens
</I><P>
<DT>
<A HREF="DATEABS.HTM;1#05f_2"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/05F_2.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Crosstalk Noise in Future Digital CMOS Circuits [p. 331]
<DD><I>
C. Werner, R. Göttsche, A. Wörner, and U. Ramacher
</I><P>
<DT>
<A HREF="DATEABS.HTM;1#05f_3"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/05F_3.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Modeling Electromagnetic Emission of Integrated Circuits for System Analysis [p. 336]
<DD><I>
P. Kralicek, W. John, and H. Garbe
</I><P>
<DT>
<A HREF="DATEABS.HTM;1#05f_4"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/05F_4.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Analysis of EME Produced by a Microcontroller Operation [p. 341]
<DD><I>
F. Fiori and F. Musolino
</I><P>
</DL>
<HR>
<H2>6A: <A HREF="DATEABS.HTM;1#sess6a" NAME="sess6a">
Design Methods for Analog and Mixed Signal Circuits
</A></H2>
<I>
Moderators: A. Kaiser, IEMN-ISEN, F; P. Wambacq, IMEC, B
</I><P>
<DL>
<DT>
<A HREF="DATEABS.HTM;1#06a_1"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/06A_1.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Top-Down Design of a xDSL 14-bit 4MS/s Sigma-Delta Modulator in Digital CMOS Technology [p. 348]
<DD><I>
R. del Río, J. de la Rosa, F. Medeiro, B. Pérez-Verdú, and A.
Rodríguez-Vázquez
</I><P>
<DT>
<A HREF="DATEABS.HTM;1#06a_2"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/06A_2.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Analog Design for Reuse - Case Study: Very Low-Voltage Sigma-Delta Modulator [p. 353]
<DD><I>
M. Dessouky, A. Kaiser, M. Louërat, and A. Greiner
</I><P>
<DT>
<A HREF="DATEABS.HTM;1#06a_3"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/06A_3.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
A Design Strategy for Low-Voltage Low-Power Continuous-Time
Sigma-Delta A/D Converters [p. 361]
<DD><I>
F. Gerfers and Y. Manoli
</I><P>
</DL>
<HR>
<H2>6B: <A HREF="DATEABS.HTM;1#sess6b" NAME="sess6b">
Issues in Synthesis and Power Optimization
</A></H2>
<I>
Moderators: R. Murgai, Fujitsu Labs of America, USA; S. Minato, NTT, JP
</I><P>
<DL>
<DT>
<A HREF="DATEABS.HTM;1#06b_1"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/06B_1.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Minimizing Stand-By Leakage Power in Static CMOS Circuits [p. 370]
<DD><I>
S. Naidu and E. Jacobs
</I><P>
<DT>
<A HREF="DATEABS.HTM;1#06b_2"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/06B_2.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
In-Place Delay Constrained Power Optmization Using Functional Symmetries
[p. 377]
<DD><I>
C. Chang, B. Hu, and M. Marek-Sadowska
</I><P>
<DT>
<A HREF="DATEABS.HTM;1#06b_3"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/06B_3.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
High-Quality Sub-Function Construction in Functional Decomposition Based on
Information Relationship Measures [p. 383]
<DD><I>
L. Józwiak and A. Chojnacki
</I><P>
<DT>
<A HREF="DATEABS.HTM;1#06b_4"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/06B_4.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Generalized Reasoning Scheme for Redundancy Addition and Removal Logic Optimization [p. 391]
<DD><I>
J. Espejo, L. Entrena, E. San Millán, and E. Olías
</I><P>
</DL>
<HR>
<H2>6C: <A HREF="DATEABS.HTM;1#sess6c" NAME="sess6c">
High Level Validation
</A></H2>
<I>
Moderators: J. Teixeira, IST/INESC, PT; M. Sonza Reorda, Politecnico di Torino, IT
</I><P>
<DL>
<DT>
<A HREF="DATEABS.HTM;1#06c_1"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/06C_1.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
LPSAT: A Unified Approach to RTL Satisfiability [p. 398]
<DD><I>
Z. Zeng, P. Kalla, and M. Ciesielski
</I><P>
<DT>
<A HREF="DATEABS.HTM;1#06c_2"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/06C_2.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Functional Test Generation for Behaviorally Sequential Models [p. 403]
<DD><I>
F. Ferrandi, G. Ferrara, D. Sciuto, A. Fin, and F. Fummi
</I><P>
<DT>
<A HREF="DATEABS.HTM;1#06c_3"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/06C_3.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
High Quality Behavioral Verification Using Statistical Stopping Criteria [p. 411]
<DD><I>
A. Hajjar, T. Chen, I. Munn, A. Andrews, and M. Bjorkman
</I><P>
</DL>
<HR>
<H2>6E: <A HREF="DATEABS.HTM;1#sess6e" NAME="sess6e">
Hot Topic: Network Processors: A Perspective on Market Requirements,
Processor Architectures and Embedded S/W Tools
</A></H2>
<I>
Organizers: P. Bromley, F. Karim, and P. Paulin, STMicroelectronics, F<BR>
Moderator: P. Paulin, STMicroelectronics, F
</I><P>
<DL>
<DT>
<A HREF="DATEABS.HTM;1#06e_1"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/06E_1.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Network Processors: A Perspective on Market Requirements,
Processor Architectures and Embedded S/W Tools [p. 420]
<DD><I>
P. Paulin, F. Karim, and P. Bromley
</I><P>
</DL>
<HR>
<H2>6F: <A HREF="DATEABS.HTM;1#sess6f" NAME="sess6f">
Interconnect Extraction and Modelling
</A></H2>
<I>
Moderators: L. Silveira, IST/INESC, PT; H. Grabinski, Hannover U, D
</I><P>
<DL>
<DT>
<A HREF="DATEABS.HTM;1#06f_1"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/06F_1.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Efficient Inductance Extraction via Windowing [p. 430]
<DD><I>
M. Beattie and L. Pileggi
</I><P>
<DT>
<A HREF="DATEABS.HTM;1#06f_2"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/06F_2.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Efficient and Passive Modeling of Transmission Lines by Using Differential Quadrature Method [p. 437]
<DD><I>
Q. Xu and P. Mazumder
</I><P>
<DT>
<A HREF="DATEABS.HTM;1#06f_3"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/06F_3.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Explicit Formulas and Efficient Algorithm for Moment Computation of Coupled RC
Trees with Lumped and Distributed Elements [p. 445]
<DD><I>
Q. Yu and E. Kuh
</I><P>
<DT>
<A HREF="DATEABS.HTM;1#06f_4"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/06F_4.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
On the Impact of On-Chip Inductance on Signal Nets under the Influence of Power Grid Noise [p. 451]
<DD><I>
T. Chen
</I><P>
</DL>
<HR>
<H2>7A: <A HREF="DATEABS.HTM;1#sess7a" NAME="sess7a">
Timing and Parallel Simulation
</A></H2>
<I>
Moderators: S. Yoo, TIMA, Grenoble, F; F. Wagner, UFRGS, BRZ
</I><P>
<DL>
<DT>
<A HREF="DATEABS.HTM;1#07a_1"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/07A_1.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Timing Simulation of Digital Circuits with Binary Decision Diagrams [p. 460]
<DD><I>
R. Ubar, A. Jutman, and Z. Peng
</I><P>
<DT>
<A HREF="DATEABS.HTM;1#07a_2"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/07A_2.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
HALOTIS: High Accuracy LOgic TIming Simulator with Inertial and Degradation
Delay Model [p. 467]
<DD><I>
P. Vazquez, J. Juan-Chico, M. Bellido, A. Acosta, and M. Valencia
</I><P>
<DT>
<A HREF="DATEABS.HTM;1#07a_3"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/07A_3.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
dlbSIM - A Parallel Functional Logic Simulator Allowing Dynamic Load Balancing [p. 472]
<DD><I>
K. Hering, J. Löser, and J. Markwardt
</I><P>
<DT>
<A HREF="DATEABS.HTM;1#07a_4"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/07A_4.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Architecture Driven Partitioning [p. 479]
<DD><I>
J. Küter and E. Barke
</I><P>
</DL>
<HR>
<H2>7B: <A HREF="DATEABS.HTM;1#sess7b" NAME="sess7b">
Embedded Tutorial: Low-Power Issues for SOCs
</A></H2>
<I>
Moderator: C. Piguet, CSEM, Neuchatel, CH
</I><P>
<DL>
<DT>
<A HREF="DATEABS.HTM;1#07b_1"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/07B_1.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Low-Power Systems on Chips (SOCs) [p. 488]
<DD><I>
C. Piguet, M. Renaudin, and T. Omnès
</I><P>
</DL>
<HR>
<H2>7C: <A HREF="DATEABS.HTM;1#sess7c" NAME="sess7c">
Defect Oriented Testing
</A></H2>
<I>
Moderators: H. Kerkhoff, Twente U, NL; J. Pineda de Gyvez, Philips Research, NL
</I><P>
<DL>
<DT>
<A HREF="DATEABS.HTM;1#07c_1"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/07C_1.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Static and Dynamic Behavior of Memory Cell Array Opens and Shorts in Embedded
DRAMs [p. 496]
<DD><I>
Z. Al-Ars and A. van de Goor
</I><P>
<DT>
<A HREF="DATEABS.HTM;1#07c_2"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/07C_2.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Definitions of the Numbers of Detections of Target Faults and their
Effectiveness in Guiding Test Generation for High Defect Coverage [p. 504]
<DD><I>
I. Pomeranz and S. Reddy
</I><P>
<DT>
<A HREF="DATEABS.HTM;1#07c_3"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/07C_3.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
CMOS Open Defect Detection by Supply Current Test [p. 509]
<DD><I>
M. Hashizume, M. Ichimiya, H. Yotsuyanagi, and T. Tamesada
</I><P>
<DT>
<A HREF="DATEABS.HTM;1#07c_4"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/07C_4.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Full Chip False Timing Path Identification: Applications to the
PowerPC<SUP>TM</SUP> Microprocessors [p. 514]
<DD><I>
J. Zeng, M. Abadir, J. Bhadra, and J. Abraham
</I><P>
</DL>
<HR>
<H2>7E: <A HREF="DATEABS.HTM;1#sess7e" NAME="sess7e">
Embedded Tutorial: CAD for RF Integrated Circuits and Systems
</A></H2>
<I>
Moderator: P. Wambacq, IMEC, B
</I><P>
<DL>
<DT>
<A HREF="DATEABS.HTM;1#07e_1"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/07E_1.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
CAD for RF Circuits [p. 520]
<DD><I>
P. Wambacq, G. Vandersteen, J. Phillips, J. Roychowdhury, W. Eberle, B. Yang,
D. Long, and A. Demir
</I><P>
</DL>
<HR>
<H2>7F: <A HREF="DATEABS.HTM;1#sess7f" NAME="sess7f">
Routing Enhancements
</A></H2>
<I>
Moderators: J. Lienig, Robert Bosch GmbH, D; A. Takahashi, Tokyo IT, JP
</I><P>
<DL>
<DT>
<A HREF="DATEABS.HTM;1#07f_1"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/07F_1.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Modeling Crosstalk Noise for Deep Submicron Verification Tools [p. 530]
<DD><I>
P. Bazargan-Sabet and F. Ilponse
</I><P>
<DT>
<A HREF="DATEABS.HTM;1#07f_2"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/07F_2.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
A Graph Based Algorithm for Optimal Buffer Insertion under Accurate Delay Models [p. 535]
<DD><I>
Y. Gao and D. Wong
</I><P>
<DT>
<A HREF="DATEABS.HTM;1#07f_3"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/07F_3.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Repeater Block Planning under Simultaneous Delay and Transition Time Constraints [p. 540]
<DD><I>
P. Sarkar and C. Koh
</I><P>
</DL>
<HR>
<H2>8A: <A HREF="DATEABS.HTM;1#sess8a" NAME="sess8a">
Layout Generation
</A></H2>
<I>
Moderators: V. Meyer zu Bexten, Atmel Germany GmbH, D; E. Barke, Hannover U, D
</I><P>
<DL>
<DT>
<A HREF="DATEABS.HTM;1#08a_1"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/08A_1.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
On-The-Fly Layout Generation for PTL Macrocells [p. 546]
<DD><I>
L. Macchiarulo, L. Benini, and E. Macii
</I><P>
<DT>
<A HREF="DATEABS.HTM;1#08a_2"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/08A_2.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Automatic Datapath Tile Placement and Routing [p. 552]
<DD><I>
T. Serdar and C. Sechen
</I><P>
<DT>
<A HREF="DATEABS.HTM;1#08a_3"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/08A_3.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
A Boolean Satisfiability-Based Incremental Rerouting Approach with Application
to FPGAs [p. 560]
<DD><I>
G. Nam, K. Sakallah, and R. Rutenbar
</I><P>
</DL>
<HR>
<H2>8B: <A HREF="DATEABS.HTM;1#sess8b" NAME="sess8b">
Modelling and Performance Analysis of Embedded Systems
</A></H2>
<I>
Moderators: J. Plantin, Ericsson Radio Systems, SE; L. Lavagno, Udine U, IT
</I><P>
<DL>
<DT>
<A HREF="DATEABS.HTM;1#08b_1"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/08B_1.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Dual Transitions Petri Net Based Modelling Technique for Embedded Systems
Specification [p. 566]
<DD><I>
M. Varea and B. Al-Hashimi
</I><P>
<DT>
<A HREF="DATEABS.HTM;1#08b_2"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/08B_2.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Probabilistic Application Modeling for System-Level Performance Analysis
[p. 572]
<DD><I>
R. Marculescu and A. Nandi
</I><P>
<DT>
<A HREF="DATEABS.HTM;1#08b_3"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/08B_3.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Reliable Estimation of Execution Time of Embedded Software [p. 580]
<DD><I>
P. Giusto, G. Martin, and E. Harcourt
</I><P>
</DL>
<HR>
<H2>8C: <A HREF="DATEABS.HTM;1#sess8c" NAME="sess8c">
Analog and Mixed Signal Testing
</A></H2>
<I>
Moderators: M. Renovell, LIRMM, F; B. Kruseman, Philips Research, NL
</I><P>
<DL>
<DT>
<A HREF="DATEABS.HTM;1#08c_1"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/08C_1.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Implementation of a Linear Histogram BIST for ADCs [p. 590]
<DD><I>
F. Azaïs, S. Bernard, Y. Bertrand, and M. Renovell
</I><P>
<DT>
<A HREF="DATEABS.HTM;1#08c_2"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/08C_2.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Test Generation Based Diagnosis of Device Parameters for Analog Circuits [p. 596]
<DD><I>
S. Cherubal and A. Chatterjee
</I><P>
<DT>
<A HREF="DATEABS.HTM;1#08c_3"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/08C_3.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Generation of Optimum Test Stimuli for Nonlinear Analog Circuits Using
Nonlinear Programming and Time -Domain Sensitivities [p. 603]
<DD><I>
B. Burdiek
</I><P>
</DL>
<HR>
<H2>8E: <A HREF="DATEABS.HTM;1#sess8e" NAME="sess8e">
Panel Session: Managing the SoC Design Challenge with 'Soft' Hardware
</A></H2>
<I>
Organizer: D. Davis, Actel, USA<BR>
Moderator: R. Wilson, EETimes, USA<BR>
Panellists: T. Kambe, Sharp, JP; B. Gupta, STmicroelectronics, USA;
C. Balough, Triscend, USA; Y. Tanurhan, Actel, USA
</I><P>
<DL>
<DT>
<A HREF="DATEABS.HTM;1#08e_1"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/08E_1.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Managing the SoC Design Challenge with "Soft" Hardware [p. 610]
<DD><I>
R. Wilson
</I><P>
</DL>
<HR>
<H2>8F: <A HREF="DATEABS.HTM;1#sess8f" NAME="sess8f">
Hardware-Software Architectures and Synthesis
</A></H2>
<I>
Moderators: J. Henkel, NEC, USA; R. Leupers, Dortmund U, D
</I><P>
<DL>
<DT>
<A HREF="DATEABS.HTM;1#08f_1"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/08F_1.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Integrated Hardware-Software Co-Synthesis and High-Level Synthesis for Design i
of Embedded Systems under Power and Latency Constraints [p. 612]
<DD><I>
A. Doboli
</I><P>
<DT>
<A HREF="DATEABS.HTM;1#08f_2"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/08F_2.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Allocation and Scheduling of Conditional Task Graph in Hardware/Software
Co-Synthesis [p. 620]
<DD><I>
Y. Xie and W. Wolf
</I><P>
<DT>
<A HREF="DATEABS.HTM;1#08f_3"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/08F_3.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Code Placement in Hardware Software Co -Synthesis to Improve Performance and
Reduce Cost [p. 626]
<DD><I>
S. Parameswaran
</I><P>
<DT>
<A HREF="DATEABS.HTM;1#08f_4"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/08F_4.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
System-On-A-Chip Processor Synchronization Support in Hardware [p. 633]
<DD><I>
B. Saglam and V. Mooney III
</I><P>
</DL>
<HR>
<H2>9A: <A HREF="DATEABS.HTM;1#sess9a" NAME="sess9a">
Reconfigurable Computing I
</A></H2>
<I>
Moderators: K. Buchenrieder, Infineon Technologies, D; H. Grünbaecher,
Carinthia Tech. Inst., Villach, A
</I><P>
<DL>
<DT>
<A HREF="DATEABS.HTM;1#09a_1"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/09A_1.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
A Decade of Reconfigurable Computing: A Visionary Retrospective [p. 642]
<DD><I>
R. Hartenstein
</I><P>
<DT>
<A HREF="DATEABS.HTM;1#09a_2"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/09A_2.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Hierarchical Memory Mapping during Synthesis in FPGA -Based Reconfigurable
Computers [p. 650]
<DD><I>
I. Ouaiss and R. Vemuri
</I><P>
<DT>
<A HREF="DATEABS.HTM;1#09a_3"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/09A_3.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Optimal FPGA Module Placement with Temporal Precedence Constraints [p. 658]
<DD><I>
S. Fekete, E. Köhler, and J. Teich
</I><P>
</DL>
<HR>
<H2>9B: <A HREF="DATEABS.HTM;1#sess9b" NAME="sess9b">
Embedded Software
</A></H2>
<I>
Moderators: P. Marwedel, Dortmund U, D; Z. Peng, Linkoping U, SE
</I><P>
<DL>
<DT>
<A HREF="DATEABS.HTM;1#09b_1"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/09B_1.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Generation of Minimal Size Code for Schedule Graphs [p. 668]
<DD><I>
C. Passerone, Y. Watanabe, and L. Lavagno
</I><P>
<DT>
<A HREF="DATEABS.HTM;1#09b_2"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/09B_2.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Generating Production Quality Software Development Tools Using a Machine
Description Language [p. 674]
<DD><I>
A. Hoffmann, A. Nohl, S. Pees, G. Braun, and H. Meyr
</I><P>
<DT>
<A HREF="DATEABS.HTM;1#09b_3"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/09B_3.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Automatic Generation and Targeting of Application Specific Operating Systems
and Embedded Systems Software [p. 679]
<DD><I>
L. Gauthier, S. Yoo, and A. Jerraya
</I><P>
<DT>
<A HREF="DATEABS.HTM;1#09b_4"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/09B_4.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Cache Conscious Data Layout Organization for Embedded Multimedia Applications
[p. 686]
<DD><I>
C. Kulkarni, C. Ghez, M. Miranda, F. Catthoor, and H. De Man
</I><P>
</DL>
<HR>
<H2>9C: <A HREF="DATEABS.HTM;1#sess9c" NAME="sess9c">
Panel Session: Design Challenges and Emerging EDA Solutions in
Mixed-Signal IC Design
</A></H2>
<I>
Organizer and Moderator: G. Gielen, KU Leuven, B<BR>
Panellists: B. Sorensen, Atrium Design Solutions; H. Casier, Alcatel Microelectronics, B;
P. Magarshack, STMicroelectronics, F; J. Rodriguez, Anacad; J. Pollet, Dolphin, F
</I><P>
<DL>
<DT>
<A HREF="DATEABS.HTM;1#09c_1"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/09C_1.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Design Challenges and Emerging EDA Solutions in Mixed-Signal IC Design [p. 694]
</DL>
<HR>
<H2>9E: <A HREF="DATEABS.HTM;1#sess9e" NAME="sess9e">
Hot Topic : Game Processors
</A></H2>
<I>
Organizers/Moderators: W. Rosenstiel, FZI/Tübingen U, D; Y. Nakamura,
Kyoto U, JP<BR>
Speakers: H. Tago, System LSI R&D Center, Toshiba Semiconductor Company;<BR>
A. Mandapati, ATI Research Inc (Subsidiary of Nintendo in the US);<BR>
S. Narita, Advanced Microcomputer Business Operation, System LSI Business Division, Hitachi Ltd.
</I><P>
<DL>
<DT>
<A HREF="DATEABS.HTM;1#09e_1"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/09E_1.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
CPU for PlayStation®2 [p. 696]
<DD><I>
H. Tago, K. Hashimoto, N. Ikumi, M. Nagamatsu, M. Suzuoki, and Y. Yamamoto
</I><P>
<DT>
<A HREF="DATEABS.HTM;1#09e_2"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/09E_2.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Implementation of the ATI Flipper Chip [p. 697]
<DD><I>
A. Mandapati
</I><P>
<DT>
<A HREF="DATEABS.HTM;1#09e_3"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/09E_3.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
SH-4 RISC Microprocessor for Multimedia, Game Machine [p. 699]
<DD><I>
S. Narita
</I><P>
</DL>
<HR>
<H2>9F: <A HREF="DATEABS.HTM;1#sess9f" NAME="sess9f">
Decision Diagrams
</A></H2>
<I>
Moderators: A. Oliveira, IST/INESC, PT; E. Macii, Politecnico di Torino, IT
</I><P>
<DL>
<DT>
<A HREF="DATEABS.HTM;1#09f_1"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/09F_1.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Streaming BDD Manipulation for Large-Scale Combinatorial Problems [p. 702]
<DD><I>
S. Minato and S. Ishihara
</I><P>
<DT>
<A HREF="DATEABS.HTM;1#09f_2"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/09F_2.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Binary Decision Diagram with Minimum Expected Path Length [p. 708]
<DD><I>
Y. Liu, K. Wang, T. Hwang, and C. Liu
</I><P>
<DT>
<A HREF="DATEABS.HTM;1#09f_3"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/09F_3.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Spectral Decision Diagrams Using Graph Transformations [p. 713]
<DD><I>
M. Thornton and R. Drechsler
</I><P>
</DL>
<HR>
<H2>9L: <A HREF="DATEABS.HTM;1#sess9l" NAME="sess9l">
Friday Keynote Session: Electronic System Design Methodology:
Europe's Positioning
</A></H2>
<I>
Moderator: A. Jerraya, TIMA, Grenoble, F<BR>
Speaker: G. Matheron, MEDEA Office Director, Paris, F
</I><P>
<DL>
<DT>
<A HREF="DATEABS.HTM;1#09l_1"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/09L_1.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Electronic System Design Methodology: Europe's Positioning [p. 720]
</DL>
<HR>
<H2>10A: <A HREF="DATEABS.HTM;1#sess10a" NAME="sess10a">
Reconfigurable Computing II
</A></H2>
<I>
Moderators: R. Lauwereins, KU Leuven, B; R. Hartenstein, Kaiserslautern U, D
</I><P>
<DT>
<A HREF="DATEABS.HTM;1#10a_1"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/10A_1.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Precision and Error Analysis of MATLAB Applications during Automated
Hardware Synthesis for FPGAs [p. 722]
<DD><I>
A. Nayak, M. Haldar, A. Choudhary, and P. Banerjee
</I><P>
<DT>
<A HREF="DATEABS.HTM;1#10a_2"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/10A_2.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
A HW/SW Partitioning Algorithm for Dynamically Reconfigurable Architectures [p. 729]
<DD><I>
J. Noguera and R. Badia
</I><P>
<DT>
<A HREF="DATEABS.HTM;1#10a_3"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/10A_3.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Managing Dynamic Reconfiguration Overhead in Systems -On-A-Chip Design Using
Reconfigurable Datapaths and Optimized Interconnection Networks [p. 735]
<DD><I>
Z. Huang and S. Malik
</I><P>
</DL>
<HR>
<H2>10B: <A HREF="DATEABS.HTM;1#sess10b" NAME="sess10b">
Co-Simulation and System Verification Techniques
</A></H2>
<I>
Moderators: P. Schwarz, FhG IIS/EAS Dresden, D; M. Rencz, TU Budapest, H
</I><P>
<DL>
<DT>
<A HREF="DATEABS.HTM;1#10b_1"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/10B_1.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Simulation-Guided Property Checking Based on a Multi-Valued AR-Automata [p. 742]
<DD><I>
J. Ruf, D. Hoffmann, T. Kropf, and W. Rosenstiel
</I><P>
<DT>
<A HREF="DATEABS.HTM;1#10b_2"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/10B_2.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Performance Improvement of Multi-Processor Systems Cosimulation
Based on SW Analysis [p. 749]
<DD><I>
J. Jung, S. Yoo and K. Choi
</I><P>
<DT>
<A HREF="DATEABS.HTM;1#10b_3"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/10B_3.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Mixed-Level Cosimulation for Fine Gradual Refinement of Communication in SoC
Design [p. 754]
<DD><I>
G. Nicolescu, S. Yoo, and A. Jerraya
</I><P>
<DT>
<A HREF="DATEABS.HTM;1#10b_4"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/10B_4.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
A Framework for Fast Hardware-Software Co-Simulation [p. 760]
<DD><I>
A. Hoffmann, T. Kogel, and H. Meyr
</I><P>
</DL>
<HR>
<H2>10C: <A HREF="DATEABS.HTM;1#sess10c" NAME="sess10c">
Embedded Tutorial: Analog Methods and Tools for SoC Integration
</A></H2>
<I>
Moderators: J. Vital, IST, PT; A. Rueda, CNM, Seville U, ES; A. Vasquez, CNM,
Seville U, ES
</I><P>
<DL>
<DT>
<A HREF="DATEABS.HTM;1#10c_1"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/10C_1.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Analog/Mixed-Signal IP Modeling for Design Reuse [p. 766]
<DD><I>
N. Madrid, E. Peralías, A. Acosta, and A. Rueda
</I><P>
<DT>
<A HREF="DATEABS.HTM;1#10c_2"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/10C_2.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
A Skill<SUP>TM</SUP>-Based Library for Retargetable Embedded Analog Cores
[p. 768]
<DD><I>
X. Jingnan, J. Vital, and N. Horta
</I><P>
<DT>
<A HREF="DATEABS.HTM;1#10c_3"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/10C_3.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Modelling SoC Devices for Virtual Test Using VHDL [p. 770]
<DD><I>
M. Rona and G. Krampl
</I><P>
<DT>
<A HREF="DATEABS.HTM;1#10c_4"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/10C_4.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Retargeting of Mixed-Signal Blocks for SoCs [p. 772]
<DD><I>
R. Castro-López, F. Fernández, M. Delgado-Restituto, and A.
Rodríguez-Vázquez
</I><P>
</DL>
<HR>
<H2>10E: <A HREF="DATEABS.HTM;1#sess10e" NAME="sess10e">
Panel Session: Standard Bus vs. Bus Wrapper:
What is the Best Solution for Future SoC Integration?
</A></H2>
<I>
Organizer: C. Yeung, VSI Alliance, USA<BR>
Moderator: P. Clarke, Electronic Engineering Times, UK<BR>
Panellists: A. Haverinen, Nokia, FIN; USA; G. Matthews, STMicroelectronics, F;
J. Morris, ARM, UK, and J. Zaidi, Palmchip Corp., USA
</I><P>
<DL>
<DT>
<A HREF="DATEABS.HTM;1#10e_1"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/10E_1.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Standard Bus vs. Bus Wrapper: What is the Best Solution for Future SoC Integration? [p. 776]
</DL>
<HR>
<H2>10F: <A HREF="DATEABS.HTM;1#sess10f" NAME="sess10f">
Architectural Level Synthesis
</A></H2>
<I>
Moderators: A. Brown, Southampton U, UK; P. Eles, Linkoping U, SE
</I><P>
<DL>
<DT>
<A HREF="DATEABS.HTM;1#10f_1"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/10F_1.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Access Pattern Based Local Memory Customization for Low Power Embedded Systems
[p. 778]
<DD><I>
P. Grun, N. Dutt, and A. Nicolau
</I><P>
<DT>
<A HREF="DATEABS.HTM;1#10f_2"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/10F_2.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Static Memory Allocation by Pointer Analysis and Coloring [p. 785]
<DD><I>
J. Zhu
</I><P>
<DT>
<A HREF="DATEABS.HTM;1#10f_3"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/10F_3.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Heuristic Datapath Allocation for Multiple Wordlength Systems [p. 791]
<DD><I>
G. Constantinides, P. Cheung, and W. Luk
</I><P>
</DL>
<HR>
<H2><A HREF="DATEABS.HTM;1#poster" NAME="poster">
Poster Session:
</A></H2>
<DL>
<DT>
<A HREF="DATEABS.HTM;1#p01"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/P01.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
On the Verification of Synthesized Designs Using Automatically Generated
Transformational Witnesses [p. 798]
<DD><I>
E. Teica, R. Radhakrishnan, and R. Vemuri
</I><P>
<DT>
<A HREF="DATEABS.HTM;1#p02"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/P02.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Property-Specific Witness Graph Generation for Guided Simulation [p. 799]
<DD><I>
A. Casavant, A. Gupta, S. Liu, A. Mukaiyama, K. Wakabayashi, and P. Ashar
</I><P>
<DT>
<A HREF="DATEABS.HTM;1#p03"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/P03.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Two Approaches for Developing Generic Components in VHDL [p. 800]
<DD><I>
V. Stuikys, G. Ziberkas, R. Damasevicius, and G. Majauskas
</I><P>
<DT>
<A HREF="DATEABS.HTM;1#p04"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/P04.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Annotated Data Types for Addressed Token Passing Networks [p. 801]
<DD><I>
G. Cichon and W. Bunnbauer
</I><P>
<DT>
<A HREF="DATEABS.HTM;1#p05"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/P05.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Testability Trade-Offs for BIST RTL Data Paths: The Case for Three Dimensional
Design Space [p. 802]
<DD><I>
N. Nicolici and B. Al-Hashimi
</I><P>
<DT>
<A HREF="DATEABS.HTM;1#p07"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/P07.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Towards a Better Understanding of Failure Modes and Test Requirements of ADCs
[p. 803]
<DD><I>
A. Lechner, A. Richardson, and B. Hermes
</I><P>
<DT>
<A HREF="DATEABS.HTM;1#p08"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/P08.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Exact Fault Simulation for Systems on Silicon that Protects Each Core's
Intellectual Property (IP) [p. 804]
<DD><I>
M. Quasem and S. Gupta
</I><P>
<DT>
<A HREF="DATEABS.HTM;1#p09"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/P09.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Using Mission Logic for Embedded Testing [p. 805]
<DD><I>
R. Dorsch and H. Wunderlich
</I><P>
<DT>
<A HREF="DATEABS.HTM;1#p10"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/P10.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
A Regularity-Based Hierarchical Symbolic Analysis Method for Large-Scale Analog Networks [p. 806]
<DD><I>
A. Doboli and R. Vemuri
</I><P>
<DT>
<A HREF="DATEABS.HTM;1#p11"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/P11.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
An Improved Hierarchical Classification Algorithm for Structural Analysis of Integrated Circuits [p. 807]
<DD><I>
M. Olbrich, A. Rein, and E. Barke
</I><P>
<DT>
<A HREF="DATEABS.HTM;1#p12"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/P12.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Automatic Nonlinear Memory Power Modelling [p. 808]
<DD><I>
E. Schmidt, G. Jochens, L. Kruse, F. Theeuwen, and W. Nebel
</I><P>
<DT>
<A HREF="DATEABS.HTM;1#p13"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/P13.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
An Operation Rearrangement Technique for Power Optimization in VLIW Instruction Fetch [p. 809]
<DD><I>
D. Shin, J. Kim, and N. Chang
</I><P>
<DT>
<A HREF="DATEABS.HTM;1#p14"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/P14.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
A Pseudo Delay-Insensitive Timing Model to Synthesizing Low-Power Asynchronous Circuits [p. 810]
<DD><I>
O. Garnica, J. Lanchares, and R. Hermida
</I><P>
<DT>
<A HREF="DATEABS.HTM;1#p15"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/P15.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
A Register-Transfer-Level Fault Simulator for Permanent and Transient Faults in
Embedded Processors [p. 811]
<DD><I>
C. Rousselle, M. Pflanz, A. Behling, T. Mohaupt, and H. Vierhaus
</I><P>
<DT>
<A HREF="DATEABS.HTM;1#p16"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/P16.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Efficient Finite Field Digit-Serial Multiplier Architecture for
Cryptography Applications [p. 812]
<DD><I>
G. Bertoni, L. Breveglieri, and P. Fragneto
</I><P>
<DT>
<A HREF="DATEABS.HTM;1#p17"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/P17.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Task Concurrency Management Methodology Summary [p. 813]
<DD><I>
C. Wong, P. Marchal, P. Yang, F. Catthoor, H. De Man,
A. Prayati, N. Cossement, R. Lauwereins, and D. Verkest
</I><P>
<DT>
<A HREF="DATEABS.HTM;1#p18"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/P18.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Susceptibility of Analog Cells to Substrate Interference [p. 814]
<DD><I>
F. Fiori
</I><P>
<DT>
<A HREF="DATEABS.HTM;1#p20"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/P20.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Order Determination for Frequency Compensation of Negative-Feedback Systems [p. 815]
<DD><I>
A. van Staveren and C. Verhoeven
</I><P>
<DT>
<A HREF="DATEABS.HTM;1#p21"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/P21.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Minimizing the Number of Floating Bias Voltage Sources with Integer Linear
Programming [p. 816]
<DD><I>
E. Yildiz, A. van Staveren, and C. Verhoeven
</I><P>
<DT>
<A HREF="DATEABS.HTM;1#p22"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/P22.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
CMOS Sizing Rule for High Performance Long Interconnects [p. 817]
<DD><I>
G. Cappuccino and G. Cocorullo
</I><P>
<DT>
<A HREF="DATEABS.HTM;1#p24"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/P24.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
On Automatic Analysis of Geometrically Proximate Nets in VLSI Layout [p. 818]
<DD><I>
S. Koranne and O. Gangwal
</I><P>
<DT>
<A HREF="DATEABS.HTM;1#p25"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/P25.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
AnalogRouter: A New Approach of Current-Driven Routing for Analog Circuits
[p. 819]
<DD><I>
J. Lienig, G. Jerke, and T. Adler
</I><P>
<DT>
<A HREF="DATEABS.HTM;1#p26"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/P26.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
A Hardware-Software Operating System for Heterogeneous Designs [p. 820]
<DD><I>
J. Moya, F. Moya, and J. López
</I><P>
<DT>
<A HREF="DATEABS.HTM;1#p27"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/P27.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
PRMDL: A Machine Description Language for Clustered VLIW Architectures [p. 821]
<DD><I>
A. Terechko, E. Pol, and J. van Eijndhoven
</I><P>
<DT>
<A HREF="DATEABS.HTM;1#p28"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/P28.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Functional Units with Conditional Input/Output Behavior in VLIW Processors
[p. 822]
<DD><I>
M. Bekooij, L. Engels, A. van der Werf, and N. Busá
</I><P>
<DT>
<A HREF="DATEABS.HTM;1#p29"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/P29.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Adaptation of an Event-Driven Simulation Environment to Sequentially Propagated
Concurrent Fault Simulation [p. 823]
<DD><I>
M. Zolfy, S. Mirkhani, and Z. Navabi
</I><P>
<DT>
<A HREF="DATEABS.HTM;1#p30"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/P30.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Constraint Satisfaction for Storage Files with Fifos or Stacks during
Scheduling [p. 824]
<DD><I>
C. Alba Pinto, B. Mesman, K. van Eijk, and J. Jess
</I><P>
</DL>
]]>