DATE 2001 TABLE OF CONTENTS
Sessions:
[Keynote]
[1A]
[1B]
[1C]
[1E]
[2A]
[2B]
[2C]
[2E]
[3A]
[3B]
[3C]
[3E]
[4A]
[4B]
[4C]
[4E]
[4F]
[5A]
[5B]
[5C]
[5E]
[5F]
[6A]
[6B]
[6C]
[6E]
[6F]
[7A]
[7B]
[7C]
[7E]
[7F]
[8A]
[8B]
[8C]
[8E]
[8F]
[9A]
[9B]
[9C]
[9E]
[9F]
[9L]
[10A]
[10B]
[10C]
[10E]
[10F]
[Posters]
DATE Executive Committee
Technical Program Chairs
Vendors Committee
DATE Sponsor Committee
Technical Program Committee
Reviewers
Welcome to DATE 2001
Best Paper Awards
Tutorials
Call for Papers DATE 2002
Plenary - Keynote Session
Moderator: A. Jerraya, TIMA, Grenoble, F
-
The Semiconductor Dynamic in the Information Age - Driving New
Technologies, Trends and Markets
-
U. Schumacher, CEO, Infineon, Munich, D
Moderators: T. Kropf, Robert Bosch GmbH, D; H. Eveking, TU Darmstadt, D
-
Abstraction of Word-Level Linear Arithmetic Functions from Bit-Level Component
Descriptions [p. 4]
-
P. Dasgupta, P. Chakrabarti, A. Nandi, S. Krishna, and A. Chakrabarti
-
Biasing Symbolic Search by Means of Dynamic Activity Profiles [p. 9]
-
G. Cabodi, P. Camurati, and S. Quer
Moderators: W. Rosenstiel, FZI/Tuebingen U, D; E. Villar, Cantabria U, ES
-
A Methodology for Interfacing Open Source SystemC with a Third Party Software
[p. 16]
-
L. Charest, M. Reid, E. Aboulhamid, and G. Bois
-
Behavioral Synthesis with SystemC [p. 21]
-
G. Economakos, P. Oikonomakos, I. Panagopoulos, I. Poulakis, and G.
Papakonstantinou
-
SystemCSV - An Extension of SystemC for Mixed Multi-Level
Communication Modeling and Interface-Based System Design [p. 26]
-
R. Siegmund and D. Müller
Organizer: Y. Zorian, LogicVision, USA
Moderator: P. Prinetto, Politecnico di Torino, IT
Speakers: J. Teixeira, IST/INESC, PT; I. Teixeira, IST/INESC, PT; C. Pereira,
UFRGS, BR; O. Dias, IST/INESC, PT; J. Semiao, IST/INESC, PT; P. Muhmenthaler,
Infineon, D; Y. Zorian, LogicVision, USA; W. Radermacher, Agilent, USA
-
Test Resource Partitioning: A Design and Test Issue [p. 34]
Organizer and Moderator: P. van Staa, Robert Bosch GmbH, D
Speaker: T. Beck, ETAS GmbH, D
-
Current Trends in the Design of Automotive Electronic Systems [p. 38]
Moderators: G. Martin, Cadence, USA; R. Seepold, FZI, D
-
Component Selection and Matching for IP-Based Design [p. 40]
-
T. Zhang, L. Benini, and G. De Micheli
-
A Universal Communication Model for an Automotive System Integration Platform [p. 47]
-
T. Demmeler and P. Giusto
-
An Efficient Architecture Model for Systematic Design of Application-Specific
Multiprocessor SoC [p. 55]
-
A. Baghdadi, D. Lyonnard, N. Zergainoh, and A. Jerraya
Moderators: N. Fristacky, Slovak TU, SLK; F. Rammig, C-LAB/Paderborn U, D
-
The Simulation Semantics of SystemC [p. 64]
-
J. Ruf, D. Hoffmann, J. Gerlach, T. Kropf, W. Rosenstiehl, and W. Mueller
-
MetaRTL: Raising the Abstraction Level of RTL Design [p. 71]
-
J. Zhu
-
A Model for Describing Communication between Aggregate Objects in the
Specification and Design of Embedded Systems [p. 77]
-
K. Svarstad, G. Nicolescu, and A. Jerraya
Moderators: P. Harrod, ARM, UK; B. Becker, Freiburg U, D
-
Circuit Partitioning for Efficient Logic BIST Synthesis [p. 86]
-
A. Irion, G. Kiefer, H. Vranken, and H. Wunderlich
-
Deterministic Software -Based Self-Testing of Embedded Processor Cores [p. 92]
-
A. Paschalis, D. Gizopoulos, N. Kranitis, M. Psarakis, and Y. Zorian
-
Memory Fault Diagnosis by Syndrome Compression [p. 97]
-
J. Li and C. Wu
-
Diagnosis for Scan-Based BIST: Reaching Deep into the Signatures [p. 102]
-
I. Bayraktaroglu and A. Orailoglu
Organizer: P. van Staa, Robert Bosch GmbH, D
Moderator: S. Reiniger, DaimlerChrysler, D
-
Vehicle Electric/Electronic Architecture - One of the Most Important
Challenges for OEM's [p. 112]
-
G. Hettich and T. Thurner
-
AIL: description of a global electronic architecture at the vehicle scale
-
Arjun Panday, Damien Couderc, Simon Marichalar
-
Methods and Tools for Systems Engineering of Automotive Electronic
Architectures
- Jakob Axelsson
Moderators: W. Damm, Oldenburg U/OFFIS, D; C. Delgado Kloos, U Carlos III de
Madrid, ES
-
Using SAT for Combinational Equivalence Checking [p. 114]
-
E. Goldberg, M. Prasad, and R. Brayton
-
Combinational Equivalence Checking Using Boolean Satisfiability and Binary
Decision Diagrams [p. 122]
-
S. Reda and A. Salem
-
An Efficient Learning Procedure for Multiple Implication Checks [p. 127]
-
Y. Novikov and E. Goldberg
Organizers: D. Gajski, UC Irvine, USA; E. Villar, Cantabria U, ES
Moderator: E. Villar, Cantabria U, ES
Panellists: W. Rosenstiel, FZI/Tuebingen U, D; V. Gerousis, Infineon, D; D. Barton, Averstar, USA; J. Plantin, Ericsson, SE; P. Cavalloro, Italtel, IT; D.
Gajski, UC Irvine, USA; G. de Jong, Telelogic, B
-
C/C ++ : Progress or Deadlock in System-Level Specification [p. 136]
Moderators: P. Muhmenthaler, Infineon Technologies, D; E.J. Marinissen, Philips Research, NL
-
An Integrated System-On-Chip Test Framework [p. 138]
-
E. Larsson and Z. Peng
-
Efficient Test Data Compression and Decompression for System-on-a-Chip Using
Internal Scan Chains and Golomb Coding [p. 145]
-
A. Chandra and K. Chakrabarty
-
Testing TAPed Cores and Wrapped Cores with the Same Test Access Mechanism
[p. 150]
-
M. Benabdenbi, W. Maroufi, and M. Marzouki
-
On Applying the Set Covering Model to Reseeding [p. 156]
-
S. Chiusano, S. Di Carlo, P. Prinetto, and H. Wunderlich
Organizer: P. van Staa, Robert Bosch GmbH, D
Moderator: H. Heidbrink, Descon GmbH, D
Panellists: B. Potock, Mentor Graphics Corp, USA; J. Mueller, Rosemann
&Lauridsen GmbH, D; U. Ahle, Siemens Business Services, D; C. Basille,
Aerospatiale Matra Missiles, F; W. Kisselmann, Infineon Technologies, D;
W. Herden, Robert Bosch GmbH, D
-
Data Management - Limiter or Accelerator for Electronic Design Creativity
[p. 162]
Moderators: H. Gräb, TU Munich, D; J. Eckmüller, Infineon
Technologies, D
-
Efficient Bit-Error-Rate Estimation of Multicarrier Transceivers [p. 164]
-
G. Vandersteen, P. Wambacq, Y. Rolain, J. Schoukens, S. Donnay,
M. Engels, I. Bolsens
-
Efficient Time -Domain Simulation of Telecom Frontends Using a Complex Damped
Exponential Signal Model [p. 169]
-
P. Vanassche, G. Gielen, and W. Sansen
-
Simulation Method to Extract Characteristics for Digital Wireless Communication Systems [p. 176]
-
L. Nguyen and V. Janicot
Moderators: G. Stamoulis, Intel, USA; K. Roy, Purdue U, USA
-
Microprocessor Power Analysis by Labeled Simulation [p. 182]
-
C. Hsieh, L. Chen, and M. Pedram
-
Power Aware Microarchitecture Resource Scaling [p. 190]
-
A. Iyer and D. Marculescu
-
Extending Lifetime of Portable Systems by Battery Scheduling [p. 197]
-
L. Benini, G. Castelli, A. Macii, E. Macii, M. Poncino, and R. Scarsi
Moderators: R. Galivanche, Intel, USA; B. Straube, FhG IIS/EAS Dresden, D
-
Efficient Spectral Techniques for Sequential ATPG [p. 204]
-
A. Giani, S. Sheng, M. Hsiao, and V. Agrawal
-
On the Test of Microprocessor IP Cores [p. 209]
-
F. Corno, M. Sonza Reorda, S. Squillero, and M. Violante
-
Sequence Reordering to Improve the Levels of Compaction Achievable by Static
Compaction Procedures [p. 214]
-
I. Pomeranz and S. Reddy
-
SEU Effect Analysis in an Open-Source Router via a Distributed Fault Injection
Environment [p. 219]
-
A. Benso, S. Di Carlo, G. Di Natale, and P. Prinetto
Organizer: A. Lock, Synopsys, USA
Moderator: R. Camposano, Synopsys, USA
Panellists: R. Camposano, Synopsys, USA; A. Cuomo, STMicrolectronics, IT;
R. Subramanian, MorphICs., USA; H. Meyr, TU Aachen, D
-
The Programmable Platform: Does One Size Fit All? [p. 226]
Moderators: F. Johannes, TU Munich, D; R. Otten, TU Delft, NL
-
Slicing Tree is a Complete Floorplan Representation [p. 228]
-
M. Lai and D. Wong
-
Further Improve Circuit Partitioning Using GBAW Logic Perturbation Techniques
[p. 233]
-
C. Cheung, Y. Wu, and D. Cheng
-
Clustering Based Fast Clock Scheduling for Light Clock-Tree [p. 240]
-
M. Saitoh, M. Azuma, and A. Takahashi
Moderators: N. Wehn, Kaiserslautern U, D; M. Bolle, Systemonic, D
-
Power-Efficient Layered Turbo Decoder Processor [p. 246]
-
J. Dielissen, J. van Meerbergen, M. Bekooij, F. Harmsze,
S. Sawitzki, J. Huisken, and A. van der Werf
-
Exploiting Data Forwarding to Reduce the Power Budget of VLIW Embedded Processors [p. 252]
-
M. Sami, D. Sciuto, C. Silvano, V. Zaccaria, and R. Zafalon
-
Design of Low-Power High-Speed Maximum a Priori Decoder Architectures [p. 258]
-
A. Worm, H. Lamm, and N. Wehn
Moderators: E. Macii, Politecnico di Torino, IT; D. Marculescu, Carnegie
Mellon U, USA
-
Low Complexity FIR Filters Using Factorization of Perturbed Coefficients
[p. 268]
-
C. Neau, K. Muhammad, and K. Roy
-
An Adaptive Algorithm for Low-Power Streaming Multimedia Processing [p. 273]
-
A. Acquaviva, L. Benini, and B. Riccó
-
A Static Power Estimation Methodology for IP-Based Design [p. 280]
-
X. Liu and C. Papaefthymiou
Moderators: C. Metra, DEIS-Bologna U, IT; R. Leveugle, TIMA, Grenoble, F
-
Optimization of Error Detecting Codes for the Detection of Crosstalk Originated Errors [p. 290]
-
M. Favalli and C. Metra
-
System Safety through Automatic High-Level Code Transformations: An Experimental Evaluation [p. 297]
-
P. Cheynet, B. Nicolescu, R. Velazco, M. Rebaudengo, M. Sonza Reorda,
and M. Violante
-
From DFT to Systems Test - A Model Based Cost Optimization Tool [p. 302]
-
M. Wahl, T. Ambler, C. Maaß and M. Rahman
-
Efficient On-Line Testing Method for a Floating-Point Adder [p. 307]
-
A. Drozd and M. Lobachev
Organizer: J. Rabaey, UC Berkeley, USA
Moderator: M. Engels, IMEC, B
-
Design Methodology for PicoRadio Networks [p. 314]
-
J. da Silva Jr., J. Shamberger, M. Ammer, C. Guo, S. Li,
R. Shah, T. Tuan, M. Sheets, J. Rabaey,
B. Nikolic, A. Sangiovanni-Vincentelli, and P. Wright
Moderators: W. John, Fraunhofer Institute Berlin/Paderborn, D;
F. Sabath, Armed Forces Institute for Protection Technologies, USA
-
High-Level Simulation of Substrate Noise Generation from
Large Digital Circuits with Multiple Supplies [p. 326]
-
M. Badaroglu, M. van Heijningen, V. Gravot, S. Donnay, H. De Man, G. Gielen
M. Engels, and I. Bolsens
-
Crosstalk Noise in Future Digital CMOS Circuits [p. 331]
-
C. Werner, R. Göttsche, A. Wörner, and U. Ramacher
-
Modeling Electromagnetic Emission of Integrated Circuits for System Analysis [p. 336]
-
P. Kralicek, W. John, and H. Garbe
-
Analysis of EME Produced by a Microcontroller Operation [p. 341]
-
F. Fiori and F. Musolino
Moderators: A. Kaiser, IEMN-ISEN, F; P. Wambacq, IMEC, B
-
Top-Down Design of a xDSL 14-bit 4MS/s Sigma-Delta Modulator in Digital CMOS Technology [p. 348]
-
R. del Río, J. de la Rosa, F. Medeiro, B. Pérez-Verdú, and A.
Rodríguez-Vázquez
-
Analog Design for Reuse - Case Study: Very Low-Voltage Sigma-Delta Modulator [p. 353]
-
M. Dessouky, A. Kaiser, M. Louërat, and A. Greiner
-
A Design Strategy for Low-Voltage Low-Power Continuous-Time
Sigma-Delta A/D Converters [p. 361]
-
F. Gerfers and Y. Manoli
Moderators: R. Murgai, Fujitsu Labs of America, USA; S. Minato, NTT, JP
-
Minimizing Stand-By Leakage Power in Static CMOS Circuits [p. 370]
-
S. Naidu and E. Jacobs
-
In-Place Delay Constrained Power Optmization Using Functional Symmetries
[p. 377]
-
C. Chang, B. Hu, and M. Marek-Sadowska
-
High-Quality Sub-Function Construction in Functional Decomposition Based on
Information Relationship Measures [p. 383]
-
L. Józwiak and A. Chojnacki
-
Generalized Reasoning Scheme for Redundancy Addition and Removal Logic Optimization [p. 391]
-
J. Espejo, L. Entrena, E. San Millán, and E. Olías
Moderators: J. Teixeira, IST/INESC, PT; M. Sonza Reorda, Politecnico di Torino, IT
-
LPSAT: A Unified Approach to RTL Satisfiability [p. 398]
-
Z. Zeng, P. Kalla, and M. Ciesielski
-
Functional Test Generation for Behaviorally Sequential Models [p. 403]
-
F. Ferrandi, G. Ferrara, D. Sciuto, A. Fin, and F. Fummi
-
High Quality Behavioral Verification Using Statistical Stopping Criteria [p. 411]
-
A. Hajjar, T. Chen, I. Munn, A. Andrews, and M. Bjorkman
Organizers: P. Bromley, F. Karim, and P. Paulin, STMicroelectronics, F
Moderator: P. Paulin, STMicroelectronics, F
-
Network Processors: A Perspective on Market Requirements,
Processor Architectures and Embedded S/W Tools [p. 420]
-
P. Paulin, F. Karim, and P. Bromley
Moderators: L. Silveira, IST/INESC, PT; H. Grabinski, Hannover U, D
-
Efficient Inductance Extraction via Windowing [p. 430]
-
M. Beattie and L. Pileggi
-
Efficient and Passive Modeling of Transmission Lines by Using Differential Quadrature Method [p. 437]
-
Q. Xu and P. Mazumder
-
Explicit Formulas and Efficient Algorithm for Moment Computation of Coupled RC
Trees with Lumped and Distributed Elements [p. 445]
-
Q. Yu and E. Kuh
-
On the Impact of On-Chip Inductance on Signal Nets under the Influence of Power Grid Noise [p. 451]
-
T. Chen
Moderators: S. Yoo, TIMA, Grenoble, F; F. Wagner, UFRGS, BRZ
-
Timing Simulation of Digital Circuits with Binary Decision Diagrams [p. 460]
-
R. Ubar, A. Jutman, and Z. Peng
-
HALOTIS: High Accuracy LOgic TIming Simulator with Inertial and Degradation
Delay Model [p. 467]
-
P. Vazquez, J. Juan-Chico, M. Bellido, A. Acosta, and M. Valencia
-
dlbSIM - A Parallel Functional Logic Simulator Allowing Dynamic Load Balancing [p. 472]
-
K. Hering, J. Löser, and J. Markwardt
-
Architecture Driven Partitioning [p. 479]
-
J. Küter and E. Barke
Moderator: C. Piguet, CSEM, Neuchatel, CH
-
Low-Power Systems on Chips (SOCs) [p. 488]
-
C. Piguet, M. Renaudin, and T. Omnès
Moderators: H. Kerkhoff, Twente U, NL; J. Pineda de Gyvez, Philips Research, NL
-
Static and Dynamic Behavior of Memory Cell Array Opens and Shorts in Embedded
DRAMs [p. 496]
-
Z. Al-Ars and A. van de Goor
-
Definitions of the Numbers of Detections of Target Faults and their
Effectiveness in Guiding Test Generation for High Defect Coverage [p. 504]
-
I. Pomeranz and S. Reddy
-
CMOS Open Defect Detection by Supply Current Test [p. 509]
-
M. Hashizume, M. Ichimiya, H. Yotsuyanagi, and T. Tamesada
-
Full Chip False Timing Path Identification: Applications to the
PowerPCTM Microprocessors [p. 514]
-
J. Zeng, M. Abadir, J. Bhadra, and J. Abraham
Moderator: P. Wambacq, IMEC, B
-
CAD for RF Circuits [p. 520]
-
P. Wambacq, G. Vandersteen, J. Phillips, J. Roychowdhury, W. Eberle, B. Yang,
D. Long, and A. Demir
Moderators: J. Lienig, Robert Bosch GmbH, D; A. Takahashi, Tokyo IT, JP
-
Modeling Crosstalk Noise for Deep Submicron Verification Tools [p. 530]
-
P. Bazargan-Sabet and F. Ilponse
-
A Graph Based Algorithm for Optimal Buffer Insertion under Accurate Delay Models [p. 535]
-
Y. Gao and D. Wong
-
Repeater Block Planning under Simultaneous Delay and Transition Time Constraints [p. 540]
-
P. Sarkar and C. Koh
Moderators: V. Meyer zu Bexten, Atmel Germany GmbH, D; E. Barke, Hannover U, D
-
On-The-Fly Layout Generation for PTL Macrocells [p. 546]
-
L. Macchiarulo, L. Benini, and E. Macii
-
Automatic Datapath Tile Placement and Routing [p. 552]
-
T. Serdar and C. Sechen
-
A Boolean Satisfiability-Based Incremental Rerouting Approach with Application
to FPGAs [p. 560]
-
G. Nam, K. Sakallah, and R. Rutenbar
Moderators: J. Plantin, Ericsson Radio Systems, SE; L. Lavagno, Udine U, IT
-
Dual Transitions Petri Net Based Modelling Technique for Embedded Systems
Specification [p. 566]
-
M. Varea and B. Al-Hashimi
-
Probabilistic Application Modeling for System-Level Performance Analysis
[p. 572]
-
R. Marculescu and A. Nandi
-
Reliable Estimation of Execution Time of Embedded Software [p. 580]
-
P. Giusto, G. Martin, and E. Harcourt
Moderators: M. Renovell, LIRMM, F; B. Kruseman, Philips Research, NL
-
Implementation of a Linear Histogram BIST for ADCs [p. 590]
-
F. Azaïs, S. Bernard, Y. Bertrand, and M. Renovell
-
Test Generation Based Diagnosis of Device Parameters for Analog Circuits [p. 596]
-
S. Cherubal and A. Chatterjee
-
Generation of Optimum Test Stimuli for Nonlinear Analog Circuits Using
Nonlinear Programming and Time -Domain Sensitivities [p. 603]
-
B. Burdiek
Organizer: D. Davis, Actel, USA
Moderator: R. Wilson, EETimes, USA
Panellists: T. Kambe, Sharp, JP; B. Gupta, STmicroelectronics, USA;
C. Balough, Triscend, USA; Y. Tanurhan, Actel, USA
-
Managing the SoC Design Challenge with "Soft" Hardware [p. 610]
-
R. Wilson
Moderators: J. Henkel, NEC, USA; R. Leupers, Dortmund U, D
-
Integrated Hardware-Software Co-Synthesis and High-Level Synthesis for Design i
of Embedded Systems under Power and Latency Constraints [p. 612]
-
A. Doboli
-
Allocation and Scheduling of Conditional Task Graph in Hardware/Software
Co-Synthesis [p. 620]
-
Y. Xie and W. Wolf
-
Code Placement in Hardware Software Co -Synthesis to Improve Performance and
Reduce Cost [p. 626]
-
S. Parameswaran
-
System-On-A-Chip Processor Synchronization Support in Hardware [p. 633]
-
B. Saglam and V. Mooney III
Moderators: K. Buchenrieder, Infineon Technologies, D; H. Grünbaecher,
Carinthia Tech. Inst., Villach, A
-
A Decade of Reconfigurable Computing: A Visionary Retrospective [p. 642]
-
R. Hartenstein
-
Hierarchical Memory Mapping during Synthesis in FPGA -Based Reconfigurable
Computers [p. 650]
-
I. Ouaiss and R. Vemuri
-
Optimal FPGA Module Placement with Temporal Precedence Constraints [p. 658]
-
S. Fekete, E. Köhler, and J. Teich
Moderators: P. Marwedel, Dortmund U, D; Z. Peng, Linkoping U, SE
-
Generation of Minimal Size Code for Schedule Graphs [p. 668]
-
C. Passerone, Y. Watanabe, and L. Lavagno
-
Generating Production Quality Software Development Tools Using a Machine
Description Language [p. 674]
-
A. Hoffmann, A. Nohl, S. Pees, G. Braun, and H. Meyr
-
Automatic Generation and Targeting of Application Specific Operating Systems
and Embedded Systems Software [p. 679]
-
L. Gauthier, S. Yoo, and A. Jerraya
-
Cache Conscious Data Layout Organization for Embedded Multimedia Applications
[p. 686]
-
C. Kulkarni, C. Ghez, M. Miranda, F. Catthoor, and H. De Man
Organizer and Moderator: G. Gielen, KU Leuven, B
Panellists: B. Sorensen, Atrium Design Solutions; H. Casier, Alcatel Microelectronics, B;
P. Magarshack, STMicroelectronics, F; J. Rodriguez, Anacad; J. Pollet, Dolphin, F
-
Design Challenges and Emerging EDA Solutions in Mixed-Signal IC Design [p. 694]
Organizers/Moderators: W. Rosenstiel, FZI/Tübingen U, D; Y. Nakamura,
Kyoto U, JP
Speakers: H. Tago, System LSI R&D Center, Toshiba Semiconductor Company;
A. Mandapati, ATI Research Inc (Subsidiary of Nintendo in the US);
S. Narita, Advanced Microcomputer Business Operation, System LSI Business Division, Hitachi Ltd.
-
CPU for PlayStation®2 [p. 696]
-
H. Tago, K. Hashimoto, N. Ikumi, M. Nagamatsu, M. Suzuoki, and Y. Yamamoto
-
Implementation of the ATI Flipper Chip [p. 697]
-
A. Mandapati
-
SH-4 RISC Microprocessor for Multimedia, Game Machine [p. 699]
-
S. Narita
Moderators: A. Oliveira, IST/INESC, PT; E. Macii, Politecnico di Torino, IT
-
Streaming BDD Manipulation for Large-Scale Combinatorial Problems [p. 702]
-
S. Minato and S. Ishihara
-
Binary Decision Diagram with Minimum Expected Path Length [p. 708]
-
Y. Liu, K. Wang, T. Hwang, and C. Liu
-
Spectral Decision Diagrams Using Graph Transformations [p. 713]
-
M. Thornton and R. Drechsler
Moderator: A. Jerraya, TIMA, Grenoble, F
Speaker: G. Matheron, MEDEA Office Director, Paris, F
-
Electronic System Design Methodology: Europe's Positioning [p. 720]
Moderators: R. Lauwereins, KU Leuven, B; R. Hartenstein, Kaiserslautern U, D
Precision and Error Analysis of MATLAB Applications during Automated
Hardware Synthesis for FPGAs [p. 722]
A. Nayak, M. Haldar, A. Choudhary, and P. Banerjee
A HW/SW Partitioning Algorithm for Dynamically Reconfigurable Architectures [p. 729]
J. Noguera and R. Badia
Managing Dynamic Reconfiguration Overhead in Systems -On-A-Chip Design Using
Reconfigurable Datapaths and Optimized Interconnection Networks [p. 735]
Z. Huang and S. Malik
Moderators: P. Schwarz, FhG IIS/EAS Dresden, D; M. Rencz, TU Budapest, H
-
Simulation-Guided Property Checking Based on a Multi-Valued AR-Automata [p. 742]
-
J. Ruf, D. Hoffmann, T. Kropf, and W. Rosenstiel
-
Performance Improvement of Multi-Processor Systems Cosimulation
Based on SW Analysis [p. 749]
-
J. Jung, S. Yoo and K. Choi
-
Mixed-Level Cosimulation for Fine Gradual Refinement of Communication in SoC
Design [p. 754]
-
G. Nicolescu, S. Yoo, and A. Jerraya
-
A Framework for Fast Hardware-Software Co-Simulation [p. 760]
-
A. Hoffmann, T. Kogel, and H. Meyr
Moderators: J. Vital, IST, PT; A. Rueda, CNM, Seville U, ES; A. Vasquez, CNM,
Seville U, ES
-
Analog/Mixed-Signal IP Modeling for Design Reuse [p. 766]
-
N. Madrid, E. Peralías, A. Acosta, and A. Rueda
-
A SkillTM-Based Library for Retargetable Embedded Analog Cores
[p. 768]
-
X. Jingnan, J. Vital, and N. Horta
-
Modelling SoC Devices for Virtual Test Using VHDL [p. 770]
-
M. Rona and G. Krampl
-
Retargeting of Mixed-Signal Blocks for SoCs [p. 772]
-
R. Castro-López, F. Fernández, M. Delgado-Restituto, and A.
Rodríguez-Vázquez
Organizer: C. Yeung, VSI Alliance, USA
Moderator: P. Clarke, Electronic Engineering Times, UK
Panellists: A. Haverinen, Nokia, FIN; USA; G. Matthews, STMicroelectronics, F;
J. Morris, ARM, UK, and J. Zaidi, Palmchip Corp., USA
-
Standard Bus vs. Bus Wrapper: What is the Best Solution for Future SoC Integration? [p. 776]
Moderators: A. Brown, Southampton U, UK; P. Eles, Linkoping U, SE
-
Access Pattern Based Local Memory Customization for Low Power Embedded Systems
[p. 778]
-
P. Grun, N. Dutt, and A. Nicolau
-
Static Memory Allocation by Pointer Analysis and Coloring [p. 785]
-
J. Zhu
-
Heuristic Datapath Allocation for Multiple Wordlength Systems [p. 791]
-
G. Constantinides, P. Cheung, and W. Luk
-
On the Verification of Synthesized Designs Using Automatically Generated
Transformational Witnesses [p. 798]
-
E. Teica, R. Radhakrishnan, and R. Vemuri
-
Property-Specific Witness Graph Generation for Guided Simulation [p. 799]
-
A. Casavant, A. Gupta, S. Liu, A. Mukaiyama, K. Wakabayashi, and P. Ashar
-
Two Approaches for Developing Generic Components in VHDL [p. 800]
-
V. Stuikys, G. Ziberkas, R. Damasevicius, and G. Majauskas
-
Annotated Data Types for Addressed Token Passing Networks [p. 801]
-
G. Cichon and W. Bunnbauer
-
Testability Trade-Offs for BIST RTL Data Paths: The Case for Three Dimensional
Design Space [p. 802]
-
N. Nicolici and B. Al-Hashimi
-
Towards a Better Understanding of Failure Modes and Test Requirements of ADCs
[p. 803]
-
A. Lechner, A. Richardson, and B. Hermes
-
Exact Fault Simulation for Systems on Silicon that Protects Each Core's
Intellectual Property (IP) [p. 804]
-
M. Quasem and S. Gupta
-
Using Mission Logic for Embedded Testing [p. 805]
-
R. Dorsch and H. Wunderlich
-
A Regularity-Based Hierarchical Symbolic Analysis Method for Large-Scale Analog Networks [p. 806]
-
A. Doboli and R. Vemuri
-
An Improved Hierarchical Classification Algorithm for Structural Analysis of Integrated Circuits [p. 807]
-
M. Olbrich, A. Rein, and E. Barke
-
Automatic Nonlinear Memory Power Modelling [p. 808]
-
E. Schmidt, G. Jochens, L. Kruse, F. Theeuwen, and W. Nebel
-
An Operation Rearrangement Technique for Power Optimization in VLIW Instruction Fetch [p. 809]
-
D. Shin, J. Kim, and N. Chang
-
A Pseudo Delay-Insensitive Timing Model to Synthesizing Low-Power Asynchronous Circuits [p. 810]
-
O. Garnica, J. Lanchares, and R. Hermida
-
A Register-Transfer-Level Fault Simulator for Permanent and Transient Faults in
Embedded Processors [p. 811]
-
C. Rousselle, M. Pflanz, A. Behling, T. Mohaupt, and H. Vierhaus
-
Efficient Finite Field Digit-Serial Multiplier Architecture for
Cryptography Applications [p. 812]
-
G. Bertoni, L. Breveglieri, and P. Fragneto
-
Task Concurrency Management Methodology Summary [p. 813]
-
C. Wong, P. Marchal, P. Yang, F. Catthoor, H. De Man,
A. Prayati, N. Cossement, R. Lauwereins, and D. Verkest
-
Susceptibility of Analog Cells to Substrate Interference [p. 814]
-
F. Fiori
-
Order Determination for Frequency Compensation of Negative-Feedback Systems [p. 815]
-
A. van Staveren and C. Verhoeven
-
Minimizing the Number of Floating Bias Voltage Sources with Integer Linear
Programming [p. 816]
-
E. Yildiz, A. van Staveren, and C. Verhoeven
-
CMOS Sizing Rule for High Performance Long Interconnects [p. 817]
-
G. Cappuccino and G. Cocorullo
-
On Automatic Analysis of Geometrically Proximate Nets in VLSI Layout [p. 818]
-
S. Koranne and O. Gangwal
-
AnalogRouter: A New Approach of Current-Driven Routing for Analog Circuits
[p. 819]
-
J. Lienig, G. Jerke, and T. Adler
-
A Hardware-Software Operating System for Heterogeneous Designs [p. 820]
-
J. Moya, F. Moya, and J. López
-
PRMDL: A Machine Description Language for Clustered VLIW Architectures [p. 821]
-
A. Terechko, E. Pol, and J. van Eijndhoven
-
Functional Units with Conditional Input/Output Behavior in VLIW Processors
[p. 822]
-
M. Bekooij, L. Engels, A. van der Werf, and N. Busá
-
Adaptation of an Event-Driven Simulation Environment to Sequentially Propagated
Concurrent Fault Simulation [p. 823]
-
M. Zolfy, S. Mirkhani, and Z. Navabi
-
Constraint Satisfaction for Storage Files with Fifos or Stacks during
Scheduling [p. 824]
-
C. Alba Pinto, B. Mesman, K. van Eijk, and J. Jess