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ISPD'99 :
[ <A HREF="ISPDABS.HTM;1">Abstracts</A> ]
[ <A HREF="ISPDSESS.HTM;1">Session Index</A> ]
[ <A HREF="ISPDAI.HTM;1">Author Index</A> ]</H3>
<HR>
<H2>ISPD'99 TABLE OF CONTENTS </H2>
<B>
Sessions:
[<A HREF="#sess10">1.0</A>]
[<A HREF="#sess11">1.1</A>]
[<A HREF="#sess12">1.2</A>]
[<A HREF="#sess13">1.3</A>]
[<A HREF="#sess14">1.4</A>]
[<A HREF="#sess15">1.5</A>]
[<A HREF="#sess20">2.0</A>]
[<A HREF="#sess21">2.1</A>]
[<A HREF="#sess22">2.2</A>]
[<A HREF="#sess23">2.3</A>]
[<A HREF="#sess24">2.4</A>]
[<A HREF="#sess25">2.5</A>]
[<A HREF="#sess30">3.0</A>]
[<A HREF="#sess31">3.1</A>]
[<A HREF="#sess32">3.2</A>]
[<A HREF="#sess33">3.3</A>]<P>
<A HREF="../../PDFFILES/FOREWORD.PDF;1">Forword</A><BR>
<A HREF="../../PDFFILES/COMM.PDF;1">Symposium Organization</A><P>
</B>
<HR>
<H2>Session 1.0: <A NAME="sess10">
Welcome and Keynote Address [p. 1]
</A></H2>
<I>Moderator: Dwight Hill (Synopsys)</I>
<DL>
<DT>
Welcome to ISPD-99 [p. 1]
<DD><I>D.F. Wong (UT-Austin)</I><P>
<DT>
Tales From the Trenches [p. 1]
<DD><I>C. Malachowski (nVidia)</I><P>
</DL>
<HR>
<H2>Session 1.1: <A HREF="ISPDABS.HTM;1#sess11" NAME="sess11">
Tutorial on Clocks</A></H2>
<I>Moderator: Sachin Sapatnekar (U. Minnesota)</I>
<DL>
<DT>
Challenges in Clock Distribution Networks [p. 2]
<DD><I>Eby Friedman, Niraj Bindal (U. Rochester, Intel)</I><P>
</DL>
<HR>
<H2>Session 1.2: <A HREF="ISPDABS.HTM;1#sess12" NAME="sess12">
Tutorial on Noise</A></H2>
<I>Moderator: Manfred Wiesel (Intel)</I>
<DL>
<DT>
<A HREF="ISPDABS.HTM;1#1_2"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/1_2_SCN.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
The Deep Sub-micron Signal Integrity Challenge [p. 3]
<DD><I>D. Kirkpatrick (Intel)</I><P>
</DL>
<HR>
<H2>Session 1.3: <A HREF="ISPDABS.HTM;1#sess13" NAME="sess13">
Analog Design and Signal Analysis
</A></H2>
<I>Moderator: C.K. Cheng (UCSD)</I>
<DL>
<DT>
<A HREF="ISPDABS.HTM;1#1_3_1"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/1_3_1.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
A Methodology to Analyze Power, Voltage Drop and Their Effects on Clock Skew/
Delay in Early Stages of Design [p. 9 ]
<DD><I>M. Iwabuchi, N. Sakamoto, Y. Sekine, T. Omachi (Hitachi)</I><P>
<DT>
<A HREF="ISPDABS.HTM;1#1_3_2"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/1_3_2SCN.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
EMI-Noise Analysis Under ASIC Design Environment [p. 16]
<DD><I>S. Hayashi, M.I. Yamada (Toshiba)</I><P>
<DT>
<A HREF="ISPDABS.HTM;1#1_3_3"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/1_3_3.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
An Efficient Sequential Quadratic Programming Formulation of Optimal Wire
Spacing for Cross-Talk Noise Avoidance Routing [p. 22]
<DD><I>P. Morton, W. Dai (UCSC)</I><P>
</DL>
<HR>
<H2>Session 1.4: <A HREF="ISPDABS.HTM;1#sess14" NAME="sess14">
Posters on Timing and Circuits
</A></H2>
<I>Moderator: Rob Rutenbar (CMU)</I>
<DL>
<DT>
<A HREF="ISPDABS.HTM;1#1_4_1"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/1_4_1.PDF;1"> <IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Post-Routing Timing Optimization with Routing Characterization [p. 30]
<DD><I>C. Changfan, Y.-C. Hsu, F.-S. Tsai (Avant!)</I><P>
<DT>
<A HREF="ISPDABS.HTM;1#1_4_2"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/1_4_2.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Buffer Insertion for Clock Delay and Skew Minimization [p. 36]
<DD><I>X. Zeng, D. Zhou, W. Li (Fudan U., UNC)</I><P>
<DT>
<A HREF="ISPDABS.HTM;1#1_4_3"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/1_4_3.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Incremental Capacitance Extraction and its Application to Iterative
Timing-Driven Detailed Routing [p. 42]
<DD><I>Y. Yuan, P. Banerjee (Northwestern U.)</I><P>
<DT>
<A HREF="ISPDABS.HTM;1#1_4_4"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/1_4_4.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Interconnect Coupling Noise in CMOS VSLI Circuits [p. 48]
<DD><I>K. Tang, E. Friedman (U. Rochester)</I><P>
</DL>
<HR>
<H2>Session 1.5: <A HREF="ISPDABS.HTM;1#sess15" NAME="sess15">
Panel: SCR Physical Design Top Ten Problems
</A></H2>
<I>Moderator: Chuck Alpert (IBM)</I>
<DL>
<DT>
<A HREF="ISPDABS.HTM;1#1_5_0"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/1_5_0.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
SRC Physical Design Top Ten Problems [p. 55]
<DD><I>J. Parkhurst, N. Sherwani, S. Maturi, D. Ahrams, E. Chiprout (Intel, LSI Logic Corp., National Semiconductor, IBM)</I><P>
</DL>
<HR>
<H2>Session 2: <A HREF="ISPDABS.HTM;1#sess20" NAME="sess20">
Benchmarks
</A></H2>
<I>Moderator: Jochen Jess (Eindhoven)</I>
<DL>
<DT>
<A HREF="ISPDABS.HTM;1#2_0_1"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/2_0_1.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Towards Synthetic Benchmark Circuits for Evaluating Timing-Driven CAD Tools
[p. 60]
<DD><I>D. Stroobandt, P.l Verplaetse, J. Van Campenhout (U. Ghent)</I><P>
<DT>
<A HREF="ISPDABS.HTM;1#2_0_2"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/2_0_2.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Generation of Very Large Circuits to Benchmark the Partitioning of FPGAs [p. 67]
<DD><I>J. Pistorius, E. Legai, M. Minoux (Mentor, Pierre et Marie Curie)</I><P>
<DT>
<A HREF="ISPDABS.HTM;1#2_0_3"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/2_0_3.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Transistor Level Micro-Placement and Routing for Two-Dimensional Digital VL
SI Cell Synthesis [p. 74]
<DD><I>M. Riepe, K. Sakallah (U. Michigan)</I><P>
</DL>
<HR>
<H2>Session 2.1: <A HREF="ISPDABS.HTM;1#sess21" NAME="sess21">
Partitioning, Placement, and Floorplanning
</A></H2>
<I>Moderator: Massoud Pedram (USC)</I>
<DL>
<DT>
<A HREF="ISPDABS.HTM;1#2_1_1"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/2_1_1.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Partitioning by Iterative Deletion [p. 83]
<DD><I>P.H. Madden (SUNY)</I><P>
<DT>
<A HREF="ISPDABS.HTM;1#2_1_2"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/2_1_2SCN.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Optimal Partitioners and End-Case Placers for Standard-Cell Layout [p. 90]
<DD><I>A.E. Caldwell, A.B. Kahng, I.L. Markov (UCLA)</I><P>
<DT>
<A HREF="ISPDABS.HTM;1#2_1_3"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/2_1_3.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Slicing Floorplans with Range Constraints [p. 97]
<DD><I>F.Y. Young, D.F. Wong (UT-Austin)</I><P>
<DT>
<A HREF="ISPDABS.HTM;1#2_1_4"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/2_1_4.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Arbitrary Convex and Concave Rectilinear Block Packing Using Sequence-Pair [p. 103]
<DD><I>K. Fujiyosi, H. Murata (Tokyo U.)</I><P>
</DL>
<HR>
<H2>Session 2.2: <A HREF="ISPDABS.HTM;1#sess22" NAME="sess22">
Tutorial on Manufacturing</A></H2>
<I>Moderator: Andrew Kahng (UCLA)</I>
<DL>
<DT>
<A HREF="ISPDABS.HTM;1#2_2_0"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/2_2_0.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Subwavelength Optical Lithography: Challenges and Impact on Physical Design
[p. 112]
<DD><I>A.B. Kahng, Y.C. Pati (UCLA, Numeric Technologies)</I><P>
</DL>
<HR>
<H2>Session 2.3: <A HREF="ISPDABS.HTM;1#sess23" NAME="sess23">
Sizing and Buffering, Plus Lithography
</A></H2>
<I>Moderator: Jason Cong (UCLA)</I>
<DL>
<DT>
<A HREF="ISPDABS.HTM;1#2_3_1"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/2_3_1.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Optimal Phase Conflict Removal for Layout of Dark Field Alternating Phase
Shifting Masks [p. 121]
<DD><I>P. Berman, A.B. Kahng, D. Vidhani, H. Wang, A. Zelikovsky (UCLA,
Penn State, Georgia State)</I><P>
<DT>
<A HREF="ISPDABS.HTM;1#2_3_2"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/2_3_2.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Gate Sizing with Controlled Displacement [p. 127]
<DD><I>W. Chen, C.-T. Hsieh, M. Pedram (USC)</I><P>
<DT>
<A HREF="ISPDABS.HTM;1#2_3_3"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/2_3_3.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Simultaneous Buffer Insertion and Non-Hanan Optimization for VLSI Interconnect
Under a Higher Order AWE Model [p. 133]
<DD><I>J. Hu, S. Sapatnekar (U. of Minnesota)</I><P>
</DL>
<HR>
<H2>Session 2.4: <A HREF="ISPDABS.HTM;1#sess24" NAME="sess24">
Posters on Placement and Partitioning
</A></H2>
<I>Moderator: Carl Sechen (U. Washington)</I>
<DL>
<DT>
<A HREF="ISPDABS.HTM;1#2_4_1"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/2_4_1.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Efficient Solution of Systems of Orientation Constraints [p. 140]
<DD><I>J. Ganley (Cadence)</I><P>
<DT>
<A HREF="ISPDABS.HTM;1#2_4_2"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/2_4_2.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
On The Behavior of Congestion Minimization During Placement [p. 145]
<DD><I>M. Wang, M. Sarrafzadeh (Northwestern U.)</I><P>
<DT>
<A HREF="ISPDABS.HTM;1#2_4_3"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/2_4_3SCN.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Partitioning with Terminals: A "New" Problem and New Benchmarks [p. 151]
<DD><I>C. J. Alpert, A. E. Caldwell, A.B. Kahng, I. L. Markov (UCLA and IBM)</I><P>
<DT>
<A HREF="ISPDABS.HTM;1#2_4_4"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/2_4_4.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Transistor Level Placement for Full Custom Datapath Cell Design [p. 158]
<DD><I>D. Vahia, M. Ciesielski (U. Mass)</I><P>
<DT>
<A HREF="ISPDABS.HTM;1#2_4_5"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/2_4_5.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Circuit Clustering Using Graph Coloring [p. 164]
<DD><I>A. Singh, M. Marek-Sadowska (UCSB)</I><P>
</DL>
<HR>
<H2>Session 2.5: <A HREF="ISPDABS.HTM;1#sess25" NAME="sess25">
Dinner Talk
</A></H2>
<I>Moderator: Martin Wong (UT-Austin)</I>
<DL>
<DT>
Why So Many Start-ups Today? A Designer and Venture Capitalist's View
<DD><I>A. Bechtolsheim (Silicon Valley)</I><P>
</DL>
<HR>
<H2>Session 3.0: <A HREF="ISPDABS.HTM;1#sess30" NAME="sess30">
Thermal and MCM
</A></H2>
<I>Moderator: Naveed Sherwani (Intel)</I>
<DL>
<DT>
<A HREF="ISPDABS.HTM;1#3_0_1"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/3_0_1.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Interconnect Thermal Modeling for Determining Design Limits on Current
Density [p. 172]
<DD><I>D. Chen, E. Li, E. Rosenbaum, S.-M. Kang (U. Illinois)</I><P>
<DT>
<A HREF="ISPDABS.HTM;1#3_0_2"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/3_0_2.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Standard Cell Placement for Even On-Chip Thermal Distribution [p. 179]
<DD><I>C.-H. Tsai, S.-M. Kang (U. Illinois)</I><P>
</DL>
<HR>
<H2>Session 3.1: <A HREF="ISPDABS.HTM;1#sess31" NAME="sess31">
Global Routing
</A></H2>
<I>Moderator: Patrick Groeneveld (Magma)</I>
<DL>
<DT>
<A HREF="ISPDABS.HTM;1#3_1_1"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/3_1_1.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
A Method of Measuring Nets Routability for MCM's General Area Routing Problems
[p. 186]
<DD><I>Kusnadi, J.D. Carothers (U. Arizona)</I><P>
<DT>
<A HREF="ISPDABS.HTM;1#3_1_2"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/3_1_2.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Getting to the Bottom of Deep Submicron II: The Global Wiring Paradigm [p. 193]
<DD><I>D. Sylvester, K. Keutzer (U. Berkeley)</I><P>
<DT>
<A HREF="ISPDABS.HTM;1#3_1_3"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/3_1_3.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Crosstalk Constrained Global Route Embedding [p. 201]
<DD><I>P. Parakh, R.B. Brown (U. Michigan)</I><P>
</DL>
<HR>
<H2>Session 3.2: <A HREF="ISPDABS.HTM;1#sess32" NAME="sess32">
Routing
</A></H2>
<I>Moderator: Ren-Song Tsay (Axis)</I>
<DL>
<DT>
<A HREF="ISPDABS.HTM;1#3_2_1"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/3_2_1.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Timing Driven Maze Routing [p. 208]
<DD><I>S.-W. Hur, A. Jagannathan, J. Lillis (U. Illinois at Chicago)</I><P>
<DT>
<A HREF="ISPDABS.HTM;1#3_2_2"><IMG SRC="../../../../../ICONS/ABSICON.GIF;1"></A>
<A HREF="../../PDFFILES/3_2_2.PDF;1"><IMG SRC="../../../../../ICONS/PDFICON.GIF;1"></A>
Via Design Rule Consideration in Multi-Layer Maze Routing Algorithms [p. 214]
<DD><I>J. Cong, J. Fang, K.-Y. Khoo (UCLA)</I><P>
</DL>
<HR>
<H2>Session 3.3: <A NAME="sess33">
Panel Physical Synthesis
</H2>
<I>Moderator: Wayne Dai (UCSC)</I>
<DL>
<DT>
Layout Driven Synthesis or Synthesis Driven Layout [p. 221]
<DD><I>W. Dai (UCSC)</I><P>
</DL>
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