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ICCAD'99 :
[ <A HREF="iccadabs.htm">Abstracts</A> ]
[ <A HREF="iccadses.htm">Session Index</A> ]
[ <A HREF="iccadai.htm">Author Index</A> ]</H3>
<HR>
<H2>ICCAD'99 TABLE OF CONTENTS</H2>
<B>
Sessions:
[<A HREF="#sess1a">1A</A>]
[<A HREF="#sess1b">1B</A>]
[<A HREF="#sess1c">1C</A>]
[<A HREF="#sess1d">1D</A>]
[<A HREF="#sess2a">2A</A>]
[<A HREF="#sess2b">2B</A>]
[<A HREF="#sess2c">2C</A>]
[<A HREF="#sess2d">2D</A>]
[<A HREF="#sess3a">3A</A>]
[<A HREF="#sess3b">3B</A>]
[<A HREF="#sess3c">3C</A>]
[<A HREF="#sess3d">3D</A>]
[<A HREF="#sess4a">4A</A>]
[<A HREF="#sess4b">4B</A>]
[<A HREF="#sess5a">5A</A>]
[<A HREF="#sess5b">5B</A>]
[<A HREF="#sess5c">5C</A>]
[<A HREF="#sess5d">5D</A>]
[<A HREF="#sess6a">6A</A>]
[<A HREF="#sess6b">6B</A>]
[<A HREF="#sess6c">6C</A>]
[<A HREF="#sess6d">6D</A>]
[<A HREF="#sess7a">7A</A>]
[<A HREF="#sess7b">7B</A>]
[<A HREF="#sess7c">7C</A>]
[<A HREF="#sess7d">7D</A>]
[<A HREF="#sess8a">8A</A>]
[<A HREF="#sess8b">8B</A>]
[<A HREF="#sess9a">9A</A>]
[<A HREF="#sess9b">9B</A>]
[<A HREF="#sess9c">9C</A>]
[<A HREF="#sess9d">9D</A>]
[<A HREF="#sess10a">10A</A>]
[<A HREF="#sess10b">10B</A>]
[<A HREF="#sess10c">10C</A>]
[<A HREF="#sess10d">10D</A>]
[<A HREF="#sess11a">11A</A>]
[<A HREF="#sess11b">11B</A>]
[<A HREF="#sess12a">12A</A>]
[<A HREF="#sess12b">12B</A>]<P>
<A HREF="../../pdffiles/foreword.pdf">Foreword</A><BR>
<A HREF="../../pdffiles/conf_com.pdf">Conference Committee</A><BR>
<A HREF="../../pdffiles/pgm_comm.pdf">Technical Program Committee</A><BR>
<A HREF="../../pdffiles/reviewer.pdf">Reviewers</A><BR>
<A HREF="../../pdffiles/tut1.pdf">Tutorial 1: Mixed-Signal Design: CAD,
Methodology, Case Studies</A><BR>
<A HREF="../../pdffiles/tut2.pdf">Tutorial 2: Modern Physical Design: Algorithm,
Technology and Methodology</A><BR>
<A HREF="../../pdffiles/tut3.pdf">Tutorial 3: Low Voltage/Low Power Design
Methodologies and CAD</A><BR>
<A HREF="../../pdffiles/tut4.pdf">Tutorial 4: Signal Integrity in High
Performance Design</A><BR>
<A HREF="../../pdffiles/panel1.pdf">Panel: CAD Roadmaps - Useful,
Redundant or Even Obstructive ?</A><BR>
<A HREF="../../pdffiles/panel2.pdf">Panel: System Level Design:
Designers' Wish List vs. Reality</A><BR>
<A HREF="../../pdffiles/cfp.pdf">Call for Papers</A><P>
</B>
<HR>
<H2>Session 1A: <A HREF="iccadabs.htm#sess1a" NAME="sess1a">
Sequential and Datapath Optimization
</A></H2>
<I>Moderators: Narendra V Shenoy, Synopsys, Inc., Mountain View, CA;
Maurizio Damiani, C2 Design Automation, Santa Clara, CA</I>
<DL>
<DT>
<A HREF="iccadabs.htm#01a_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/01a_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
1A.1 MARSH:Min-Area Retiming with Setup and Hold Constraints [p. 2]
<DD><I>Vijay Sundararajan, Sachin S. Sapatnekar, Keshab K. Parhi </I><P>
<DT>
<A HREF="iccadabs.htm#01a_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/01a_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
1A.2 OPTIMISTA: State Minimization of Asynchronous FSMs for Optimum
Output Logic [p. 7]
<DD><I>Robert M. Fuhrer, Steven M. Nowick </I><P>
<DT>
<A HREF="iccadabs.htm#01a_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/01a_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
1A.3 Bit-level Arithmetic Optimization for Carry-Save Additions [p. 14]
<DD><I>Kei-Yong Khoo, Zhan Yu, Alan N. Willson, Jr. </I><P>
</DL>
<HR>
<H2>Session 1B: <A HREF="iccadabs.htm#sess1b" NAME="sess1b">
Placement I
</A></H2>
<I>Moderator: Carl Sechen, University of Washington, Seattle, WA</I>
<DL>
<DT>
<A HREF="iccadabs.htm#01b_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/01b_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
1B.1 Attractor-Repeller Approach for Global Placement [p. 20]
<DD><I>Hussein Etawil, Shawki Areibi, Anthony Vannelli </I><P>
<DT>
<A HREF="iccadabs.htm#01b_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/01b_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
1B.2 Cell Replication and Redundancy Elimination During Placement for Cycle
Time Optimization [p. 25]
<DD><I>Ingmar Neumann, Dominik Stoffel, Hendrik Hartje, Wolfgang Kunz </I><P>
<DT>
<A HREF="iccadabs.htm#01b_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/01b_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
1B.3 Concurrent Logic Restructuring and Placement for Timing Closure [p. 31]
<DD><I>Jinan Lou, Wei Chen, Massoud Pedram </I><P>
</DL>
<HR>
<H2>Session 1C: <A HREF="iccadabs.htm#sess1c" NAME="sess1c">
BDDs in Formal Verification
</A></H2>
<I>Moderators: Andreas Kuehlmann, IBM Corporation, Yorktown Heights, NY;
David L. Dill, Stanford University, Stanford, CA</I>
<DL>
<DT>
<A HREF="iccadabs.htm#01c_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/01c_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
1C.1 Implicit Enumeration of Strongly Connected Components [p. 37]
<DD><I>Aiguo Xie, Peter A. Beerel </I><P>
<DT>
<A HREF="iccadabs.htm#01c_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/01c_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
1C.2 Least Fixpoint Approximations for Reachability Analysis [p. 41]
<DD><I>In-Ho Moon, James Kukula, Thomas Shiple, Fabio Somenzi </I><P>
<DT>
<A HREF="iccadabs.htm#01c_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/01c_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
1C.3 Lazy Group Sifting for Efficient Symbolic State Traversal of FSMs [p. 45]
<DD><I>Hiroyuki Higuchi, Fabio Somenzi </I><P>
<DT>
<A HREF="iccadabs.htm#01c_4"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/01c_4.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
1C.4 Efficient Manipulation Algorithms for Linearly Transformed BDDs [p. 50]
<DD><I>Wolfgang Günther, Rolf Drechsler </I><P>
</DL>
<HR>
<H2>Session 1D: <A HREF="iccadabs.htm#sess1d" NAME="sess1d">
Analog and Mixed-Signal
</A></H2>
<I>Moderators: Balsha Robert Stanisic, IBM Corporation, Rochester, MN;
Ramesh Harjani, University of Minnesota, Minneapolis, MN</I>
<DL>
<DT>
<A HREF="iccadabs.htm#01d_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/01d_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
1D.1 Noise Analysis of Non-Autonomous Radio Frequency Circuits [p. 55]
<DD><I>Amit Mehrotra, Alberto L. Sangiovanni-Vincentelli </I><P>
<DT>
<A HREF="iccadabs.htm#01d_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/01d_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
1D.2 New Methods for Speeding up Computation of Newton Updates in Harmonic
Balance [p. 61]
<DD><I>M. Gourary, S. Ulyanov, M. Zharov, S. Rusakov, K. Gullapalli,
B. Mulvaney </I><P>
<DT>
<A HREF="iccadabs.htm#01d_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/01d_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
1D.3 Design and Optimization of LC Oscillators [p. 65]
<DD><I>Maria del Mar Hershenson, Ali Hajimiri, Sunderarajan S. Mohan,
Stephen P. Boyd, Thomas H. Lee </I><P>
<DT>
<A HREF="iccadabs.htm#01d_4"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/01d_4.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
1D.4 Modeling and Simulation of the Interference due to Digital Switching in
Mixed-Signal ICs [p. 70]
<DD><I>Alper Demir, Peter Feldmann </I><P>
</DL>
<HR>
<H2>Session 2A: <A HREF="iccadabs.htm#sess2a" NAME="sess2a">
Power Optimization
</A></H2>
<I>Moderators: Renu Mehra, Synopsys, Inc., Mountain View, CA;
Luca Benini, University of Bologna, Bologna, Italy</I>
<DL>
<DT>
<A HREF="iccadabs.htm#02a_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/02a_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
2A.1 Provably Good Algorithm for Low Power Consumption with Dual Supply
Voltages [p. 76]
<DD><I>Chunhong Chen, Majid Sarrafzadeh </I><P>
<DT>
<A HREF="iccadabs.htm#02a_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/02a_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
2A.2 A Novel Design Methodology for High Performance and Low Power Digital
Filters [p. 80]
<DD><I>Khurram Muhammad, Kaushik Roy </I><P>
<DT>
<A HREF="iccadabs.htm#02a_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/02a_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
2A.3 A Bipartition-Codec Architecture to Reducing Power in Pipelined Circuits
[p. 84]
<DD><I>Shanq-Jang Ruan, Rung-Ji Shang, Feipei Lai, Shyh-Jong Chen and
Xian-Jun Huang </I><P>
</DL>
<HR>
<H2>Session 2B: <A HREF="iccadabs.htm#sess2b" NAME="sess2b">
Placement II
</A></H2>
<I>Moderators: Majid Sarrafzadeh, Northwestern University, Evanston, IL;
Gary Yeap, Monterey Design Systems, Inc., Sunnyvale, CA</I>
<DL>
<DT>
<A HREF="iccadabs.htm#02b_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/02b_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
2B.1 AKORD: Transistor Level and Mixed Transistor/Gate Level Placement Tool for Digital Data Paths [p. 91]
<DD><I>Tatjana Serdar, Carl Sechen </I><P>
<DT>
<A HREF="iccadabs.htm#02b_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/02b_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
2B.2 Analytical Approach to Custom Datapath Design [p. 98]
<DD><I>Serkan Askar, Maciej Ciesielski </I><P>
<DT>
<A HREF="iccadabs.htm#02b_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/02b_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
2B.3 An Integrated Algorithm for Combined Placement and Libraryless Technology
Mapping [p. 102]
<DD><I>Yanbin Jiang, Sachin S. Sapatnekar </I><P>
</DL>
<HR>
<H2>Session 2C: <A HREF="iccadabs.htm#sess2c" NAME="sess2c">
Domino- and ATPG-Based Logic Synthesis
</A></H2>
<I>Moderators: Rajeev Murgai, Fujitsu Labs. of America, Inc., Sunnyvale, CA;
Massoud Pedram, University of Southern California, Los Angeles, CA</I>
<DL>
<DT>
<A HREF="iccadabs.htm#02c_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/02c_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
2C.1 Timing-driven Partitioning for Two-Phase Domino and Mixed Static/Domino
Implementations [p. 107]
<DD><I>Min Zhao, Sachin S. Sapatnekar </I><P>
<DT>
<A HREF="iccadabs.htm#02c_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/02c_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
2C.2 Implication Graph based Domino Logic Synthesis [p. 111]
<DD><I>Ki-Wook Kim, C.L. Liu, Sung-Mo Kang </I><P>
<DT>
<A HREF="iccadabs.htm#02c_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/02c_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
2C.3 Synthesis for Multiple Input Wires Replacement of a Gate for Wiring
Consideration [p. 115]
<DD><I>Shih-Chieh Chang, Jung-Cheng Chuang, Zhong-Zhen Wu </I><P>
</DL>
<HR>
<H2>Session 2D: <A HREF="iccadabs.htm#sess2d" NAME="sess2d">
Electrical and Thermal Analysis
</A></H2>
<I>Moderators: Joel R. Phillips, Cadence Design Systems, Inc., San Jose, CA;
Peter Feldmann, Bell Labs., Murray Hill, NJ</I>
<DL>
<DT>
<A HREF="iccadabs.htm#02d_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/02d_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
2D.1 Transient Sensitivity Computation for Transistor Level Analysis and Tuning [p. 120]
<DD><I>Tuyen V. Nguyen, Peter R. O'Brien, David Winston </I><P>
<DT>
<A HREF="iccadabs.htm#02d_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/02d_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
2D.2 An Efficient Method for Hot-spot Identification in ULSI Circuits [p. 124]
<DD><I>Yi-Kan Cheng, Sung-Mo Kang </I><P>
<DT>
<A HREF="iccadabs.htm#02d_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/02d_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
2D.3 A Scalable Substrate Noise Coupling Model for Mixed-Signal ICs [p. 128]
<DD><I>Anil Samavedam, Karti Mayaram, Terri Fiez </I><P>
<DT>
<A HREF="iccadabs.htm#02d_4"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/02d_4.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
2D.4 Towards True Crosstalk Noise Analysis [p. 132]
<DD><I>Pinhong Chen, Kurt Keutzer </I><P>
</DL>
<HR>
<H2>Session 3A: <A HREF="iccadabs.htm#sess3a" NAME="sess3a">
Automatic Test Pattern Generation
</A></H2>
<I>Moderators: Janak H. Patel, University of Illinois, Urbana, IL;
Vamsi Boppana, Fujitsu Labs. of America, Sunnyvale, CA</I>
<DL>
<DT>
<A HREF="iccadabs.htm#03a_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/03a_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
3A.1 SAT Based ATPG Using Fast Justification and Propagation in the Implication Graph [p. 139]
<DD><I>Paul Tafertshofer, Andreas Ganz </I><P>
<DT>
<A HREF="iccadabs.htm#03a_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/03a_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
3A.2 Techniques for Improving the Efficiency of Sequential Circuit Test
Generation [p. 147]
<DD><I>Xijiang Lin, Irith Pomeranz, Sudhakar M. Reddy </I><P>
<DT>
<A HREF="iccadabs.htm#03a_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/03a_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
3A.3 Concurrent D-Algorithm on Reconfigurable Hardware [p. 152]
<DD><I>Fatih Kocan, Daniel G. Saab </I><P>
</DL>
<HR>
<H2>Session 3B: <A HREF="iccadabs.htm#sess3b" NAME="sess3b">
Routing
</A></H2>
<I>Moderators: Patrick Groeneveld, Magma Design Automation, Inc., Cupertino, CA;
Louis Scheffer, Cadence Design Systems, Inc., San Jose, CA</I>
<DL>
<DT>
<A HREF="iccadabs.htm#03b_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/03b_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
3B.1 A New Heuristic for Rectilinear Steiner Trees [p. 157]
<DD><I>Ion I. Mandoiu, Vijay V. Vazirani, Joseph L. Ganley </I><P>
<DT>
<A HREF="iccadabs.htm#03b_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/03b_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
3B.2 An Implicit Connection Graph Maze Routing Algorithm for ECO Routing [p. 163]
<DD><I>Jason Cong, Jie Fang, Kei-Yong Khoo </I><P>
<DT>
<A HREF="iccadabs.htm#03b_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/03b_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
3B.3 The Associative-Skew Clock Routing Problem [p. 168]
<DD><I>Yu Chen, Andrew B. Kahng, Gang Qu, Alexander Zelikovsky</I><P>
<DT>
<A HREF="iccadabs.htm#03b_4"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/03b_4.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
3B.4 Efficient Incremental Rerouting for Fault Reconfiguration in Field
Programmable Gate Arrays [p. 173]
<DD><I>Shantanu Dutt, Vimalvel Shanmugavel, Steve Trimberger </I><P>
</DL>
<HR>
<H2>Session 3C: <A HREF="iccadabs.htm#sess3c" NAME="sess3c">
Logic-Level Performance Optimization
</A></H2>
<I>Moderators: Masahiro Fujita, Fujitsu Labs. of America, Inc., Sunnyvale, CA;
Hamid Savoj, Magma Design Automation, Inc., Cupertino, CA</I>
<DL>
<DT>
<A HREF="iccadabs.htm#03c_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/03c_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
3C.1 Optimal P/N Width Ratio Selection for Standard Cell Libraries [p. 178]
<DD><I>David S. Kung, Ruchir Puri </I><P>
<DT>
<A HREF="iccadabs.htm#03c_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/03c_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
3C.2 Performance Optimization Under Rise and Fall Parameters [p. 185]
<DD><I>Rajeev Murgai </I><P>
<DT>
<A HREF="iccadabs.htm#03c_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/03c_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
3C.3 Performance Optimization Using Separator Sets [p. 191]
<DD><I>Yutaka Tamiya </I><P>
<DT>
<A HREF="iccadabs.htm#03c_4"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/03c_4.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
3C.4 Factoring Logic Functions Using Graph Partitioning [p. 195]
<DD><I>Martin C. Golumbic, Aviad Mintz </I><P>
</DL>
<HR>
<H2>Session 3D: <A HREF="iccadabs.htm#sess3d" NAME="sess3d">
Practical Issues in Order Reduction
</A></H2>
<I>Moderators: Luis Miguel Silveira, INESC, Lisboa, Portugal;
Tuyen V. Nguyen, IBM Austin Research Lab., Austin, TX</I>
<DL>
<DT>
<A HREF="iccadabs.htm#03d_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/03d_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
3D.1 TICER: Realizable Reduction of Extracted RC Circuits [p. 200]
<DD><I>Bernard N. Sheehan </I><P>
<DT>
<A HREF="iccadabs.htm#03d_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/03d_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
3D.2 Realizable Reduction for RC Interconnect Circuits [p. 204]
<DD><I>Anirudh Devgan, Peter R. O'Brien </I><P>
<DT>
<A HREF="iccadabs.htm#03d_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/03d_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
3D.3 RLC Interconnect Delay Estimation via Moments of Amplitude and Phase
Response [p. 208]
<DD><I>Xiaodong Yang, Walter H. Ku, Chung-Kuan Cheng </I><P>
<DT>
<A HREF="iccadabs.htm#03d_4"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/03d_4.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
3D.4 Practical Considerations For Passive Reduction of RLC Circuits [p. 214]
<DD><I>Altan Odabasioglu, Mustafa Celik, Lawrence T. Pileggi </I><P>
</DL>
<HR>
<H2>Session 4A: <A HREF="iccadabs.htm#sess4a" NAME="sess4a">
Embedded Tutorial
</A></H2>
<I>Moderator: Ellen M. Sentovich, Cadence Berkeley Labs., Berkeley, CA</I>
<DL>
<DT>
<A HREF="iccadabs.htm#04a_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
4A.1 Formal Verification Meets Simulation [p. 221]
<DD><I>David L. Dill, Serdar Tasiran </I><P>
</DL>
<HR>
<H2>Session 4B: <A HREF="iccadabs.htm#sess4b" NAME="sess4b">
Embedded Tutorial
</A></H2>
<I>Moderator: Lawrence T. Pileggi, Carnegie Mellon University, Pittsburgh, PA</I>
<DL>
<DT>
<A HREF="iccadabs.htm#04b_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
4B.1 Interconnect Parasitic Extraction in the IC Design Methodology [p. 223]
<DD><I>Matton Kamon, Stephen McCormick, Kenneth L. Shepard </I><P>
</DL>
<HR>
<H2>Session 5A: <A HREF="iccadabs.htm#sess5a" NAME="sess5a">
Timing Optimization
</A></H2>
<I>Moderator: Alexander T. Ishii, NEC USA, C&C Research Labs., Princeton, NJ</I>
<DL>
<DT>
<A HREF="iccadabs.htm#05a_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/05a_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
5A.1 Cycle Time and Slack Optimization for VLSI-Chips [p. 232]
<DD><I>Christoph Albrecht, Bernhard Korte, Juergen Schietke, Jens Vygen </I><P>
<DT>
<A HREF="iccadabs.htm#05a_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/05a_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
5A.2 Clock Skew Scheduling for Improved Reliability via Quadratic Programming [p. 239]
<DD><I>Ivan S. Kourtev, Eby G. Friedman </I><P>
<DT>
<A HREF="iccadabs.htm#05a_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/05a_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
5A.3 Formulation of Static Circuit Optimization with Reduced Size, Degeneracy
and Redundancy by Timing Graph Manipulation [p. 244]
<DD><I>Chandu Visweswariah, Andrew R. Conn </I><P>
</DL>
<HR>
<H2>Session 5B: <A HREF="iccadabs.htm#sess5b" NAME="sess5b">
Compilation Techniques for Embedded Systems
</A></H2>
<I>Moderators: Abhijit Ghosh, Synopsys, Inc., Mountain View, CA;
Donatella Sciuto, Politecnico di Milano, Milano, Italy</I>
<DL>
<DT>
<A HREF="iccadabs.htm#05b_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/05b_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
5B.1 Function Inlining under Code Size Constraints for Embedded Processors [p. 253]
<DD><I>Rainer Leupers, Peter Marwedel </I><P>
<DT>
<A HREF="iccadabs.htm#05b_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/05b_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
5B.2 Function Unit Specialization through Code Analysis [p. 257]
<DD><I>Daniel Benyamin, William H. Mangione-Smith </I><P>
<DT>
<A HREF="iccadabs.htm#05b_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/05b_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
5B.3 Lower Bound on Latency for VLIW ASIP Datapaths [p. 261]
<DD><I>Margarida F. Jacome, Gustavo de Veciana </I><P>
</DL>
<HR>
<H2>Session 5C: <A HREF="iccadabs.htm#sess5c" NAME="sess5c">
High Level Power Exploration
</A></H2>
<I>Moderators: Farid N. Najm, University of Toronto, Toronto, Canada;
Kaushik Roy, Purdue University, West Lafayette, IN</I>
<DL>
<DT>
<A HREF="iccadabs.htm#05c_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/05c_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
5C.1 Interface and Cache Power Exploration for Core-Based Embedded System
Design [p. 270]
<DD><I>Tony Givargis, Jörg Henkel, Frank Vahid </I><P>
<DT>
<A HREF="iccadabs.htm#05c_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/05c_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
5C.2 Dynamic Power Management Using Adaptive Learning Tree [p. 274]
<DD><I>Eui-Young Chung, Luca Benini, Giovanni De Micheli </I><P>
<DT>
<A HREF="iccadabs.htm#05c_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/05c_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
5C.3 Analytical Macromodeling for High-Level Power Estimation [p. 280]
<DD><I>Giuseppe Bernacchia, Marios C. Papaefthymiou </I><P>
<DT>
<A HREF="iccadabs.htm#05c_4"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/05c_4.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
5C.4 Parameterized RTL Power Models for Combinational Soft Macros [p. 284]
<DD><I>Alessandro Bogliolo, Roberto Corgnati, Enrico Macii, Massimo Poncino </I><P>
</DL>
<HR>
<H2>Session 5D: <A HREF="iccadabs.htm#sess5d" NAME="sess5d">
Analog and Mixed Signal Test
</A></H2>
<I>Moderators: Kwang-Ting (Tim) Cheng, University of California, Santa Barbara, CA; Shawn Blanton, Carnegie Mellon University, Pittsburgh, PA</I>
<DL>
<DT>
<A HREF="iccadabs.htm#05d_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/05d_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
5D.1 Validation and Test Generation for Oscillatory Noise in VLSI Interconnects [p. 289]
<DD><I>Arani Sinha, Sandeep K. Gupta, Melvin A. Breuer </I><P>
<DT>
<A HREF="iccadabs.htm#05d_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/05d_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
5D.2 Fault Modeling and Simulation for Crosstalk in System-on-Chip Interconnects [p. 297]
<DD><I>Michael Cuviello, Sujit Dey, Xiaoliang Bai, Yi Zhao </I><P>
<DT>
<A HREF="iccadabs.htm#05d_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/05d_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
5D.3 Robust Optimization Based Backtrace Method for Analog Circuits [p. 304]
<DD><I>Alfred V. Gomes, Abhijit Chatterjee </I><P>
</DL>
<HR>
<H2>Session 6A: <A HREF="iccadabs.htm#sess6a" NAME="sess6a">
Globally Untimed Locally Timed Design
</A></H2>
<I>Moderators: Kenneth Y. Yun, University of California at San Diego, La Jolla,
CA; Steven M. Nowick, Columbia University, New York, NY </I>
<DL>
<DT>
<A HREF="iccadabs.htm#06a_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/06a_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
6A.1 A Methodology for Correct-by-Construction Latency Insensitive Design [p. 309]
<DD><I>Luca P. Carloni, Kenneth L. McMillan, Alexander Saldanha,
Alberto L. Sangiovanni-Vincentelli </I><P>
<DT>
<A HREF="iccadabs.htm#06a_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/06a_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
6A.2 What is the cost of Delay Insensitivity ? [p. 316]
<DD><I>Hiroshi Saito, Alex Kondratyev, Jordi Cortadella, Luciano Lavagno,
Alexander Yakovlev </I><P>
<DT>
<A HREF="iccadabs.htm#06a_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/06a_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
6A.3 Synthesis of Asynchronous Control Circuits with Automatically Generated
Relative Timing Assumptions [p. 324]
<DD><I>Jordi Cortadella, Michael Kishinevsky, Steven M. Burns, Ken Stevens
</I><P>
<DT>
<A HREF="iccadabs.htm#06a_4"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/06a_4.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
6A.4 Direct Synthesis of Timed Asynchronous Circuits [p. 332]
<DD><I>Sung Tae Jung, Chris J. Myers </I><P>
</DL>
<HR>
<H2>Session 6B: <A HREF="iccadabs.htm#sess6b" NAME="sess6b">
Task-Level Analysis and Synthesis
</A></H2>
<I>Moderators: Francky Catthoor, IMEC, Leuven, Belgium;
Stan Liao, Synopsys, Inc., Mountain View, CA</I>
<DL>
<DT>
<A HREF="iccadabs.htm#06b_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/06b_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
6B.1 Co-Synthesis of Heterogeneous Multiprocessor Systems Using Arbitrated
Communication [p. 339]
<DD><I>David L. Rhodes, Wayne Wolf </I><P>
<DT>
<A HREF="iccadabs.htm#06b_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/06b_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
6B.2 Power Minimization using System-Level Partitioning of Applications with
Quality of Service Requirements [p. 343]
<DD><I>Gang Qu, Miodrag Potkonjak </I><P>
<DT>
<A HREF="iccadabs.htm#06b_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/06b_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
6B.3 Worst-case Analysis of Discrete Systems [p. 347]
<DD><I>Felice Balarin </I><P>
</DL>
<HR>
<H2>Session 6C: <A HREF="iccadabs.htm#sess6c" NAME="sess6c">
Floorplanning and Partitioning
</A></H2>
<I>Moderators: Naveed Sherwani, Intel Corporation, Hillsboro, OR;
Martin D. F. Wong, University of Texas, Austin, TX</I>
<DL>
<DT>
<A HREF="iccadabs.htm#06c_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/06c_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
6C.1 Integrated Floorplanning and Interconnect Planning [p. 354]
<DD><I>Hung-Ming Chen, Hai Zhou, F.Y. Young, D.F. Wong, Hannah H. Yang,
Naveed Sherwani </I><P>
<DT>
<A HREF="iccadabs.htm#06c_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/06c_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
6C.2 Buffer Block Planning for Interconnect-Driven Floorplanning [p. 358]
<DD><I>Jason Cong, Tianming Kong, David Zhigang Pan </I><P>
<DT>
<A HREF="iccadabs.htm#06c_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/06c_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
6C.3 A Clustering- and Probability-Based Approach for Time-Multiplexed FPGA
Partitioning [p. 364]
<DD><I>Mango C.-T. Chao, Guang-Ming Wu, Iris Hui-Ru Jiang, Yao-Wen Chang </I><P>
</DL>
<HR>
<H2>Session 6D: <A HREF="iccadabs.htm#sess6d" NAME="sess6d">
Advances in Model Order Reduction
</A></H2>
<I>Moderators: Ibrahim M. Elfadel, IBM Corporation, Yorktown Heights, NY;
Alper Demir, Bell Labs., Murray Hill, NJ</I>
<DL>
<DT>
<A HREF="iccadabs.htm#06d_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/06d_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
6D.1 The Chebyshev Expansion Based Passive Model for Distributed Interconnect
Networks [p. 370]
<DD><I>Janet M. Wang, Ernest S. Kuh and Qingjian Yu </I><P>
<DT>
<A HREF="iccadabs.htm#06d_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/06d_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
6D.2 Model Reduction for DC Solution of Large Nonlinear Circuits [p. 376]
<DD><I>Emad Gad, Michel Nakhla </I><P>
<DT>
<A HREF="iccadabs.htm#06d_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/06d_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
6D.3 Efficient Model Reduction of Interconnect via Approximate System Gramians [p. 380]
<DD><I>Jing-Rebecca Li, Jacob K. White </I><P>
</DL>
<HR>
<H2>Session 7A: <A HREF="iccadabs.htm#sess7a" NAME="sess7a">
Core Test
</A></H2>
<I>Moderators: Srinivas Patil, Mentor Graphics Corporation, Austin, TX;
Nur A. Touba, University of Texas, Austin, TX</I>
<DL>
<DT>
<A HREF="iccadabs.htm#07a_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/07a_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
7A.1 A Framework for Testing Core-Based Systems-on-a-Chip [p. 385]
<DD><I>Srivaths Ravi, Ganesh Lakshminarayana, Niraj K. Jha </I><P>
<DT>
<A HREF="iccadabs.htm#07a_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/07a_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
7A.2 Test Scheduling for Core-Based Systems [p. 391]
<DD><I>Krishnendu Chakrabarty </I><P>
<DT>
<A HREF="iccadabs.htm#07a_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/07a_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
7A.3 Partial BIST Insertion to Eliminate Data Correlation [p. 395]
<DD><I>Qiushuang Zhang, Ian Harris </I><P>
</DL>
<HR>
<H2>Session 7B: <A HREF="iccadabs.htm#sess7b" NAME="sess7b">
Graph Techniques for Design Optimization
</A></H2>
<I>Moderators: Sujit Dey, University of California at San Diego, La Jolla, CA;
Don MacMillen, Synopsys, Inc., Mountain View, CA</I>
<DL>
<DT>
<A HREF="iccadabs.htm#07b_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/07b_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
7B.1 A Graph Theoretic Optimal Algorithm for Schedule Compression in
Time-Multiplexed FPGA Partitioning [p. 400]
<DD><I>Huiqun Liu, Martin D. F. Wong </I><P>
<DT>
<A HREF="iccadabs.htm#07b_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/07b_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
7B.2 Throughput Optimization of General Non-Linear Computations [p. 406]
<DD><I>Inki Hong, Miodrag Potkonjak, Lisa M. Guerra </I><P>
<DT>
<A HREF="iccadabs.htm#07b_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/07b_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
7B.3 Optimal Allocation of Carry-Save-Adders in Arithmetic Optimization [p. 410]
<DD><I>Junhyung Um, Taewhan Kim, C.L. Liu </I><P>
<DT>
<A HREF="iccadabs.htm#07b_4"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/07b_4.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
7B.4 Regularity Extraction Via Clan-Based Structural Circuit Decomposition [p. 414]
<DD><I>Soha Hassoun, Carolyn McCreary </I><P>
</DL>
<HR>
<H2>Session 7C: <A HREF="iccadabs.htm#sess7c" NAME="sess7c">
Interconnect
</A></H2>
<I>Moderators: Jochen A.G. Jess, Eindhoven University of Technology, Eindhoven, The Netherlands;
Rajesh K. Gupta, University of California, Irvine, CA</I>
<DL>
<DT>
<A HREF="iccadabs.htm#07c_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/07c_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
7C.1 Repeater Insertion in Tree Structured Inductive Interconnect [p. 420]
<DD><I>Yehea I. Ismail, Eby G. Friedman, Jose L. Neves </I><P>
<DT>
<A HREF="iccadabs.htm#07c_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/07c_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
7C.2 Interconnect Scaling Implications for CAD [p. 425]
<DD><I>Ron Ho, Ken Mai, Hema Kapadia, Mark Horowitz </I><P>
<DT>
<A HREF="iccadabs.htm#07c_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/07c_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
7C.3 Is Wire Tapering Worthwhile? [p. 430]
<DD><I>Charles J. Alpert, Anirudh Devgan, Stephen T. Quay </I><P>
</DL>
<HR>
<H2>Session 7D: <A HREF="iccadabs.htm#sess7d" NAME="sess7d">
Techniques for Parasitic Extraction
</A></H2>
<I>Moderators: J. Eric Bracken, Ansoft Corporation, Pittsburgh, PA;
Keith Nabors, Cadence Design Systems, Inc., San Jose, CA</I>
<DL>
<DT>
<A HREF="iccadabs.htm#07d_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/07d_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
7D.1 Electromagnetic Parasitic Extraction via a Multipole Method with
Hierarchical Refinement [p. 437]
<DD><I>Michael W. Beattie, Lawrence T. Pileggi </I><P>
<DT>
<A HREF="iccadabs.htm#07d_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/07d_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
7D.2 Virtual Screening: A Step Towards a Sparse Partial Inductance Matrix [p. 445]
<DD><I>A.J. Dammers, N.P. van der Meijs </I><P>
<DT>
<A HREF="iccadabs.htm#07d_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/07d_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
7D.3 A Wide Frequency Range Surface Integral Formulation for 3-D RLC Extraction [p. 453]
<DD><I>J. Wang, J. Tausch, J. White </I><P>
</DL>
<HR>
<H2>Session 8A: <A HREF="iccadabs.htm#sess8a" NAME="sess8a">
Embedded Tutorial
</A></H2>
<I>Moderators: Lawrence T. Pileggi, Carnegie Mellon University, Pittsburgh, PA</I>
<DL>
<DT>
<A HREF="iccadabs.htm#08a_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
8A.1 SOI Technology and Tools [p. 459]
<DD><I>Sani R. Nassif, Tuyen V. Nguyen </I><P>
</DL>
<HR>
<H2>Session 8B: <A HREF="iccadabs.htm#sess8b" NAME="sess8b">
Embedded Tutorial
</A></H2>
<I>Moderator: Rolf Ernst, Technical University of Braunschweig, Braunschweig,
Germany</I>
<DL>
<DT>
<A HREF="iccadabs.htm#08b_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
8B.1 System Level Design and Debug of High-Performance Embedded Media Systems
[p. 461]
<DD><I>Kees A. Vissers, Pieter van der Wolf and Gert-Jan van
Rootselaar </I><P>
</DL>
<HR>
<H2>Session 9A: <A HREF="iccadabs.htm#sess9a" NAME="sess9a">
Test Pattern Analysis
</A></H2>
<I>Moderators: Robert Aitken, Hewlett-Packard Company, Palo Alto, CA;
Sreejit Chakravarty, Intel Corporation, Santa Clara, CA</I>
<DL>
<DT>
<A HREF="iccadabs.htm#09a_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/09a_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
9A.1 An Approach for Improving the Levels of Compaction Achieved by Vector
Omission [p. 463]
<DD><I>Irith Pomeranz, Sudhakar M. Reddy </I><P>
<DT>
<A HREF="iccadabs.htm#09a_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/09a_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
9A.2 Deep Submicron Defect Detection with the Energy Consumption Ratio [p. 467]
<DD><I>Bapiraju Vinnakota </I><P>
<DT>
<A HREF="iccadabs.htm#09a_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/09a_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
9A.3 Efficient Diagnosis of Path Delay Faults in Digital Logic Circuits [p. 471]
<DD><I>Pankaj Pant, Abhijit Chatterjee </I><P>
</DL>
<HR>
<H2>Session 9B: <A HREF="iccadabs.htm#sess9b" NAME="sess9b">
Memory and Interconnect Optimization in High Level Synthesis
</A></H2>
<I>Moderator: Kazutoshi Wakabayashi, NEC Corporation, Kawasaki, Japan</I>
<DL>
<DT>
<A HREF="iccadabs.htm#09b_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/09b_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
9B.1 Memory Bank Customization and Assignment in Behavioral Synthesis [p. 477]
<DD><I>Preeti Ranjan Panda </I><P>
<DT>
<A HREF="iccadabs.htm#09b_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/09b_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
9B.2 Memory Binding for Performance Optimization of Control-Flow Intensive
Behaviors [p. 482]
<DD><I>Kamal S. Khouri, Ganesh Lakshminarayana, Niraj K. Jha </I><P>
<DT>
<A HREF="iccadabs.htm#09b_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/09b_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
9B.3 Improved Interconnect Sharing by Identity Operation Insertion [p. 489]
<DD><I>Dirk Herrmann, Rolf Ernst </I><P>
</DL>
<HR>
<H2>Session 9C: <A HREF="iccadabs.htm#sess9c" NAME="sess9c">
System Verification
</A></H2>
<I>Moderators: Mandayam Srivas, SRI International, Menlo Park, CA;
Pei-Hsin Ho, Synospsys, Inc., Beaverton, OR</I>
<DL>
<DT>
<A HREF="iccadabs.htm#09c_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/09c_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
9C.1 Formal Specification and Verification of a Dataflow Processor Array [p. 494]
<DD><I>Thomas A. Henzinger, Xiaojun Liu, Shaz Qadeer, Sriram K. Rajamani </I><P>
<DT>
<A HREF="iccadabs.htm#09c_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/09c_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
9C.2 Distributed Simulation of VLSI Systems via Lookahed-Free Self-Adaptive
Optimistic and Conservative Synchronization [p. 500]
<DD><I>Dragos Lungeanu, C.-J. Richard Shi </I><P>
<DT>
<A HREF="iccadabs.htm#09c_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/09c_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
9C.3 Synchronous Equivalence for Embedded Systems: A Tool for Design
Exploration [p. 505]
<DD><I>Harry Hsieh, Felice Balarin, Luciano Lavagno, Alberto L. Sangiovanni-Vincentelli </I><P>
</DL>
<HR>
<H2>Session 9D: <A HREF="iccadabs.htm#sess9d" NAME="sess9d">
Fanout Optimization
</A></H2>
<I>Moderators: Yuji Kukimoto, Monterey Design Systems, Inc., Sunnyvale, CA;
Shih-Chieh Chang, National Chung-Cheng University, Chiayi, Taiwan ROC</I>
<DL>
<DT>
<A HREF="iccadabs.htm#09d_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/09d_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
9D.1 On The Global Fanout Optimization Problem [p. 511]
<DD><I>Rajeev Murgai </I><P>
<DT>
<A HREF="iccadabs.htm#09d_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/09d_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
9D.2 LEOPARD: A Logical Effort-based fanout OPtimization for ARea and Delay [p. 516]
<DD><I>Peyman Rezvani, Amir H. Ajami, Massoud Pedram, Hamid Savoj </I><P>
<DT>
<A HREF="iccadabs.htm#09d_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/09d_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
9D.3 Optimum Loading Dispersion for High-Speed Tree-Type Decision Circuitry [p. 520]
<DD><I>Jie-Hong Roland Jiang, Iris Hui-Ru Jiang </I><P>
</DL>
<HR>
<H2>Session 10A: <A HREF="iccadabs.htm#sess10a" NAME="sess10a">
Timing Analysis
</A></H2>
<I>Moderators: David J. Hathaway, IBM Corporation, Essex Junction, VT;
Joao P. Marques Silva, Technical University of Lisbon, Lisboa, Portugal</I>
<DL>
<DT>
<A HREF="iccadabs.htm#10a_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/10a_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
10A.1 Symbolic Functional and Timing Verification of Transistor-Level Circuits [p. 526]
<DD><I>Clayton B. McDonald, Randal E. Bryant </I><P>
<DT>
<A HREF="iccadabs.htm#10a_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/10a_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
10A.2 Body-Voltage Estimation in Digital PD-SOI circuits and its application to
Static Timing Analysis [p. 531]
<DD><I>Kenneth L. Shepard, Dae-Jin Kim </I><P>
<DT>
<A HREF="iccadabs.htm#10a_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/10a_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
10A.3 Functional Timing Optimization [p. 539]
<DD><I>Alexander Saldanha </I><P>
<DT>
<A HREF="iccadabs.htm#10a_4"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/10a_4.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
10A.4 Timing-Safe False Path Removal for Combinational Modules [p. 544]
<DD><I>Yuji Kukimoto, Robert K. Brayton </I><P>
</DL>
<HR>
<H2>Session 10B: <A HREF="iccadabs.htm#sess10b" NAME="sess10b">
Concurrency in Embedded Systems
</A></H2>
<I>Moderators: Joseph Buck, Synopsys, Inc., Mountain View, CA;
Wayne Wolf, Princeton University, Princeton, NJ</I>
<DL>
<DT>
<A HREF="iccadabs.htm#10b_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/10b_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
10B.1 JMTP: An Architecture for Exploiting Concurrency in Embedded Java
Applications with Real-Time Considerations [p. 551]
<DD><I>Rachid Helaihel, Kunle Olukotun </I><P>
<DT>
<A HREF="iccadabs.htm#10b_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/10b_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
10B.2 FunState - An Internal Design Representation for Codesign [p. 558]
<DD><I>Lothar Thiele, Karsten Strehl, Dirk Ziegenbein, Rolf Ernst, Jergen Teich </I><P>
<DT>
<A HREF="iccadabs.htm#10b_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/10b_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
10B.3 Fast Performance Analysis of Bus-Based System-On-Chip Communication
Architectures [p. 566]
<DD><I>Kanishka Lahiri, Anand Raghunathan, Sujit Dey </I><P>
</DL>
<HR>
<H2>Session 10C: <A HREF="iccadabs.htm#sess10c" NAME="sess10c">
Semi-Formal Verification
</A></H2>
<I>Moderators: Thomas R. Shiple, Synopsys, Inc., Mountain View, CA;
Alan Hu, The University British Columbia, Vancouver, Canada</I>
<DL>
<DT>
<A HREF="iccadabs.htm#10c_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/10c_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
10C.1 Probabilistic State Space Search [p. 574]
<DD><I>Andreas Kuehlmann, Kenneth L. McMillan, Robert K. Brayton </I><P>
<DT>
<A HREF="iccadabs.htm#10c_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/10c_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
10C.2 Improving Coverage Analysis and Test Generation for Large Designs [p. 580]
<DD><I>Jules P. Bergmann, Mark A. Horowitz </I><P>
<DT>
<A HREF="iccadabs.htm#10c_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/10c_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
10C.3 Modeling Design Constraints and Biasing in Simulation Using BDDs [p. 584]
<DD><I>Jun Yuan, Kurt Shultz, Carl Pixley, Hillel Miller, Adnan Aziz </I><P>
</DL>
<HR>
<H2>Session 10D: <A HREF="iccadabs.htm#sess10d" NAME="sess10d">
Intellectual Property Protection
</A></H2>
<I>Moderators: Emil S. Ochotta, Xilinx, Inc., San Jose, CA;
Margarida Jacome, University of Texas, Austin, TX</I>
<DL>
<DT>
<A HREF="iccadabs.htm#10d_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/10d_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
10D.1 Copyright Protection of Designs Based on Multi Source IPs [p. 591]
<DD><I>Edoardo Charbon, Ilhami Torunoglu </I><P>
<DT>
<A HREF="iccadabs.htm#10d_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/10d_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
10D.2 Localized Watermarking: Methodology and Application to Operation
Scheduling [p. 596]
<DD><I>Darko Kirovski, Miodrag Potkonjak </I><P>
<DT>
<A HREF="iccadabs.htm#10d_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/10d_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
10D.3 Copy Detection for Intellectual Property Protection of VLSI Designs [p. 600]
<DD><I>Andrew B. Kahng, Darko Kirovski, Stefanus Mantik, Miodrag Potkonjak,
Jennifer L. Wong </I><P>
</DL>
<HR>
<H2>Session 11A: <A HREF="iccadabs.htm#sess11a" NAME="sess11a">
Embedded Tutorial
</A></H2>
<I>Moderator: Jacob K. White, Massachusetts Institute of Technology, Cambridge, MA</I>
<DL>
<DT>
<A HREF="iccadabs.htm#11a_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
11A.1 Path Toward Future CAD Environments for MEMS [p. 606]
<DD><I>Gary K. Fedder, Tamal Mukherjee </I><P>
</DL>
<HR>
<H2>Session 11B: <A HREF="iccadabs.htm#sess11b" NAME="sess11b">
ICCAD/ISSS Invited Papers
</A></H2>
<I>Moderator: Nikil Dutt, University of California, Irvine, CA</I>
<DL>
<DT>
<A HREF="iccadabs.htm#11b_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
11B.1 Design of a Set-Top Box System on a Chip [p. 608]
<DD><I>Eric Foster </I><P>
<DT>
<A HREF="iccadabs.htm#11b_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
11B.2 On the Rapid Prototyping and Design of a Wireless Communication System on a Chip [p. 609]
<DD><I>Brian Kelley </I><P>
</DL>
<HR>
<H2>Session 12A: <A HREF="iccadabs.htm#sess12a" NAME="sess12a">
Embedded Tutorial
</A></H2>
<I>Moderator: Jacob K. White, Massachusetts Institute of Technology,
Cambridge, MA</I>
<DL>
<DT>
<A HREF="iccadabs.htm#12a_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
12A.1 Advances in Transistor Timing, Simulation, and Optimization [p. 611]
<DD><I>Jacob Avidan, Abe Elfadel, D.F. Wong </I><P>
</DL>
<HR>
<H2>Session 12B: <A HREF="iccadabs.htm#sess12b" NAME="sess12b">
Joint ICCAD/ISSS Session<BR>
Embedded Tutorial
</A></H2>
<I>Moderator:Reinaldo Bergamaschi, IBM Corporation, Yorktown Heights, NY</I>
<DL>
<DT>
<A HREF="iccadabs.htm#12b_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
12B.1 Embedded Java: Techniques and Applications [p. 613]
<DD><I>Brian Barry, John Duimovich </I><P>
</DL>
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