FPGA'99 TABLE OF CONTENTS

Welcome Message
Symposium Organization

Session 1: Commercial FPGA Architectures

1.1 A new high density and very low cost reprogrammable FPGA architecture [p. 3]

Sinan Kaptanoglu, Greg Bakker, Arun Kundu, Ivan Corneillet, Actel Corporation; Ben Ting, BTR Inc.

1.2 Hybrid Product Term and LUT Based Architectures Using Embedded Memory Blocks [p. 13]

Frank Heile, Andrew Leaver, Altera Corporation

1.3 An Innovative, Segmented High Performance FPGA Family with Variable-Grain- Architecture and Wide-gating Functions [p. 17]

Om Agrawal, Herman Chang, Brad Sharpe-Geisler, Nick Schmitz, Bai Nguyen, Jack Wong, Giap Tran, Fabiano Fontana, Bill Harding, Vantis Corporation

Session 2: Mapping, Packing and Floorplanning

2.1 Cut Ranking and Pruning: Enabling a General and Efficient FPGA Mapping Solution [p. 29]

Jason Cong, Chang Wu, University of California, Los Angeles, Yuzheng Ding, Lucent Technologies

2.2 Using Cluster-Based Logic Blocks and Timing-Driven Packing to Improve FPGA Speed and Density [p. 37]

Alexander Marquardt, Vaughn Betz, Jonathan Rose, University of Toronto

2.3 A Methodology for Fast FPGA Floorplanning [p. 47]

John Emmert, Dinesh Bhatia, University of Cincinatti

Session 3: FPGA Architecture Studies

3.1 FPGA Routing Architecture: Segmentation and Buffering to Optimize Speed and Density [p. 59]

Vaughn Betz, Jonathan Rose, University of Toronto

3.2 Balancing Interconnect and Computation in a Reconfigurable Computing Array (or, why you don't really want 100% LUT utilization) [p. 69]

André DeHon, University of California, Berkeley

Session 4: Rapid Reconfiguration

4.1 Configuration Cloning: Exploiting Regularity in Dynamic DSP Architectures [p. 81]

S.R. Park, W. Burleson, University of Massachusetts

4.2 Don't Care Discovery for FPGA Configuration Compression [p. 91]

Zhiyuan Li, Scott Hauck, Northwestern University

Session 5: Computational Applications

5.1 A FPGA-Based Hardware Implementation of Generalized Profile Search Using Online Arithmetic [p. 101]

Emeka Mosanya, Eduardo Sanchez, Swiss Federal Institute of Technology

5.2 Procedural Texture Mapping on FPGAs [p. 112]

Andy G. Ye, David M. Lewis, University of Toronto

Panel: FPGAs in the Era of Systems-on-a-Chip [p. 121]

Session 6: FPGAs for Custom Computing

6.1 HSRA: High-Speed, Hierarchical Synchronous Reconfigurable Array [p. 125]

William Tsu, Kip Macy, Atul Joshi, Randy Huang, Norman Walker, Tony Tung, Omid Rowhani, Varghese George, John Wawrzynek, André DeHon, University of California, Berkeley

6.2 A Reconfigurable Arithmetic Array for Multimedia Applications [p. 135]

Alan Marshall, Hewlett Packard; Jean Vuillemin, Ecole Normale Supérieure; Tony Stansfield, Igor Kostarnov, Hewlett Parkard; Brad Hutchings, Brigham Young University

6.3 Memory Interfacing and Instruction Specification for Reconfigurable Processors [p. 145]

Jeffrey A. Jacob, Paul Chow, University of Toronto

Session 7: Placement and Routing

7.1 Trading Quality for Compile Time: Ultra-Fast Placement for FPGAs [p. 157]

Yaska Sankar, Jonathan Rose, University of Toronto

7.2 Satisfiability-Based Layout Revisited: Detailed Routing of Complex FPGAs Via Search-Based Boolean SAT [p. 167]

Gi-Joon Nam, Karem A. Sakallah, University of Michigan; Rob A. Rutenbar, Carnegie Mellon University

7.3 Multi-Terminal Net Routing for Partial Crossbar-Based Multi-FPGA Systems [p. 176]

Abdel Ejnioui; University of South Florida; N. Ranganathan, University of Texas

Session 8: DPGAs and Pipeline Configurable FPGAs

8.1 Circuit Partitioning for Dynamically Reconfigurable FPGAs [p. 187]

Huiqun Liu, D.F. Wong, University of Texas

8.2 Fast Compilation for Pipelined Reconfigurable Fabrics [p. 195]

Mihai Budiu, Seth Copen Goldstein, Carnegie Mellon University

8.3 Configuration Caching Vs Data Caching for Striped FPGAs [p. 206]

Deepali Deshpande, Arun K. Somani, Akhilesh Tyagi, Iowa State University

Session 9: Applications

9.1 String Matching on Multicontext FPGAs using Self-Reconfiguration [p. 217]

Reetinder P.S. Sidhu, Alessandro Mei, Viktor K. Prasanna, University of Southern California

9.2 Reduction of Latency and Resource Usage in Bit-Level Pipelined Data Paths for FPGAs [p. 227]

P. Kollig, B.M. Al-Hashimi, Staffordshire University

9.3 Exploiting FPGA-Features during the Emulation of a Fast Reactive Embedded System [p. 235]

Karlheinz WeiB, Thorsten Steckstor, Gernot Koch, Wolfgang Rosenstiel, University of Tübingen

Poster Paper Abstracts [p. 243]