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ISSS'98 :
[ <A HREF="issstoc.htm">Table of Contents</A> ]
[ <A HREF="issssess.htm">Session Index</A> ]
[ <A HREF="isssai.htm">Author Index</A> ]</H3>
<HR>
<H2>ISSS'98 ABSTRACTS </H2>
<B>
Sessions:
[<A HREF="#invited1">Invited Talk</A>]
[<A HREF="#sess1">1</A>]
[<A HREF="#invited2">Invited Talk</A>]
[<A HREF="#sess2">2</A>]
[<A HREF="#poster">Poster Presentation</A>]
[<A HREF="#invited3">Invited Talk</A>]
[<A HREF="#sess3">3</A>]
[<A HREF="#sess4">4</A>]
[<A HREF="#sess5">5</A>]
[<A HREF="#sess6">6</A>]
</B></P>
<HR>
<H2>
<A NAME="invited1">
Invited Talk
</A></H2>
<DL>
<DT>
<B>Is IP Business Hype or Reality?</B>
<DD><I>D. D. Gajski</I><P>
Selling and using IPs seems to be the perfect solution for improving
design productivity. However, IP business models may not have adequate
infrastructures with which to flourish. This talk will elaborate on new
design styles, modeling guidelines, methodologies, and CAD tools needed
for successful reuse.<P>
</DL>
<HR>
<H2>Session 1:
<A NAME="sess1">
Code Generation and Optimization Issues
</A></H2>
<DL>
<DT>
<A HREF="../../pdffiles/1_1.pdf" NAME="1_1"><IMG SRC="../../../../../icons/pdficon.gif"></A>
<B>A Uniform Optimization Technique for Offset Assignment Problems [p. 3]</B>
<DD><I>Rainer Leupers, Fabian David</I><P>
A number of different algorithms for optimized offset assignment in
DSP code generation have been developed recently. These algorithms
aim at constructing a layout of local variables in memory, such
that the addresses of variables can be computed efficiently in most
cases. This is achieved by maximizing the use of auto-increment operations
on address registers. However, the algorithms published in previous work
only consider special cases of offset assignment problems, characterized by
fixed parameters such as register file sizes and auto-increment ranges. In
contrast, this paper presents a genetic optimization technique capable of
simultaneously handling arbitrary register file sizes and auto-increment
ranges. Moreover, this technique is the first that integrates the allocation
of modify registers into offset assignment. Experimental evaluation
indicates a significant improvement in the quality of constructed offset
assignments, as compared to previous work.<P>
<DT>
<A HREF="../../pdffiles/1_2.pdf" NAME="1_2"><IMG SRC="../../../../../icons/pdficon.gif"></A>
<B>Code Generation for Compiled Bit-True Simulation of DSP Applications [p. 9]</B>
<DD><I>L. De Coster, M. Adé, R. Lauwereins, J. A. Peperstraete</I><P>
Bit-true simulation verifies the finite word length choices in the VLSI
implementation of a DSP application. Present-day bit-true simulation tools
are time consuming. We elaborate a new approach in which the signal flow graph
of the application is analyzed and then transformed utilizing the flexibility
available on the simulation target. This global approach outperforms
current tools by an order of magnitude in simulation time.<P>
<DT>
<A HREF="../../pdffiles/1_3.pdf" NAME="1_3"><IMG SRC="../../../../../icons/pdficon.gif"></A>
<B>Addressing Optimization for Loop Execution Targeting DSP with Auto-Increment/Decrement Architecture [p. 15]</B>
<DD><I>Wei-Kai Cheng, Youn-Long Lin</I><P>
Since most DSP applications access large amount of data stored in the memory,
a DSP code generator must minimize the addressing overhead. In this paper,
we propose a method for addressing optimization in loop execution targeted
toward DSP processors with auto-increment/decrement feature in their address
generation unit. Our optimization methods include a multi-phase data ordering
and a graph-based address register allocation. The proposed approaches have
been evaluated using a set of core algorithms targeted towards the TI
TMS320C40 DSP processor. Experimental results show that our system is indeed
more effective compared to a commercial optimizing DSP compiler.<P>
</DL>
<HR>
<H2>
<A NAME="invited2">
Invited Talk
</A></H2>
<DL>
<DT>
<A HREF="../../pdffiles/inv_1.pdf" NAME="invited2_2"><IMG SRC="../../../../../icons/pdficon.gif"></A>
<B>Issues in Embedded DRAM Development and Applications [p. 23]</B>
<DD><I>D. Keitel-Schulz, N. Wehn</I><P>
After being niche markets for several years, application markets for
one-chip integration of large DRAMs and logic circuits are growing
very rapidly as the transition to 0.25um technologies will offer
customers up to 128 Mbit of embedded DRAM and 500 Kgates logic.
However, embedded DRAM implies many technical challenges to be solved.
In this paper we will address some of these technical issues in more
detail.<P>
</DL>
<HR>
<H2>Session 2:
<A NAME="sess2">
IP Reuse and Language
</A></H2>
<DL>
<DT>
<A HREF="../../pdffiles/2_1.pdf" NAME="2_1"><IMG SRC="../../../../../icons/pdficon.gif"></A>
<B>A Processor Description Language Supporting Retargetable Multi-Pipeline
DSP Program Development Tools [p. 31]</B>
<DD><I>Chuck Siska</I><P>
Many ISA-level machine description languages have been introduced to support
the automated development and retargeting of digital signal processor (DSP)
software development tools. These languages have yet to move below the
ISA-level and adequately address DSP pipeline issues. ISA-level bit-accurate
models may be reasonable for small micro-controllers, but are inadequate
when applied to complex high-performance DSPs. We introduce a new machine
description language, RADL, which supports the automated generation of DSP
programming tools. From RADL, we can generate production-quality tools
including cycle- and phase-accurate simulators. RADL has explicit support for
pipeline modeling, including delay slots, interrupts, hardware loops, hazards,
and multiple interacting pipelines in a natural and intuitive way. RADL can
represent both SIMD and MIMD instruction styles. We have coupled our language
to an in-house tool-chain generator which is used to create production
assemblers, simulators and compilers.<P>
<DT>
<A HREF="../../pdffiles/2_2.pdf" NAME="2_2"><IMG SRC="../../../../../icons/pdficon.gif"></A>
<B>Intellectual Property Re-use in Embedded System Co-design: An Industrial
Case Study [p. 37]</B>
<DD><I>E. Filippi, L. Lavagno, L. Licciardi, A. Montanaro, M. Paolini,
R. Passerone, M. Sgroi, A. Sangiovanni-Vincentelli</I><P>
Design of large systems on a chip would be infeasible without the capability
to flexibly adapt the system architecture to the application and the re-use
of existing Intellectual Property (IP). This in turn requires the use of an
appropriate methodology for system specification, architecture selection, IP
integration and implementation generation. The goals of this work are: a)
verification of the effectiveness of the POLIS HW/SW co-design methodology for
the design of embedded systems for telecom applications; b) definition of a
methodology for integrating system level IP libraries in this HW/SW co-design
framework. Methodology evaluations have been carried out through the
development of an industrial telecom system design, an ATM node server.<P>
<DT>
<A HREF="../../pdffiles/2_3.pdf" NAME="2_3"><IMG SRC="../../../../../icons/pdficon.gif"></A>
<B>Incorporating Cores into System-Level Specification [p. 43]</B>
<DD><I>Frank Vahid, Tony Givargis</I><P>
We describe an approach for incorporating cores into a system-level
specification. The goal is to allow a designer to specify both custom behavior
and pre-designed cores at the earliest design stages, and to refine both into
implementations in a unified manner. The approach is based on experience with
an actual application of a GPS- based navigation system. We use an
object-oriented language for specification, representing each core as an
object. We define three specification levels, and we evaluate the
appropriateness of existing inter-object communication methods for cores. The
approach forms the specification basis for the Dalton project.<P>
</DL>
<HR>
<H2>
<A NAME="poster">
Poster Presentations
</A></H2>
<DL>
<DT>
<A HREF="../../pdffiles/post_1.pdf" NAME="poster_1"><IMG SRC="../../../../../icons/pdficon.gif"></A>
<B>HDL-Based Modeling of Embedded Processor Behavior for Retargetable
Compilation [p. 51]</B>
<DD><I>Rainer Leupers</I><P>
The concept of retargetability enables compiler technology to keep pace with
the increasing variety of domain-specific embedded processors. In order to
achieve user retargetability, powerful processor modeling formalisms are
required. Most of the recent modeling formalisms concentrate on horizontal,
VLIW-like instruction formats. However, for encoded instruction formats with
restricted instruction-level parallelism (ILP), a large number of ILP
constraints might need to be specified, resulting in less concise processor
models. This paper presents an HDL-based approach to processor modeling for
retargetable compilation, in which ILP may be implicitly constrained. As a
consequence, the formalism allows for concise models also for encoded
instruction formats. The practical applicability of the modeling formalism is
demonstrated by means of a case study for a complex DSP.<P>
<DT>
<A HREF="../../pdffiles/post_2.pdf" NAME="poster_2"><IMG SRC="../../../../../icons/pdficon.gif"></A>
<B>False Path Analysis Based on a Hierarchical Control Representation
[p. 55]</B>
<DD><I>Apostolos A. Kountouris, Christophe Wolinski</I><P>
False path analysis is an activity with applications in a variety of computer
science and engineering domains like for instance high-level synthesis, worst
case execution time estimation, software testing etc. In this paper a method
to automate false path analysis, based on a control flow graph connected to a
hierarchical BDD based control representation, is described. By its ability to
reason on predicate expressions involving arithmetic inequalities, this method
overcomes certain limitations of previous approaches. Preliminary experimental
results confirm its effectiveness.<P>
<DT>
<A HREF="../../pdffiles/post_3.pdf" NAME="poster_3"><IMG SRC="../../../../../icons/pdficon.gif"></A>
<B>Resource Constrained Modulo Scheduling with Global Resource Sharing
[p. 60]</B>
<DD><I>Christoph Jäschke, Rainer Laur</I><P>
Commonly used scheduling algorithms in high-level synthesis are not capable of
sharing resources across process boundaries. This results in the usage of at
least one resource per operation type and process. A new method is proposed in
order to overcome these restrictions and to share high-cost or limited resources
within a process group. This allows the use of less than one resource per
operation type and process, while keeping the mutual independence of the
involved processes. The method which represents an extension of general
scheduling algorithms is not tied to a specific algorithm. The method is
explained by using the common List Scheduling and further on applied to
examples.<P>
<DT>
<A HREF="../../pdffiles/post_4.pdf" NAME="poster_4"><IMG SRC="../../../../../icons/pdficon.gif"></A>
<B>Statistical Performance-Driven Module Binding in High-Level Synthesis [p. 66]</B>
<DD><I>Hiroyuki Tomiyama, Akihiko Inoue, Hiroto Yasuura</I><P>
The inevitable fluctuation in fabrication processes results in LSI chips with
various critical path delay even though all the chips are fabricated from the
same design. Therefore, in LSI design, it is important to estimate what
percentage of the fabricated chips will achieve the performance level and to
maximize the percentage. This paper presents a model and a method to analyze
statistical delay of RT-level datapath designs. The method predicts the
probability that the fabricated circuits will work at a user specified clock
period. Using the method, we can estimate a tight bound on the worst case
critical path delay of the circuits. Based on the delay analysis method, a
high-level module binding algorithm which maximizes the probability is also
proposed. Experimental results demonstrate that the proposed statistical delay
analysis method leads to lower-cost or higher-performance designs than
conventional delay analysis methods.<P>
<DT>
<A HREF="../../pdffiles/post_5.pdf" NAME="poster_5"><IMG SRC="../../../../../icons/pdficon.gif"></A>
<B>Concurrent Error Detection at Architectural Level [p. 72]</B>
<DD><I>C. Bolchini, W. Fornaciari, F. Salice, D. Sciuto</I><P>
A methodology for designing systems with concurrent error detection capability
is introduced. The proposed approach consists of a functional architecture and
a checking architecture to verify data computed by the functional one. The
methodology reduces both redundancy and latency through hardware resources and
data sharing, respectively.<P>
<DT>
<A HREF="../../pdffiles/post_6.pdf" NAME="poster_6"><IMG SRC="../../../../../icons/pdficon.gif"></A>
<B>Communication and Interface Synthesis on a Rapid Prototyping
Hardware/Software Codesign System [p. 76]</B>
<DD><I>Yin-Tsung Hwang, Yuan-Hung Wang</I><P>
In this paper, we propose the target board architecture of a rapid prototyping
embedded system based on hardware software codesign. The target board contains
a TMS320C30 DSP processor and up to four Xilinx XC4025E FPGAs. Various
communication channels between the C30 and the FPGAs are provided and a
master-master computing paradigm is supported. HW/SW communication protocols,
ranging from handshaking, batch to queue controlled, as well as the
corresponding interfaces are described in VHDL and C codes respectively and
can be easily augmented to the mapped design. A codesign implementation example
based on G.728 LD-CELP speech decoder shows the proposed communication
protocols and interfaces lead to very small time and circuitry overhead.<P>
</DL>
<HR>
<H2>
<A NAME="invited3">
Invited Talk
</A></H2>
<DL>
<DT>
<B>Processor Architectures and Compilers for Systems on Chips</B>
<DD><I>Monica Lam</I><P>
As it becomes possible to integrate an entire system on a chip, the processor
architect is presented with an unprecedented opportunity to tailor the
processor to the application at hand. To fully realize the potential of this
technology, it is critical for us to be able to quickly produce an optimized
processor design and associated programming tools. Language and compilers have
an important role in the revolution of processor IP in ASIC designs. Many of
the advanced architectural ideas (parallelism, memory subsystem optimizations)
originally developed for high-end processors are directly applicable to this
environment. They often require more nontrivial compiler support.
Opportunities for application-specific optimizations can be exposed by means
of more expressive programming languages. Finally, program analyses can
extract program characteristics that can be used directly in guiding the
architecture customization process.<P>
</DL>
<HR>
<H2>Session 3:
<A NAME="sess3">
Application-Specific Synthesis Techniques
</A></H2>
<DL>
<DT>
<A HREF="../../pdffiles/3_1.pdf" NAME="3_1"><IMG SRC="../../../../../icons/pdficon.gif"></A>
<B>Application-Specific Heterogeneous Multiprocessor Synthesis Using
Differential-Evolution [p. 83]</B>
<DD><I>Allan Rae, Sri Parameswaran</I><P>
This paper presents an application-specific, heterogeneous multiprocessor
synthesis system, named HeMPS, that combines a form of Evolutionary Computation
known as Differential Evolution with a scheduling heuristic to search the
design space efficiently. We demonstrate the effectiveness of our technique by
comparing it to similar existing systems. The proposed strategy is shown to be
faster than recent systems on large problems while providing equivalent
or improved final solutions.<P>
<DT>
<A HREF="../../pdffiles/3_2.pdf" NAME="3_2"><IMG SRC="../../../../../icons/pdficon.gif"></A>
<B>Proposal for Unified System Design Meta Flow in Task-Level and
Instruction-Level Design Technology Research for Multi-Media Applications
[p. 89]</B>
<DD><I>Francky Catthoor, Diederik Verkest, Erik Brockmeyer</I><P>
This paper describes an attempt to bring together the many different system
design flows existing in architecture and system design technology research,
into a more abstract but unifying meta flow. Many existing system and
architecture design flows have a strong resemblance and unnecessary overlap.
Mainly due to a lack of a common and consistent terminology coupled to a common
reference basis, it is now nearly impossible to compare and reuse (sub)steps.
In addition, there is a too strong separation between research in different
communities. To alleviate this problem, we introduce a more abstract but
unifying meta flows which attempts to bridge the gap between the existing
flows. From this meta flow, a particular design flow can be instantiated for
a given application (domain) by leaving out the non-required stages/steps, by
selecting a (sub)step sequence which is compatible with the partial meta-flow
order, and by selecting the appropriate technique for all remaining (sub)steps
(e.g. the type of scheduler). This paper focuses on the principles at the
task- and instruction-level abstractions. It also provides an illustration of
the power of the metaflow principles for a realistic multi-media compression
demonstrator from the MPEG4 context.<P>
<DT>
<A HREF="../../pdffiles/3_3.pdf" NAME="3_3"><IMG SRC="../../../../../icons/pdficon.gif"></A>
<B>Data-Path Synthesis of VLIW Video Signal Processors [p. 96]</B>
<DD><I>Zhao Wu, Wayne Wolf</I><P>
This paper describes a methodology for synthesizing the data-path of a Very
Long Instruction Word (VLIW) based Video Signal Processor (VSP). Offering both
performance and programmability, VSPs are important for their roles in digital
video applications, which are omnipresent in today's world. Among many different
architectures, VLIW is becoming increasingly popular and widely used due to its
efficiency in exploiting high degree of parallelism inherent in multimedia
applications. While architectural syntheses of embedded systems have been
studied in depth, little literature has addressed similar issues for VLIW-based
VSPs. Using an MPEG-2 video encoder as a case study, in this paper we present a
combined application of trace-driven simulation and performance estimation in
the data-path synthesis of a VLIW VSP. Results show that our estimations are
quite precise and helpful, let alone that they are orders of magnitude faster
than simulation.<P>
</DL>
<HR>
<H2>Session 4:
<A NAME="sess4">
Synchronization and Interface Issues
</A></H2>
<DL>
<DT>
<A HREF="../../pdffiles/4_1.pdf" NAME="4_1"><IMG SRC="../../../../../icons/pdficon.gif"></A>
<B>Synchronization Detection for Multi-Process Hierarchical Synthesis
[p. 105]</B>
<DD><I>Oliver Bringmann, Wolfgang Rosenstiel, Dirk Reichardt</I><P>
Complex system specifications are often hierarchically composed of several
subsystems. Each subsystem contains one or more processes. In order to provide
optimization across different levels of hierarchy, a synchronicity analysis
of the concerned processes has to be performed during high-level synthesis.
The first step is the generation of a condensed graph representation of the
inter-process communication. This graph is then utilized to detect
inter-process communication which can be used to represent synchronization
points between two or more processes. A synchronization point represents the
starting point of an interval in which the communicating processes run
synchronously. This interval is limited by unbounded data-dependent loops,
denoted as de-synchronization points. As a result, different processes can
only share resources in such an interval.<P>
<DT>
<A HREF="../../pdffiles/4_2.pdf" NAME="4_2"><IMG SRC="../../../../../icons/pdficon.gif"></A>
<B>Integrating Communication Protocol Selection with Partitioning in
Hardware/Software Codesign [p. 111]</B>
<DD><I>Peter Voigt Knudsen, Jan Madsen</I><P>
This paper presents a codesign approach which incorporates communication
protocol selection as a design parameter within hardware/software partitioning.
The presented approach takes into account data transfer rates depending on
communication protocol types and configurations, and different operating
frequencies of system components, i.e. CPUs, ASICs, and busses. It also takes
into account the timing and area influences of drivers and driver calls needed
to perform the communication. The approach is illustrated by a number of design
space exploration experiments which use models of the PCI and USB communication
protocols.<P>
<DT>
<A HREF="../../pdffiles/4_3.pdf" NAME="4_3"><IMG SRC="../../../../../icons/pdficon.gif"></A>
<B>Interface Exploration for Reduced Power in Core-Based Systems [p. 117]</B>
<DD><I>Tony Givargis, Frank Vahid</I><P>
Reducing power dissipation is becoming more important in the design of embedded
systems. Core-based system design opens up the opportunity for exploring
different bus interfaces in order to optimize for reduced power. We give a
first approach for exploring a range of possible bus configurations, such as
width and coding schemes, for a given set of communication channels. Our
approach uses power estimation formulas, for fast performance. We use this
approach to explore different bus interfaces for a real GPS navigation system
in order to select the optimal bus interface for minimum power consumption.<P>
</DL>
<HR>
<H2>Session 5:
<A NAME="sess5">
Instruction Encoding and Software Synthesis Techniques
</A></H2>
<DL>
<DT>
<A HREF="../../pdffiles/5_1.pdf" NAME="5_1"><IMG SRC="../../../../../icons/pdficon.gif"></A>
<B>Instruction Encoding Techniques for Area Minimization of Instruction ROM [p. 125]</B>
<DD><I>T. Okuma, H. Tomiyama, A. Inoue, E. Fajar, H. Yasuura</I><P>
In this paper, we propose instruction encoding techniques for embedded system
design, which encode immediate fields of instructions to reduce the size of an
instruction memory. Although our proposed techniques require an additional
decoder for the encoded immediate values, experimental results demonstrate the
effectiveness of our techniques to reduce the chip area.<P>
<DT>
<A HREF="../../pdffiles/5_2.pdf" NAME="5_2"><IMG SRC="../../../../../icons/pdficon.gif"></A>
<B>Application of Instruction Analysis/Synthesis Tools to x86's Functional Unit Allocation [p. 131]</B>
<DD><I>Ing-Jer Huang, Ping-Huei Xie</I><P>
Designing a cost effective superscalar architecture for x86 compatible
microprocessors is a challenging task in terms of both technical difficulty
and commercial value. One of the important design issues is the measurements
of the distribution of functional unit usage and the micro operation level
parallelism (MLP), which together determine the proper allocation of functional
units in the superscalar architecture. To obtain such measurements, an x86
instruction set CAD system x86 Workshop is developed, which consists of both
instruction set analysis and optimization tools. x86 Workshop has been applied
to analyze several popular Windows95 applications such as Word, Excel,
Communicator, etc. The MLP and distribution of functional unit usage are
measured for these applications. The measurements are used to evaluate several
existing x86 superscalar processors and suggest future extension.<P>
<DT>
<A HREF="../../pdffiles/5_3.pdf" NAME="5_3"><IMG SRC="../../../../../icons/pdficon.gif"></A>
<B>Memory Efficient Software Synthesis from Dataflow Graph [p. 137]</B>
<DD><I>Wonyong Sung, Junedong Kim, Soonhoi Ha</I><P>
Due to the limited amount of memory resources in embedded systems, minimizing
the memory requirements is an important goal of software synthesis. This paper
presents a set of techniques to reduce the code and data size for software
synthesis from graphical DSP programs based on the synchronous dataflow (SDF)
model. By sharing the kernel code among multiple instances of a block, we can
further reduce the code size below the single appearance schedule. And, a
systematic approach is presented to give up single appearance schedules to
reduce the data buffer requirements. Experimental results from two real
examples prove the significance of the proposed techniques.<P>
</DL>
<HR>
<H2>Session 6:
<A NAME="sess6">
Partitioning and Scheduling Techniques
</A></H2>
<DL>
<DT>
<A HREF="../../pdffiles/6_1scn.pdf" NAME="6_1"><IMG SRC="../../../../../icons/pdficon.gif"></A>
<B>A Tool for Partitioning and Pipelined Scheduling of Hardware-Software
Systems [p. 145]</B>
<DD><I>Karam S. Chatha, Ranga Vemuri</I><P>
We present a tool for synthesis of pipelined implementations of
hardware-software systems. The tool uses iterative hardware-software
partitioning and pipelined scheduling to obtain optimal partitions which
satisfy the timing and area constraints. The partitioner uses a branch
and bound approach with a unique objective function which minimizes the
initiation interval of the final design. It takes communication time and
hardware sharing into account. This paper also presents techniques for
generation of good initial solution and search space bounding for the
partitioning algorithm. A candidate partition is evaluated by generating
its pipelined schedule. The scheduler uses a list based scheduler and a
retiming transformation to optimize the initiation interval, number of
pipeline stages and memory requirements of a particular design alternative.
The effectiveness of the tool is demonstrated by experimentation.<P>
<DT>
<A HREF="../../pdffiles/6_2.pdf" NAME="6_2"><IMG SRC="../../../../../icons/pdficon.gif"></A>
<B>A Three-Step Approach to the Functional Partitioning of Large Behavioral
Processes [p. 152]</B>
<DD><I>Frank Vahid</I><P>
Earlier work has demonstrated that partitioning one large behavioral process
into smaller ones before synthesis can yield numerous advantages, such as
reduced synthesis runtime, easier package constraint satisfaction, reduced
power consumption, improved performance, and hardware/software tradeoffs. In
this paper, we describe a novel three-step functional partitioning methodology
for automatically dividing a large behavioral process into mutually-exclusive
subprocesses, and we define the problems and our solutions for each step. The
three steps are granularity selection, pre-clustering, and N-way assignment.
We refer to experiments throughout that demonstrate the effectiveness of the
solutions.<P>
<DT>
<A HREF="../../pdffiles/6_3.pdf" NAME="6_3"><IMG SRC="../../../../../icons/pdficon.gif"></A>
<B>Fine Grain Incremental Rescheduling Via Architectural Retiming [p. 158]</B>
<DD><I>Soha Hassoun</I><P>
With the decreasing feature sizes during VLSI fabrication and the dominance of
interconnect delay over that of gates, control logic and wiring no longer have
a negligible impact on delay and area. The need thus arises for developing
techniques and tools to redesign incrementally to eliminate performance
bottlenecks. Such a redesign effort corresponds to incrementally modifying an
existing schedule obtained via high-level synthesis. In this paper we
demonstrate that applying architectural retiming, a technique for pipelining
latency-constrained circuits, results in incrementally modifying an existing
schedule. Architectural retiming reschedules fine grain operations (ones that
have a delay equal to or less than one clock cycle) to occur in earlier time
steps, while modifying the design to preserve its correctness.<P>
</DL>
]]>