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<h3><a href="../../../../../main_ss.htm">Main Page</a></br>
GLSVLSI 1996 :
[ <a href="glsvabs.htm">Abstracts</a> ]
[ <a href="glsvsess.htm">Session Index</a> ]
[ <a href="glsvai.htm">Author Index</a> ]</h3>
<hr>
<h2>GLSVLSI 1996 TABLE OF CONTENTS</h2>
<b>
Sessions:
[<a href="#sess1a">1A</a>]
[<a href="#sess1b">1B</a>]
[<a href="#sess2a">2A</a>]
[<a href="#sess2b">2B</a>]
[<a href="#sess3a">3A</a>]
[<a href="#sess3b">3B</a>]
[<a href="#sess4a">4A</a>]
[<a href="#sess4b">4B</a>]
[<a href="#sess5a">5A</a>]
[<a href="#sess5b">5B</a>]
[<a href="#sess6a">6A</a>]
[<a href="#sess6b">6B</a>]
[<a href="#sess7a">7A</a>]
[<a href="#sess7b">7B</a>]<p>
<a href="../../pdffiles/message.pdf">Message from the Program Co-chairs</a><br>
<a href="../../pdffiles/smessage.pdf">Message from the Steering Chair</a><br>
<a href="../../pdffiles/committe.pdf">Steering Committee</a><br>
<a href="../../pdffiles/committe.pdf">Program Committee</a><br>
<a href="../../pdffiles/reviewer.pdf">Reviewers</a><p>
</b>
<hr>
<h2>Session 1A: <a href="glsvabs.htm#sess1a" NAME="sess1a">
High-level Synthesis and Special Purpose Architecture I
</a></h2>
<dl>
<dt>
<a href="glsvabs.htm#002"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/glsvlsi96_002.pdf"><img src="../../../../../icons/pdficon.gif"></a>
Loop-List Scheduling for Heterogeneous Functional Units [p. 2]
<dd><i>
Yun-Nan Chang, Ching- Yi Wang, and Keshab K. Parhi
</i><p>
<dt>
<a href="glsvabs.htm#008"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/glsvlsi96_008.pdf"><img src="../../../../../icons/pdficon.gif"></a>
Synthesis of Real-Time Recursive DSP Algorithms Using Multiple Chips [p. 8]
<dd><i>
Duen-Jeng Wang, Yu Hen Hu
</i><p>
<dt>
<a href="glsvabs.htm#014"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/glsvlsi96_014.pdf"><img src="../../../../../icons/pdficon.gif"></a>
Resource-Constrained Algebraic Transformation for Loop Pipelining [p. 14]
<dd><i>
Jian-Feng Shi, Liang-Fang Chao
</i><p>
<dt>
<a href="glsvabs.htm#018"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/glsvlsi96_018.pdf"><img src="../../../../../icons/pdficon.gif"></a>
A Global Mode Instruction Minimization Technique for Embedded DSPRs [p. 18]
<dd><i>
Thomas Charles Wilson, Gary William Grewal
</i><p>
</dl>
<hr>
<h2>Session 1B: <a href="glsvabs.htm#sess1b" NAME="sess1b">
Circuit Design and FPGA Architecture II
</a></h2>
<dl>
<dt>
<a href="glsvabs.htm#024"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/glsvlsi96_024.pdf"><img src="../../../../../icons/pdficon.gif"></a>
A 1.Ons 64-bits GaAs Adder using Quad-Tree Algorithm [p. 24]
<dd><i>
Philippe ROYANNEZ, Amara AMARA
</i><p>
<dt>
<a href="glsvabs.htm#029"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/glsvlsi96_029.pdf"><img src="../../../../../icons/pdficon.gif"></a>
FPGA-Based High Performance Page Layout Segmentation [p. 29]
<dd><i>
Nalini K. Ratha, Anil K. Jain, Diane T. Rover
</i><p>
<dt>
<a href="glsvabs.htm#035"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/glsvlsi96_035.pdf"><img src="../../../../../icons/pdficon.gif"></a>
A Reprogrammable FPGA-Based ATM Traffic Generator [p. 35]
<dd><i>
Pong P. Chu and Brian Frantz
</i><p>
<dt>
<a href="glsvabs.htm#039"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/glsvlsi96_039.pdf"><img src="../../../../../icons/pdficon.gif"></a>
Software Fault Tolerance Using Dynamically Reconfigurable FPGAs [p. 39]
<dd><i>
Kevin A. Kwiat Warren H. Debany Jr., Salim Hariri
</i><p>
</dl>
<hr>
<h2>Session 2A: <a href="glsvabs.htm#sess2a" NAME="sess2a">
Physical Design I
</a></h2>
<dl>
<dt>
<a href="glsvabs.htm#044"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/glsvlsi96_044.pdf"><img src="../../../../../icons/pdficon.gif"></a>
A New Faster Algorithm for Iterative Placement Improvement [p. 44]
<dd><i>
Moazzem Hossain, Bala Thumma, Sunil Ashtaputre
</i><p>
<dt>
<a href="glsvabs.htm#050"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/glsvlsi96_050.pdf"><img src="../../../../../icons/pdficon.gif"></a>
An Accurate Interconnection Length Estimation for Computer Logic [p. 50]
<dd><i>
Dirk Stroobandt, Herwig Van Marck, Jan Van Campenhout
</i><p>
<dt>
<a href="glsvabs.htm#056"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/glsvlsi96_056.pdf"><img src="../../../../../icons/pdficon.gif"></a>
A Minimum-Area Floorplanning Algorithm for Mixed Block and Cell Designs [p. 56]
<dd><i>
Dinesh P. Mehta, Naveed Sherwani
</i><p>
<dt>
<a href="glsvabs.htm#060"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/glsvlsi96_060.pdf"><img src="../../../../../icons/pdficon.gif"></a>
A New Model for General Connectivity and its Application to Placement [p. 60]
<dd><i>
Jianjian Song, Heng Kek Choo, Wenjun Zhuang
</i><p>
</dl>
<hr>
<h2>Session 2B: <a href="glsvabs.htm#sess2b" NAME="sess2b">
High-level Synthesis and Special Purpose Architecture II
</a></h2>
<dl>
<dt>
<a href="glsvabs.htm#066"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/glsvlsi96_066.pdf"><img src="../../../../../icons/pdficon.gif"></a>
A Parameterized Index-Generator for the Multi-Dimensional
Interleaving Optimization [p. 66]
<dd><i>
Nelson Luiz Passos, Edwin Hsing-Mean Sha
</i><p>
<dt>
<a href="glsvabs.htm#072"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/glsvlsi96_072.pdf"><img src="../../../../../icons/pdficon.gif"></a>
A High Speed VLSI Architecture for Scaleable ATM Switches [p. 72]
<dd><i>
Paul Shipley, Sherif Sayed, Magdy Bayoumi
</i><p>
<dt>
<a href="glsvabs.htm#077"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/glsvlsi96_077.pdf"><img src="../../../../../icons/pdficon.gif"></a>
A Design Exploration Environment [p. 77]
<dd><i>
J. Wilberg, A. Kuth, H.-T. Vierhaus, R. Camposano, W. Rosenstiel
</i><p>
<dt>
<a href="glsvabs.htm#081"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/glsvlsi96_081.pdf"><img src="../../../../../icons/pdficon.gif"></a>
A Parametrical Architecture for Reed-Solomon Decoders [p. 81]
<dd><i>
Mariana-Eugenia Petre, Guido Masera
</i><p>
</dl>
<hr>
<h2>Session 3A: <a href="glsvabs.htm#sess3a" NAME="sess3a">
Physical Design II
</a></h2>
<dl>
<dt>
<a href="glsvabs.htm#086"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/glsvlsi96_086.pdf"><img src="../../../../../icons/pdficon.gif"></a>
A Provably Good Moat Routing Algorithm [p. 86]
<dd><i>
Joseph L. Ganley, James P. Cohoon
</i><p>
<dt>
<a href="glsvabs.htm#092"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/glsvlsi96_092.pdf"><img src="../../../../../icons/pdficon.gif"></a>
On Locally Optimal Breaking of Complex Cyclic Vertical Constraints in
VLSI Channel Routing [p. 92]
<dd><i>
Anthony D. Johnson
</i><p>
<dt>
<a href="glsvabs.htm#096"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/glsvlsi96_096.pdf"><img src="../../../../../icons/pdficon.gif"></a>
Chip Pad Migration is a Key Component to High Performance MCM Design [p. 96]
<dd><i>
James Loy, Atul Garg, Mukkai Krishnamoorthy, John McDonald
</i><p>
<dt>
<a href="glsvabs.htm#100"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/glsvlsi96_100.pdf"><img src="../../../../../icons/pdficon.gif"></a>
An Optimal ILP Formulation for Minimizing the Number of Feedthrough Cells in
Standard Cell Placement [p. 100]
<dd><i>
Jin-Tai Yan
</i><p>
<dt>
<dd><i>
</i><p>
Breaking Non-Disjoint Cycles with Vertical Constraints (paper not received at press time)
Lin, Chen, Xie
</dl>
<hr>
<h2>Session 3B: <a href="glsvabs.htm#sess3b" NAME="sess3b">
Synthesis and Verification I
</a></h2>
<dl>
<dt>
<a href="glsvabs.htm#106"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/glsvlsi96_106.pdf"><img src="../../../../../icons/pdficon.gif"></a>
Formal Verification of an ATM Switch Fabric Using Multiway Decision Graphs [p. 106]
<dd><i>
Sofiène Tahar, Zijian Zhou, Xiaoyu Song, Eduard Cerny and Michel Langevin
</i><p>
<dt>
<a href="glsvabs.htm#112"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/glsvlsi96_112.pdf"><img src="../../../../../icons/pdficon.gif"></a>
Boolean Function Representation Using Parallel-Access Diagrams [p. 112]
<dd><i>
Valeria Bertacco and Maurizio Damiani
</i><p>
<dt>
<a href="glsvabs.htm#118"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/glsvlsi96_118.pdf"><img src="../../../../../icons/pdficon.gif"></a>
Logic Synthesis for Testability [p. 118]
<dd><i>
Chien-Chung Tsai, Malgorzata Marek-Sadowska
</i><p>
<dt>
<a href="glsvabs.htm#122"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/glsvlsi96_122.pdf"><img src="../../../../../icons/pdficon.gif"></a>
Self-Timed Mesochronous Interconnection for High-Speed VLSI Systems [p. 122]
<dd><i>
Seokjin Kim and Ramalingam Sridhar
</i><p>
<dt>
<a href="glsvabs.htm#126"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/glsvlsi96_126.pdf"><img src="../../../../../icons/pdficon.gif"></a>
Least Upper Bounds on the Sizes of Symmetric Variable Order Based OBDDs [p. 126]
<dd><i>
Laura Litan, Paul Molitor, Dirk Möller
</i><p>
</dl>
<hr>
<h2>Session 4A: <a href="glsvabs.htm#sess4a" NAME="sess4a">
Special Session on Issues in Performance Driven Layout
</a></h2>
<dl>
<dt>
<a href="glsvabs.htm#132"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/glsvlsi96_132.pdf"><img src="../../../../../icons/pdficon.gif"></a>
Performance-Driven Interconnect Global Routing [p. 132]
<dd><i>
Dongsheng Wang, Ernest S. Kuh
</i><p>
<dt>
<a href="glsvabs.htm#137"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/glsvlsi96_137.pdf"><img src="../../../../../icons/pdficon.gif"></a>
Recent Developments in Performance Driven Steiner Routing: An Overview [p. 137]
<dd><i>
Manjit Borah, Robert Michael Owens, Mary Jane Irwin
</i><p>
<dt>
<a href="glsvabs.htm#143"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/glsvlsi96_143.pdf"><img src="../../../../../icons/pdficon.gif"></a>
Clock Buffer Placement Algorithm for Wire-Delay-Dominated Timing Model [p. 143]
<dd><i>
Masato Edahiro, Richard J. Lipton
</i><p>
<dt>
<a href="glsvabs.htm#148"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/glsvlsi96_148.pdf"><img src="../../../../../icons/pdficon.gif"></a>
Simultaneous Routing and Buffer Insertion for High Performance Interconnect [p. 148]
<dd><i>
John Lillis, Chung-Kuan Cheng, Ting-Ting Y. Lin,
</i><p>
<dt>
<a href="glsvabs.htm#154"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/glsvlsi96_154.pdf"><img src="../../../../../icons/pdficon.gif"></a>
Timing and Power Optimization by Gate Sizing Considering False Path [p. 154]
<dd><i>
Guangqiu Chen, Hidetoshi Onodera, Keikichi Tamaru
</i><p>
</dl>
<hr>
<h2>Session 4B: <a href="glsvabs.htm#sess4b" NAME="sess4b">
Low Power Design
</a></h2>
<dl>
<dt>
<a href="glsvabs.htm#162"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/glsvlsi96_162.pdf"><img src="../../../../../icons/pdficon.gif"></a>
Exact Computation of the Entropy of a Logic Circuit [p. 162]
<dd><i>
Enrico Macii, Massirno Poncino
</i><p>
<dt>
<a href="glsvabs.htm#168"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/glsvlsi96_168.pdf"><img src="../../../../../icons/pdficon.gif"></a>
CMOS Transistor Sizing for Minimization of Energy-Delay Product [p. 168]
<dd><i>
Christophe Tretz and Charles Zukowski
</i><p>
<dt>
<a href="glsvabs.htm#174"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/glsvlsi96_174.pdf"><img src="../../../../../icons/pdficon.gif"></a>
Low-Power Implementation of Discrete Cosine Transform [p. 174]
<dd><i>
Emad N. Farag and Mohamed I. Elmasry
</i><p>
<dt>
<a href="glsvabs.htm#178"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/glsvlsi96_178.pdf"><img src="../../../../../icons/pdficon.gif"></a>
Some Issues in Gray Code Addressing [p. 178]
<dd><i>
Huzefa Mehta, Robert Michael Owens, Mary Jane Irwin
</i><p>
<dt>
<a href="glsvabs.htm#182"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/glsvlsi96_182.pdf"><img src="../../../../../icons/pdficon.gif"></a>
A Hierarchical Approach for Power Reduction in VLSI Chips [p. 182]
<dd><i>
Prakash Arunachalam, Jacob Abraham, Manuel d'Abreu
</i><p>
</dl>
<hr>
<h2>Session 5A: <a href="glsvabs.htm#sess5a" NAME="sess5a">
Physical Design III
</a></h2>
<dl>
<dt>
<a href="glsvabs.htm#188"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/glsvlsi96_188.pdf"><img src="../../../../../icons/pdficon.gif"></a>
TROY: A Tree-Based Approach to Logic Synthesis and Technology Mapping [p. 188]
<dd><i>
Winfried Nöth, Uwe Hinsberger and Reiner Kolla
</i><p>
<dt>
<a href="glsvabs.htm#194"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/glsvlsi96_194.pdf"><img src="../../../../../icons/pdficon.gif"></a>
Transistor Chaining in CMOS Leaf Cells of Planar Topology [p. 194]
<dd><i>
Bradley S. Carlson, C.Y. Roger Chen and Dikran S. Meliksetian
</i><p>
<dt>
<a href="glsvabs.htm#200"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/glsvlsi96_200.pdf"><img src="../../../../../icons/pdficon.gif"></a>
Partitioning Algorithms for Corner Stitching [p. 200]
<dd><i>
Mario A. Lopez, Dinesh P. Mehta
</i><p>
</dl>
<hr>
<h2>Session 5B: <a href="glsvabs.htm#sess5b" NAME="sess5b">
Testing I
</a></h2>
<dl>
<dt>
<a href="glsvabs.htm#208"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/glsvlsi96_208.pdf"><img src="../../../../../icons/pdficon.gif"></a>
Test Generation for Networks of Interacting FSMs Using Symbolic Techniques [p. 208]
<dd><i>
F. Ferrandi, F. Fummi, E. Macii, M. Poncino, D. Sciuto
</i><p>
<dt>
<a href="glsvabs.htm#214"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/glsvlsi96_214.pdf"><img src="../../../../../icons/pdficon.gif"></a>
Input Pattern Classification for Transistor Level Testing of Bridging
Faults in BiCMOS Circuits [p. 214]
<dd><i>
Sankaran M. Menon, Anura P. Jayasumana, Yashwant K. Malaiya
</i><p>
<dt>
<a href="glsvabs.htm#220"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/glsvlsi96_220.pdf"><img src="../../../../../icons/pdficon.gif"></a>
Efficient Delay Test Generation for Modular Circuits [p. 220]
<dd><i>
C.P. Ravikumar, Nitin Agrawal and Parul Agarwal
</i><p>
</dl>
<hr>
<h2>Session 6A: <a href="glsvabs.htm#sess6a" NAME="sess6a">
High-level Synthesis and Special Purpose Architecture III
</a></h2>
<dl>
<dt>
<a href="glsvabs.htm#228"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/glsvlsi96_228.pdf"><img src="../../../../../icons/pdficon.gif"></a>
Design and VLSI Implementation of a Unified Synapse-Neuron Architecture [p. 228]
<dd><i>
H. Djahanshahi, M. Ahmadi, C. Jullien, W. Miller
</i><p>
<dt>
<a href="glsvabs.htm#234"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/glsvlsi96_234.pdf"><img src="../../../../../icons/pdficon.gif"></a>
Rapid Prototyping for Fuzzy Systems [p. 234]
<dd><i>
Chantana Chantrapornchai, Sissades Tongsima, Edwin H.-M. Sha
</i><p>
<dt>
<a href="glsvabs.htm#240"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/glsvlsi96_240.pdf"><img src="../../../../../icons/pdficon.gif"></a>
A Modular Architecture for Real Time HDTV Motion Estimation with
Large Search Range [p. 240]
<dd><i>
Hangu Yeo and Yu Hen Hu
</i><p>
</dl>
<hr>
<h2>Session 6B: <a href="glsvabs.htm#sess6b" NAME="sess6b">
Circuit Design II
</a></h2>
<dl>
<dt>
<a href="glsvabs.htm#246"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/glsvlsi96_246.pdf"><img src="../../../../../icons/pdficon.gif"></a>
A VLSI Interconnection Network Router Using a D-CAM with Hidden Refresh [p. 246]
<dd><i>
José G. Delgado-Frias, Jabulani Nyathi, Chester L. Miller, Douglas H. Summerville
</i><p>
<dt>
<a href="glsvabs.htm#252"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/glsvlsi96_252.pdf"><img src="../../../../../icons/pdficon.gif"></a>
A High-Speed, Real-to-Quadrature Converter with Filtering and Decimation [p. 252]
<dd><i>
L. Desormeaux, V. Szwarc, and J. Lodge
</i><p>
<dt>
<a href="glsvabs.htm#256"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/glsvlsi96_256.pdf"><img src="../../../../../icons/pdficon.gif"></a>
A CMOS VLSI Implementation of an NxN Multiplexing Circuitry for
ATM Applications [p. 256]
<dd><i>
Maher E. Rizkalla, Richard L. Aldridge, Nadeem A. Khan, and Harry C. Gundrum
</i><p>
<dt>
<a href="glsvabs.htm#260"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/glsvlsi96_260.pdf"><img src="../../../../../icons/pdficon.gif"></a>
A 3V-5OMHz Analog CMOS Current-Mode High Frequency Filter with a
Negative Resistance Load [p. 260]
<dd><i>
Jai-Sop Hyun and Kwang Sub Yoon
</i><p>
</dl>
<hr>
<h2>Session 7A: <a href="glsvabs.htm#sess7a" NAME="sess7a">
Synthesis and Verification II
</a></h2>
<dl>
<dt>
<a href="glsvabs.htm#266"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/glsvlsi96_266.pdf"><img src="../../../../../icons/pdficon.gif"></a>
Delay Hazards in Complex Gate Based Speed Independent VLSI Circuits [p. 266]
<dd><i>
Nozar Tabrizi, Michael J. Liebelt, Kamran Eshraghian
</i><p>
<dt>
<a href="glsvabs.htm#272"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/glsvlsi96_272.pdf"><img src="../../../../../icons/pdficon.gif"></a>
Macromodeling C- and RC-loaded CMOS Inverters for Timing Analysis [p. 272]
<dd><i>
Ayman Kayssi
</i><p>
<dt>
<a href="glsvabs.htm#277"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/glsvlsi96_277.pdf"><img src="../../../../../icons/pdficon.gif"></a>
On Verifying the Correctness of Retimed Circuits [p. 277]
<dd><i>
Shi-Yu Huang, Kwang-Ting Cheng, Kuang-Chien Chen
</i><p>
</dl>
<hr>
<h2>Session 7B: <a href="glsvabs.htm#sess7b" NAME="sess7b">
Testing II
</a></h2>
<dl>
<dt>
<a href="glsvabs.htm#282"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/glsvlsi96_282.pdf"><img src="../../../../../icons/pdficon.gif"></a>
On Double Transition Faults as a Delay Fault Model [p. 282]
<dd><i>
Irith Pomeranz, Sudhakar M. Reddy, Janak H, Patel
</i><p>
<dt>
<a href="glsvabs.htm#288"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/glsvlsi96_288.pdf"><img src="../../../../../icons/pdficon.gif"></a>
Improving Circuit Testability by Clock Control [p. 288]
<dd><i>
Kent L. Einspahr, Sharad C. Seth, Vishwani D. Agrawal
</i><p>
<dt>
<a href="glsvabs.htm#294"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/glsvlsi96_294.pdf"><img src="../../../../../icons/pdficon.gif"></a>
An Efficient Multiple Scan Chain Testing Scheme [p. 294]
<dd><i>
Zaifu Zhang and Robert D. McLeod
</i><p>
</dl>
]]>