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FPGA 1994 :
[ <a href="fpgaabs.htm">Abstracts</a> ]
[ <a href="fpgasess.htm">Session Index</a> ]
[ <a href="fpgaai.htm">Author Index</a> ]</H3>
<hr>
<h2>FPGA 1994 TABLE OF CONTENTS</h2>
<b>
Sessions:
[<a href="#sess1">1</a>]
[<a href="#poster1">Posters</a>]
[<a href="#sess2">2</a>]
[<a href="#poster2">Posters</a>]
[<a href="#sess3">3</a>]
[<a href="#poster3">Posters</a>]
[<a href="#sess4">4</a>]
[<a href="#poster4">Posters</a>]
[<a href="#panel">Panel</a>]
[<a href="#sess5">5</a>]
[<a href="#poster5">Posters</a>]
[<a href="#sess6">6</a>]
[<a href="#poster6">Posters</a>]
[<a href="#sess7">7</a>]
[<a href="#poster7">Posters</a>]
[<a href="#sess8">8</a>]
[<a href="#poster8">Posters</a>]<p>
<a href="../../pdffiles/message.pdf">Message from the Symposium Chairs</a><br>
<a href="../../pdffiles/symcomm.pdf">Symposium Committee</a><br>
<a href="../../pdffiles/referees.pdf">Referees</a><p>
</b>
<hr>
<h2>Session 1: <a href="fpgaabs.htm#sess1" NAME="sess1">
Field-Programmable Systems
</a></h2>
Chair: Chi-Ping Hsu, Quickturn Design Systems
<dl>
<dt>
<a href="fpgaabs.htm#1_1"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/fpga94_1_1.pdf"><img src="../../../../../icons/pdficon.gif"></a>
High-Speed Emulation of Communication Circuits on a Multiple-FPGA System
<dd><i>
K. Yamada, Hiroshi Nakada,
A. Tsutsui, and Naohisa Ohta, NTT, Japan
</i><p>
<dt>
<a href="fpgaabs.htm#1_2"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/fpga94_1_2.pdf"><img src="../../../../../icons/pdficon.gif"></a>
The Virtual Wire Emulation System: A Gate-Efficient ASIC Prototyping Environment
<dd><i>
R. Tessier, J. Babb, M. Dahl, S. Hanono, A. Agarwal, MIT
</i><p>
<dt>
<a href="fpgaabs.htm#1_3"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/fpga94_1_3.pdf"><img src="../../../../../icons/pdficon.gif"></a>
A Fast-FPGA Prototyping System that Uses Inexpensive High-Performance FPIC
<dd><i>
D. Brasen, M. Slimane-Kadi, G. Saucier, Institut National Polytechnique de Grenoble/CSI
</i><p>
</dl>
<hr>
<h2><a href="fpgaabs.htm#poster1" NAME="poster1">
Posters
</a></h2>
<dl>
<dt>
<a href="fpgaabs.htm#1_p1"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/fpga94_1_p1.pdf"><img src="../../../../../icons/pdficon.gif"></a>
Springbok: A Rapid-Prototyping System for Board-Level Designs
<dd><i>
S. Hauck, G. Borriello, C. Ebeling, University of Washington
</i><p>
<dt>
<a href="fpgaabs.htm#1_p2"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/fpga94_1_p2.pdf"><img src="../../../../../icons/pdficon.gif"></a>
Improved Multiple-Way Circuit Partitioning Algorithms
<dd><i>
A. Dasdan, C. Aykanat, Bilkent University, Turkey
</i><p>
<dt>
<a href="fpgaabs.htm#1_p3"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/fpga94_1_p3.pdf"><img src="../../../../../icons/pdficon.gif"></a>
FPGA Package Partitioning for Performance
<dd><i>
D. Brasen, G. Saucier, Institut National Polytechnique de Grenoble/CSI
</i><p>
</dl>
<hr>
<h2>Session 2: <a href="fpgaabs.htm#sess2" NAME="sess2">
FPGA Architecture
</a></h2>
Chair: Jonathan Rose, University of Totonto
<dl>
<dt>
<a href="fpgaabs.htm#2_1"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/fpga94_2_1.pdf"><img src="../../../../../icons/pdficon.gif"></a>
Routing Architecture for Hierarchical Field Programmable Gate Arrays
<dd><i>
A. Agarwal, D. Lewis, University of Toronto
</i><p>
<dt>
<a href="fpgaabs.htm#2_2"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/fpga94_2_2.pdf"><img src="../../../../../icons/pdficon.gif"></a>
An Effective Hardware/Software Solution for Fine Grained Architectures
<dd><i>
G.J. Jones, D.M. Wedgwood, Pilkington Microelectronics Ltd., England
</i><p>
<dt>
<a href="fpgaabs.htm#2_3"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/fpga94_2_3.pdf"><img src="../../../../../icons/pdficon.gif"></a>
A Datapath Oriented Architectures for FPGAs
<dd><i>
D. Cherepacha, D. Lewis, University of Toronto
</i><p>
</dl>
<hr>
<h2><a href="fpgaabs.htm#poster2" NAME="poster2">
Posters
</a></h2>
<dl>
<dt>
<a href="fpgaabs.htm#2_p1"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/fpga94_2_p1.pdf"><img src="../../../../../icons/pdficon.gif"></a>
Reduced Look Up Tables with Increased Functionality
<dd><i>
K. Gudger
</i><p>
<dt>
<a href="fpgaabs.htm#2_p2"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/fpga94_2_p2.pdf"><img src="../../../../../icons/pdficon.gif"></a>
Binary Decision Diagram Oriented FPGAs
<dd><i>
A. Stauffer, P. Marchal, Swiss Federal Institute of Technology
</i><p>
</dl>
<hr>
<h2>Session 3: <a href="fpgaabs.htm#sess3" NAME="sess3">
Technology Mapping I
</a></h2>
Chair: Jason Cong, UCLA
<dl>
<dt>
<a href="fpgaabs.htm#3_1"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/fpga94_3_1.pdf"><img src="../../../../../icons/pdficon.gif"></a>
Performance Driven Technology Mapping for Lookup-Table Based FPGAs Using the
General Delay Model
<dd><i>
A. Mathur, C.L. Liu, University of Illinois, Urbana-Champaign
</i><p>
<dt>
<a href="fpgaabs.htm#3_2"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/fpga94_3_2.pdf"><img src="../../../../../icons/pdficon.gif"></a>
Technology Mapping for Heterogeneous FPGAs
<dd><i>
J. He, J. Rose, University of Toronto
</i><p>
<dt>
<a href="fpgaabs.htm#3_3"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/fpga94_3_3.pdf"><img src="../../../../../icons/pdficon.gif"></a>
Functional Decision Diagrams for Technology Mapping to Lookup-Table FPGA
<dd><i>
E. Schubert, U. Kebschull, W. Rosenstiel, Universitat Tubingen, Germany
</i><p>
</dl>
<hr>
<h2><a href="fpgaabs.htm#poster3" NAME="poster3">
Posters
</a></h2>
<dl>
<dt>
<a href="fpgaabs.htm#3_p1"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/fpga94_3_p1.pdf"><img src="../../../../../icons/pdficon.gif"></a>
An Efficient Graph-Based Technology Mapping Algorithm for FPGAs Using Lookup
Tables
<dd><i>
B. Kapoor, Texas Instruments, Dallas
</i><p>
<dt>
<a href="fpgaabs.htm#3_p2"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/fpga94_3_p2.pdf"><img src="../../../../../icons/pdficon.gif"></a>
Logic Module Independent Mapping for Table-Lookup FPGAs
<dd><i>
U. Weinmann, W. Rosenstiel, Forschungszetrum Informatik an der Universitat Karlsruhe
</i><p>
<dt>
<a href="fpgaabs.htm#3_p3"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/fpga94_3_p3.pdf"><img src="../../../../../icons/pdficon.gif"></a>
Use of Binary Decision Diagrams for FPGA Mapping
<dd><i>
T. Besson, V.V. Le, S. Tixier, S. Saucier, Instit National Polytechnique de Grenoble
</i><p>
<dt>
<a href="fpgaabs.htm#3_p4"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/fpga94_3_p4.pdf"><img src="../../../../../icons/pdficon.gif"></a>
State Assignment Selection for FPGAs and CPLDs
<dd><i>
H. Belhadj, A. Fortas, G. Saucier, Instit National Polytechnique de Grenoble
</i><p>
<dt>
<a href="fpgaabs.htm#3_p5"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/fpga94_3_p5.pdf"><img src="../../../../../icons/pdficon.gif"></a>
On the Lookup-Table Minimization Problem for FPGA Technology Mapping
<dd><i>
A. Farrahi, M. Sarrafzadeh, Northwestern University
</i><p>
</dl>
<hr>
<h2>Session 4: <a href="fpgaabs.htm#sess4" NAME="sess4">
Field-Programmable Analog Arrays and Yield-Enhancement
</a></h2>
Chair: Bahram Ahanin, Altera
<dl>
<dt>
<a href="fpgaabs.htm#4_1"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/fpga94_4_1.pdf"><img src="../../../../../icons/pdficon.gif"></a>
MOS Transconductor-Based Field-Programmable Analog Array
<dd><i>
G. Gulak, E. Lee, University of Toronto
</i><p>
<dt>
<a href="fpgaabs.htm#4_2"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/fpga94_4_2.pdf"><img src="../../../../../icons/pdficon.gif"></a>
High Speed Field Programmable Analog Array Architecture Design
<dd><i>
E. Pierzchala, M. Perkowski, Portland State University
</i><p>
<dt>
<a href="fpgaabs.htm#4_3"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/fpga94_4_3.pdf"><img src="../../../../../icons/pdficon.gif"></a>
A Novel Approach to Defect Tolerant Design for SRAM Based FPGAs
<dd><i>
J.L. Kelly, P.A. Ivey, University of Sheffield, England
</i><p>
</dl>
<hr>
<h2><a href="fpgaabs.htm#poster4" NAME="poster4">
Posters
</a></h2>
<dl>
<dt>
<a href="fpgaabs.htm#4_p1"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/fpga94_4_p1.pdf"><img src="../../../../../icons/pdficon.gif"></a>
FPGAs with Self Repair Capabilities
<dd><i>
S. Durand, C. Piguet, Swiss Fed. Inst. of Tech.
</i><p>
</dl>
<hr>
<h2><a href="fpgaabs.htm#panel" NAME="panel">
Panel: Open, Closed Untouched, Irrelevant and Unprofitable:
Questions Worth Pursuing in FPGAs
</a></h2>
<dl>
<dt>
<a href="../../pdffiles/fpga94_panel.pdf"><img src="../../../../../icons/pdficon.gif"></a>
</dl>
<hr>
<h2>Session 5: <a href="fpgaabs.htm#sess5" NAME="sess5">
FPGA-Based Computing Architectures and Paradigms
</a></h2>
Chair: Duncan Buell, Supercomputing Research Centre
<dl>
<dt>
<a href="fpgaabs.htm#5_1"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/fpga94_5_1.pdf"><img src="../../../../../icons/pdficon.gif"></a>
Mesh Routing Topologies for FPGA Arrays
<dd><i>
S. Hauck, G. Borriello, C. Ebeling, University of Washington
</i><p>
<dt>
<a href="fpgaabs.htm#5_2"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/fpga94_5_2.pdf"><img src="../../../../../icons/pdficon.gif"></a>
Programming the Hawaii Parallel Computer
<dd><i>
A. Lew, R. Halverson Jr., University of Hawaii
</i><p>
<dt>
<a href="fpgaabs.htm#5_3"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/fpga94_5_3.pdf"><img src="../../../../../icons/pdficon.gif"></a>
Unifying FPGAs and SIMD Arrays
<dd><i>
M. Bolotski, A. Dellon, T. Knight Jr., MIT
</i><p>
</dl>
<hr>
<h2><a href="fpgaabs.htm#poster5" NAME="poster5">
Posters : Placement and Routing
</a></h2>
Chair: David Marple, Crosspoint
<dl>
<dt>
<a href="fpgaabs.htm#5_p1"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/fpga94_5_p1.pdf"><img src="../../../../../icons/pdficon.gif"></a>
Algorithms for FPGA Switch Module Routing
<dd><i>
M.D.F. Wong, S. Thakur, S. Muthukrishnan, The University of Texas at Austin
</i><p>
<dt>
<a href="fpgaabs.htm#5_p2"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/fpga94_5_p2.pdf"><img src="../../../../../icons/pdficon.gif"></a>
On Minimizing Clock Skew During FPGA Placement
<dd><i>
M.D.F. Wong, K. Zhu, The University of Texas at Austin
</i><p>
<dt>
<a href="fpgaabs.htm#5_p3"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/fpga94_5_p3.pdf"><img src="../../../../../icons/pdficon.gif"></a>
Switch Bound Allocation in Timing-Driven Routing of FPGAs
<dd><i>
M.D.F. Wong, K. Zhu, The University of Texas at Austin
</i><p>
</dl>
<hr>
<h2>Session 6: <a href="fpgaabs.htm#sess6" NAME="sess6">
Applications of FPGAs
</a></h2>
Chair: Stephen Trimberger, Xilinx Inc.
<dl>
<dt>
<a href="fpgaabs.htm#6_1"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/fpga94_6_1.pdf"><img src="../../../../../icons/pdficon.gif"></a>
A Field-Programmable Gate Array Implementation of a Self-Adapting and Scalable
Connectionist Network
<dd><i>
A. Ferrucci, M. Martin, T. Geocaris, M. Schlag, P.K. Chan, University of
California, Santa Cruz
</i><p>
<dt>
<a href="fpgaabs.htm#6_2"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/fpga94_6_2.pdf"><img src="../../../../../icons/pdficon.gif"></a>
Taking Advantage of Reconfigurable Logic
<dd><i>
B.K. Fawcett, Xilinx Inc.
</i><p>
<dt>
<a href="fpgaabs.htm#6_3"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/fpga94_6_3.pdf"><img src="../../../../../icons/pdficon.gif"></a>
A Variable Precision Multiplier for Field Programmable Gate Arrays
<dd><i>
M. Louie, M. Ercegovac, University of California, Los Angeles
</i><p>
</dl>
<hr>
<h2><a href="fpgaabs.htm#poster6" NAME="poster6">
Posters
</a></h2>
<dl>
<dt>
<a href="fpgaabs.htm#6_p1"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/fpga94_6_p1.pdf"><img src="../../../../../icons/pdficon.gif"></a>
Space Efficient Neural Net Implementation
<dd><i>
M. Gshwind, V. Salapura, O. Maischberer, Technische Universitat Wien
</i><p>
<dt>
<a href="fpgaabs.htm#6_p2"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/fpga94_6_p2.pdf"><img src="../../../../../icons/pdficon.gif"></a>
Implementation of a Local Controller for the Reconfigurable Machine Using the
Xilinx's 4005 FPGA
<dd><i>
S.S. Erdogan, N. Kuo, A. Wahab, Nanyang Technological University, Singapore
</i><p>
</dl>
<hr>
<h2>Session 7: <a href="fpgaabs.htm#sess7" NAME="sess7">
Partitioning and Technology Mapping
</a></h2>
Chair: Ewald Detfens, Exemplar
<dl>
<dt>
<a href="fpgaabs.htm#7_1"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/fpga94_7_1.pdf"><img src="../../../../../icons/pdficon.gif"></a>
Area/Pin-Constrained Circuit Clustering for Delay Minimization
<dd><i>
M.D.F. Wong, H. Yang, The University of Texas at Austin
</i><p>
<dt>
<a href="fpgaabs.htm#7_2"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/fpga94_7_2.pdf"><img src="../../../../../icons/pdficon.gif"></a>
Min-Cut Replication for Improved Partitions
<dd><i>
J. Hwang, Quickturn Design Systems & Stanford
</i><p>
<dt>
<a href="fpgaabs.htm#7_3"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/fpga94_7_3.pdf"><img src="../../../../../icons/pdficon.gif"></a>
Using Encoding for Functional Decomposition with Application to Look Up Table Architectures
<dd><i>
R. Murgai, R. Brayton, A. Sangiovanni-Vincentelli, University of California, Berkeley
</i><p>
</dl>
<hr>
<h2><a href="fpgaabs.htm#poster7" NAME="poster7">
Posters
</a></h2>
<dl>
<dt>
<a href="fpgaabs.htm#7_p1"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/fpga94_7_p1.pdf"><img src="../../../../../icons/pdficon.gif"></a>
A Technique for Synthesizing Data Part Using FPGAs
<dd><i>
M. Balakrishnan, A.R. Naseer, A. Kumar, Indian Institute of Technology Delhi, India
</i><p>
<dt>
<a href="fpgaabs.htm#7_p2"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/fpga94_7_p2.pdf"><img src="../../../../../icons/pdficon.gif"></a>
Vertex Ordering in Partitioning-Based Fitter for an Application Specific EPLD Device
<dd><i>
M. Jeske, T. Gao, A. Coppola, Portland State University
</i><p>
<dt>
<a href="fpgaabs.htm#7_p3"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/fpga94_7_p3.pdf"><img src="../../../../../icons/pdficon.gif"></a>
RTL Synthesis System Using FPGA Macro Bloc Capabilities
<dd><i>
M.C. Bertrand, A. Mignotte, O. Khalil, G. Saucier, Institut National Polytechnique
</i><p>
</dl>
<hr>
<h2>Session 8: <a href="fpgaabs.htm#sess8" NAME="sess8">
Placement, Routing and Timing Modelling
</a></h2>
Chair: Sinan Kaptanoglu, Actel
<dl>
<dt>
<a href="fpgaabs.htm#8_1"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/fpga94_8_1.pdf"><img src="../../../../../icons/pdficon.gif"></a>
A New Approach to FPGA Routing Based on Multi-Weighted Graphs
<dd><i>
G. Robins, M.J. Alexander, University of Virginia
</i><p>
<dt>
<a href="fpgaabs.htm#8_2"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/fpga94_8_2.pdf"><img src="../../../../../icons/pdficon.gif"></a>
A Simultaneous Placement and Global Routing Algorithm for Symmetric FPGAs
<dd><i>
N. Togawa, M. Sato, T. Ohtsuki, Waseda Univeristy
</i><p>
<dt>
<a href="fpgaabs.htm#8_3"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/fpga94_8_3.pdf"><img src="../../../../../icons/pdficon.gif"></a>
Fast Delay Estimation in Segmented Channel FPGAs
<dd><i>
M. Chew, J-C. Lien, Actel Corp.
</i><p>
</dl>
<hr>
<h2><a href="fpgaabs.htm#poster8" NAME="poster8">
Posters
</a></h2>
<dl>
<dt>
<a href="fpgaabs.htm#8_p1"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/fpga94_8_p1.pdf"><img src="../../../../../icons/pdficon.gif"></a>
Timing Modelling for Antifuse Based FPGAs
<dd><i>
N.S. Nagaraj, P. Krivacek, M. Harward, Texas Instruments Inc., India
</i><p>
<dt>
<a href="fpgaabs.htm#8_p2"><img src="../../../../../icons/absicon.gif"></a>
<a href="../../pdffiles/fpga94_8_p2.pdf"><img src="../../../../../icons/pdficon.gif"></a>
Computational Complexity of 2-D FPGA Routing for Arbitrary Switch Box Topologies
<dd><i>
Y-L. Wu, S. Tsukiyama, Chuo Uaniversity, Japan
</i><p>
</dl>
]]>