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The 11th Asia and South Pacific Design Automation Conference

Friday January 27, 2006

Session 7C Statistical and Yield Analysis (10:15 - 12:20)
Location: Room 414+415
Chair(s): Hiroo Masuda (STARC, Japan), Seijiro Moriyama (PDF Solutions, Japan)

7C-1 (Time: 10:15 - 10:40)
TitleStatistical Corner Conditions of Interconnect Delay (Corner LPE Specifications)
Author*Kenta Yamada, Noriaki Oda (NEC Electronics, Japan)
Pagepp. 706 - 711
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7C-2 (Time: 10:40 - 11:05)
TitleSpeed Binning Aware Design Methodology to Improve Profit under Parameter Variations
AuthorAnimesh Datta (Purdue Univ., United States), Swarup Bhunia (Case Western Reserve Univ., United States), Jung Hwan Choi, Saibal Mukhopadhyay, *Kaushik Roy (Purdue Univ., United States)
Pagepp. 712 - 717
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7C-3 (Time: 11:05 - 11:30)
TitleYield-Area Optimizations of Digital Circuits Using Non-dominated Sorting Genetic Algorithm (YOGA)
AuthorVineet Agarwal, *Janet Wang (Univ. of Arizona, United States)
Pagepp. 718 - 723
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7C-4 (Time: 11:30 - 11:55)
TitleA Probabilistic Analysis of Pipelined Global Interconnect Under Process Variations
Author*Navneeth Kankani, Vineet Agarwal, Janet M Wang (Univ. of Arizona, United States)
Pagepp. 724 - 729
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7C-5 (Time: 11:55 - 12:20)
TitleYield-Preferred Via Insertion Based on Novel Geotopological Technology
AuthorFangyi Luo (Univ. of California, Santa Cruz, United States), *Yongbo Jia (Nannor Technologies, Inc., United States), Wayne Wei-Ming Dai (Univ. of California, Santa Cruz, United States)
Pagepp. 730 - 735
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