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The 11th Asia and South Pacific Design Automation Conference

Friday January 27, 2006

Session 7A Minimization of Test Cost and Power (10:15 - 12:20)
Location: Room 411+412
Chair(s): Seiji Kajihara (Kyushu Inst. of Tech., Japan), Satoshi Ohtake (NAIST, Japan)

7A-1 (Time: 10:15 - 10:40)
TitleA Routability Constrained Scan Chain Ordering Technique for Test Power Reduction
Author*Xuan-Lun Huang, Jiun-Lang Huang (National Taiwan Univ., Taiwan)
Pagepp. 648 - 652
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7A-2 (Time: 10:40 - 11:05)
TitleFCSCAN: An Efficient Multiscan-based Test Compression Technique for Test Cost Reduction
Author*Youhua Shi, Nozomu Togawa, Shinji Kimura, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ., Japan)
Pagepp. 653 - 658
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7A-3 (Time: 11:05 - 11:30)
TitleCompaction of Pass/Fail-based Diagnostic Test Vectors for Combinational and Sequential Circuits
Author*Yoshinobu Higami (Ehime Univ., Japan), Kewal K. Saluja (Univ. of Wisconsin-Madison, United States), Hiroshi Takahashi, Shin-ya Kobayashi, Yuzo Takamatsu (Ehime Univ., Japan)
Pagepp. 659 - 664
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7A-4 (Time: 11:30 - 11:55)
TitleLow-Overhead Design of Soft-Error-Tolerant Scan Flip-Flops with Enhanced-Scan Capability
AuthorAshish Goel (Purdue Univ., United States), Swarup Bhunia (Case Western Reserve Univ., United States), Hamid Mahmoodi (San Francisco State Univ., United States), *Kaushik Roy (Purdue Univ., United States)
Pagepp. 665 - 670
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7A-5 (Time: 11:55 - 12:20)
TitleA Memory Grouping Method for Sharing Memory BIST Logic
Author*Masahide Miyazaki, Tomokazu Yoneda, Hideo Fujiwara (NAIST, Japan)
Pagepp. 671 - 676
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