| Thursday January 26, 2006 |
| Title | Reusable Component IP Design using Refinement-based Design Environment |
| Author | *Sanggyu Park, Sang-Yong Yoon, Soo-Ik Chae (Seoul National Univ., Republic of Korea) |
| Page | pp. 588 - 593 |
| Detailed information (abstract, keywords, etc) | |
| PDF file | |
| Title | An Interface-Circuit Synthesis Method with Configurable Processor Core in IP-Based SoC Designs |
| Author | *Shunitsu Kohara, Naoki Tomono, Jumpei Uchida, Yuichiro Miyaoka, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ., Japan) |
| Page | pp. 594 - 599 |
| Detailed information (abstract, keywords, etc) | |
| PDF file | |
| Title | A Real-Time and Bandwidth Guaranteed Arbitration Algorithm for SoC Bus Communication |
| Author | Chien-Hua Chen, *Geeng-Wei Lee, Juinn-Dar Huang, Jing-Yang Jou (National Chiao Tung Univ., Taiwan) |
| Page | pp. 600 - 605 |
| Detailed information (abstract, keywords, etc) | |
| PDF file | |
| Title | Hierarchical Memory Size Estimation for Loop Fusion and Loop Shifting in Data-Dominated Applications |
| Author | *Qubo Hu (Univ. of Trondheim, Norway), Arnout Vandecappelle, Martin Palkovic (IMEC, Belgium), Per Gunnar Kjeldsberg (Univ. of Trondheim, Norway), Erik Brockmeyer, Francky Catthoor (IMEC, Belgium) |
| Page | pp. 606 - 611 |
| Detailed information (abstract, keywords, etc) | |
| PDF file | |
| Title | A Novel Instruction Scratchpad Memory Optimization Method based on Concomitance Metric |
| Author | Andhi Janapsatya, Aleksandar Ignjatovic, *Sri Parameswaran (Univ. of New South Wales, Australia) |
| Page | pp. 612 - 617 |
| Detailed information (abstract, keywords, etc) | |
| PDF file | |