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The 11th Asia and South Pacific Design Automation Conference

Thursday January 26, 2006

Session 6A Power Optimization of Large-Scale Circuits (16:00 - 18:05)
Location: Room 411+412
Chair(s): Sheldon Tan (Univ. of California, Riverside, United States), David Z. Pan (Univ. of Texas, Austin, United States)

6A-1 (Time: 16:00 - 16:25)
TitleMathematically Assisted Adaptive Body Bias (ABB) for Temperature Compensation in Gigascale LSI Systems
AuthorSanjay V Kumar, Chris H Kim, *Sachin S Sapatnekar (Univ. of Minnesota, United States)
Pagepp. 559 - 564
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6A-2 (Time: 16:25 - 16:50)
TitleAnalysis and Optimization of Gate Leakage Current of Power Gating Circuits
Author*Hyung-Ock Kim, Youngsoo Shin (KAIST, Republic of Korea)
Pagepp. 565 - 569
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6A-3 (Time: 16:50 - 17:15)
TitleDelay Modeling and Static Timing Analysis for MTCMOS Circuits
Author*Naoaki Ohkubo, Kimiyoshi Usami (Shibaura Inst. of Tech., Japan)
Pagepp. 570 - 575
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6A-4 (Time: 17:15 - 17:40)
TitleSwitching-Activity Driven Gate Sizing and Vth Assignment for Low Power Design
AuthorYu-Hui Huang, *Po-Yuan Chen, TingTing Hwang (National Tsing Hua Univ., Taiwan)
Pagepp. 576 - 581
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6A-5 (Time: 17:40 - 18:05)
TitlePower Driven Placement with Layout Aware Supply Voltage Assignment for Voltage Island Generation in Dual-Vdd Designs
Author*Bin Liu, Yici Cai, Qiang Zhou, Xianlong Hong (Tsinghua Univ., China)
Pagepp. 582 - 587
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