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The 11th Asia and South Pacific Design Automation Conference

Thursday January 26, 2006

Session 5D Designers' Forum: Low Power Design (13:30 - 15:30)
Location: Small Auditorium, 5F
Chair(s): Haruyuki Tago (Toshiba, Japan), Makoto Ikeda (Univ. of Tokyo, Japan)

5D-1 (Time: 13:30 - 14:00)
TitleLow-Power Design Methodology for Module-wise Dynamic Voltage and Frequency Scaling with Dynamic De-skewing Systems
Author*Takeshi Kitahara, Hiroyuki Hara, Shinichiro Shiratake (Toshiba, Japan), Yoshiki Tsukiboshi (Toshiba Microelectronics Co., Japan), Tomoyuki Yoda, Tetsuaki Utsumi, Fumihiro Minami (Toshiba, Japan)
Pagepp. 533 - 540
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5D-2 (Time: 14:00 - 14:30)
TitleSingle-Chip Multi-Processor Integrating Quadruple 8-Way VLIW Processors with Interface Timing Analysis Considering Power Supply Noise
Author*Satoshi Imai, Atsuki Inoue, Motoaki Matsumura, Kenichi Kawasaki, Atsuhiro Suga (Fujitsu Lab., Japan)
Pagepp. 541 - 546
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5D-3 (Time: 14:30 - 15:00)
TitleA System-level Power-estimation Methodology based on IP-level Modeling, Power-level Adjustment, and Power Accumulation
Author*Masafumi Onouchi, Tetsuya Yamada (Hitachi Ltd., Japan), Kimihiro Morikawa, Isamu Mochizuki, Hidetoshi Sekine (Renesas, Japan)
Pagepp. 547 - 550
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5D-4 (Time: 15:00 - 15:30)
TitlePowerViP: SoC Power Estimation Framework at Transaction Level
Author*Ikhwan Lee, Hyunsuk Kim, Peng Yang, Sungjoo Yoo (Samsung Electronics, Republic of Korea), Eui-Young Chung (Yonsei Univ., Republic of Korea), Kyu-Myung Choi, Jeong-Taek Kong, Soo-Kwan Eo (Samsung Electronics, Republic of Korea)
Pagepp. 551 - 558
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