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The 11th Asia and South Pacific Design Automation Conference

Wednesday January 25, 2006

Session 1C Timing Analysis and Optimization (10:15 - 12:20)
Location: Room 414+415
Chair(s): Ryuichi Yamaguchi (Matsushita, Japan), Atsushi Kurokawa (STARC, Japan)

1C-1 (Time: 10:15 - 10:40)
TitleRobust Analytical Gate Delay Modeling for Low Voltage Circuits
AuthorAnand Ramalingam (Univ. of Texas, Austin, United States), Sreekumar V. Kodakara (Univ. of Minnesota, United States), Anirudh Devgan (Magma, United States), *David Z. Pan (Univ. of Texas, Austin, United States)
Pagepp. 61 - 66
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1C-2 (Time: 10:40 - 11:05)
TitleCGTA: Current Gain-based Timing Analysis for Logic Cells
AuthorShahin Nazarian, *Massoud Pedram (Univ. of Southern California, United States), Tao Lin, Emre Tuncer (Magma, United States)
Pagepp. 67 - 72
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1C-3 (Time: 11:05 - 11:30)
TitleEfficient Static Timing Analysis Using a Unified Framework for False Paths and Multi-Cycle Paths
AuthorShuo Zhou, Bo Yao, Hongyu Chen, Yi Zhu, *Chung-Kuan Cheng (Univ. of California, San Diego, United States), Mike Hutton (Altera Corp., United States)
Pagepp. 73 - 78
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1C-4 (Time: 11:30 - 11:55)
TitleCrosstalk Analysis using Reconvergence Correlation
Author*Sachin Shrivastava, Rajendra Pratap, Harindranath Parameswaran, Manuj Verma (Cadence Design Systems, India)
Pagepp. 79 - 83
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1C-5 (Time: 11:55 - 12:20)
TitleProcess-Induced Skew Reduction in Nominal Zero-Skew Clock Trees
Author*Matthew R. Guthaus, Dennis Sylvester (Univ. of Michigan, United States), Richard B. Brown (Univ. of Utah, United States)
Pagepp. 84 - 89
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