| Wednesday January 25, 2006 |
| Title | Constraint-Driven Bus Matrix Synthesis for MPSoC |
| Author | *Sudeep Pasricha, Nikil Dutt (Univ. of California, Irvine, United States), Mohamed Ben-Romdhane (Conexant, United States) |
| Page | pp. 30 - 35 |
| Detailed information (abstract, keywords, etc) | |
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| Title | Improving Routing Efficiency for Network-on-Chip through Contention-Aware Input Selection |
| Author | *Dong Wu, Bashir M. Al-Hashimi, Marcus T. Schmitz (Univ. of Southampton, Great Britain) |
| Page | pp. 36 - 41 |
| Detailed information (abstract, keywords, etc) | |
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| Title | Physical Design Implementation of Segmented Buses to Reduce Communication Energy |
| Author | *Jin Guo, Antonis Papanikolaou, Pol Marchal, Francky Catthoor (IMEC, Belgium) |
| Page | pp. 42 - 47 |
| Detailed information (abstract, keywords, etc) | |
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| Title | Co-Synthesis of a Configurable SoC Platform based on a Network on Chip Architecture |
| Author | *Mário Pereira Véstias, Horácio Neto (INESC-ID, Portugal) |
| Page | pp. 48 - 53 |
| Detailed information (abstract, keywords, etc) | |
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| Title | Customized SIMD Unit Synthesis for System on Programmable Chip - A Foundation for HW/SW Partitioning with Vectorization |
| Author | Muhammad Omer Cheema, *Omar Hammami (ENSTA Paris, France) |
| Page | pp. 54 - 60 |
| Detailed information (abstract, keywords, etc) | |
| PDF file | |