Research Projects
Embedded Systems Methodology Group
Our main focus is currently on developing new algorithms, tools, and design flows in the context of a comprehensive SoC system-level design methodology. The results of these research efforts will flow into building different tool sets that are part of the envisioned SoC design flow.
Reference:
D. Gajski, "System-Level Design Methodology," ASP-DAC 2004 Pacifico Yokohama, Yokohama, Japan, January 27, 2004.
System-on-Chip Design Environment (SCE)
Key Researchers: Lukai Cai, Haobo Yu, Dongwan Shin, Andreas Gerstlauer, and Jerry Peng.
SCE is an Interactive environment for system-level design that starts from an executable specification and ends with a cycle-accurate model of the system that composes of a variety of processors, IPs, memories and buses executing the specification in a distributed fashion. SCE allows designers to make all decisions such as selecting and connecting components, partitioning computations and communications, scheduling, etc. While SCE performs automatic transaction level model generation, simulation, verification, and exploration.
Reference:
S. Abdi, J. Peng, H. Yu, D. Shin, A. Gerstlauer, R. Doemer, and D. Gajski, "System-on-Chip Environment: SCE Version 2.2.0 Beta Tutorial," TR 03-41, December 2003.
Verification Through Model Algebra
Key Researcher: Samar Abdi
This project defines levels of abstractions in modeling systems and rules for transformation between them in the form of a model algebra. Such well-defined models and sequence of transformation between them allow verification of model equivalence which is not possible for too independently generated models of the same design.
References:
S. Abdi and D. Gajski, "System Debugging and Verification: A New Challenge," TR 03-31, October 1, 2003.
D. Gajski and S. Abdi, "System Debugging and Verification: A New Challenge," Verify 2003, Tokyo, Japan, November 20, 2003.
NISC: No-Instruction-Set-Computer
Key Researcher: Mehrdad Reshadi
NISC Demo: http://www.cecs.uci.edu/~nisc/
NISC projects unites HW and SW views of computation by defining the model that unties traditional concepts of custom HW (RTL and NISC processors) with concepts of standard processors (RISC and CISC processors).
References:
D. Gajski, "NISC: The Ultimate Reconfigurable Component," TR 03-28, October 1, 2003.
M. Reshadi and D. Gajski, "NISC Modeling and Simulation," TR 04-08, March 2004.