Select Publications

Books

Note: Due to copyright issues we are not able to provide downloads for most of the Cadlab book publications.

Books:

• D. D. Gajski, S. Abdi, A. Gerstlauer, and G. Schirner, Embedded System Design: Modeling, Synthesis, Verification, Springer, ISBN 978-1-4419-0503-1, July 2009. (slides available at: http://www.cecs.uci.edu/embedded-system-design-book
• A. Gerstlauer, R. Doemer, J. Peng, D. D. Gajski, System Design: A Practical Guide with SpecC, Kluwer Academic Publishers, Boston, MA, ISBN 0-7923-7387-1, June 2001.
• D. D. Gajski, J. Zhu, R. Doemer, A. Gerstlauer, S. Zhao, SpecC: Specification Language and Methodology, Japanese Edition, CQ Publishing, Japan, ISBN 4-7898-3353-4, December 2000, 328 pages.
• D. D. Gajski, J. Zhu, R. Doemer, A. Gerstlauer, S. Zhao, SpecC: Specification Language and Methodology, Kluwer Academic Publishers, Boston, MA, ISBN 0-7923-7822-9, March 2000, 336 pages.
• D. D. Gajski, Principles of Digital Design, Prentice Hall, Upper Saddle River, NJ, 1997, 450 pages.
• D. D. Gajski, F. Vahid, S. Narayan, J. Gong, Specification and Design of Embedded Systems, Prentice Hall, Englewood Cliffs, NJ, 1994, 450 pages. [Transparencies/Slides]
• D. D. Gajski, N. D. Dutt, Allen C-H. Wu, Steve Y-L. Lin, High-Level Synthesis: Introduction to Chip and System Design, Kluwer Academic Publishers, Boston, MA, ISBN 0-7923-9194-2, 1992, 359 pages. [Transparencies/Slides and Errata]
• D. D. Gajski, editor, Silicon Compilation, Addison-Wesley, 1988.

Book Chapters

• Yu Lo, S. Abdi, D. Gajski, "Transaction Level Model Automation for Multicore Systems" in Behavioral Modeling for Embedded Systems and Technologies (Gomes and Fernandes, eds), IGI Global, Hershey, Pennsylvania, 2009
• Daniel Gajski and Samar Abdi, "Transaction-Level System Modeling", in Practical Design Verification (D. K. Pradhan and I. G Harris, eds), Cambridge University Press, 2009
• Daniel D. Gajski, "System Level Design: Past, Present and Future", in Design, Automation and Test in Europe: The Most Influential papers of 10 Years DATE (Lauwereins and Madsen, eds), Springer, March 2008
• Andreas Gerstlauer, Haobo Yu, Daniel D. Gajski, "RTOS Modeling for System-Level Design," in Design, Automation, and Test in Europe: The Most Influential Papers of 10 Years DATE, edited by Rudy Lauwereins and Jan Madsen, Springer Science+Business Media, New York, NY, ISBN 978-1-4020-6487-6, March 2008.
• D. Shin, A. Gerstlauer, R. Doemer, and D. Gajski, "An Interactive Design Environment for C-Based High-Level Synthesis," in Embedded Systems Design: Topics, Techniques, and Trends (A. Rettenberg et al, eds), Springer, May 2007
• B. Gorjiara, M Reshadi, D. Gajski, "Low-Power Design with NISC Technology", in Designing Embedded Processors: A Low Power Perspective (J Henkel, S. Paramesweran, eds), Springer 2007
• D. Shin, A. Gerstlauer, R. Doemer and D. D. Gajski, "Automatic Generation of Communication Architectures," From Specification to Embedded System Application (Rettberg, Zanella, Rammig, eds.) Springer, August 2005, pp. 179-188.
• H. Yu, R. Doemer and D. D. Gajski, "Software and Driver Synthesis from Transaction level Models," Specification to Embedded System Application (Rettberg, Zanella, Rammig, eds.) Springer, 2005, pp. 65-76.
• L. Cai, M. Olivarez, P. Kritzinger, and D. D. Gajski, "C/C++ Based System Design Flow Using SpecC, VCC, and SystemC," System Specification and Design Languages, edited by E Villar, Kluwer Academic Publishers, Boston, 2003.
• A. Gerstlauer, H. Yu and D. D. Gajski, "RTOS Modeling for System-Level Design," Embedded Software for SoC, edited by A. A. Jerraya, S. Yoo, N. When, D. Verkest, Kluwer Academic Publishers, June 2003.
• L. Cai, M. Olivarez and D. D. Gajski, "The Guidelines and JPEG Encoder Study Case of Systems Level Architecture Exploration Using SpecC Methodology," System On Chip Design Languages (Mignotte, Villar, Horobin, eds.), Kluwer Academic Publishers, 2002.
• A. Rettberg, F. Rammig, A. Gerstlauer, D. D. Gajski, W. Hardt, and B. Kleinjohann, "The Specification Language SpecC within the PARADISE Design Environment," Architecture and Design of Distributed Embedded Systems, edited by B. Kleinjohann, Kluwer Academic Publishers, April 2001.

Journals

• Dongwan Shin, Andreas Gerstlauer, Rainer Doemer, Daniel D. Gajski, "An Interactive Design Environment for C-Based High-Level Synthesis of RTL Processors," IEEE Transactions on Very Large Scale Integration Systems (TVLSI), vol. 16, no. 4, pp. 466-475, April 2008.
• Andreas Gerstlauer, Dongwan Shin, Junyu Peng, Rainer Doemer, Daniel D. Gajski, "Automatic Layer-Based Generation of System-On-Chip Bus Communication Models," IEEE Transactions on Design Computer-Aided of Integrated Circuits and Systems, vol. 26, no. 9, pp. 1676-1687, September 2007.
• J. Trajkovic and D. D. Gajski, "Automatic Architecture Selection for Custom Processors," SRC Symposium, October 2006.
• R. Doemer, A. Gerstlauer, D. Gajski, "SpecC Methodology for High-Level Modeling," 9th IEEE/DATC Electronic Design Process Workshop, Monterey, Ca, April 2002.

Conferences

• Daniel D. Gajski, "High-Level Synthesis for ESL Design: Fundamentals and Case Studies", Tutorial speaker, DAC, San Francisco, Ca, July 27-31, 2009
• Daniel D. Gajski, "A System-Level Modeling, Analysis and Synthesis of Embedded Multi-Core Designs", Tutorial Organizer, DATE Conference, Nice, France, April 20-25, 2009
• Daniel D. Gajski, "The Future of ESL Synthesis", Workshop Organizer (with J. Teich and F. Schafer) and speaker, DATE Conference, Nice, France, April 20-25, 2009
• Gunar Schirner, Andreas Gerstlauer, Rainer Doemer, "Automatic Generation of Hardware dependent Software for MPSoCs from Abstract System Specifications," Proceedings of the Asia and South Pacific Design Automation Conference, Seoul, Korea, January 2008.
• Gunar Schirner, Andreas Gerstlauer, Rainer Doemer, "Abstract, Multifaceted Modeling of Embedded Processors for System Level Design," Proceedings of the Asia and South Pacific Design Automation Conference, Yokohama, Japan, January 2007.
• Dongwan Shin, Andreas Gerstlauer, Junyu Peng, Rainer Doemer, Daniel D. Gajski, "Automatic Generation of Transaction-Level Models for Rapid Design Space Exploration," Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis, Seoul, Korea, October 2006.
• Rainer Doemer, Andreas Gerstlauer, Dongwan Shin, "Cycle-accurate RTL Modeling with Multi-Cycled and Pipelined Components," Proceedings of the International SoC Design Conference, Seoul, Korea, October 2006.
• Dongwan Shin, Andreas Gerstlauer, Rainer Doemer, Daniel D. Gajski, "Automatic Network Generation for System-On-Chip Communication Design," Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis, Jersey City, NJ, September 2005.
• Andreas Gerstlauer, Dongwan Shin, Rainer Doemer, Daniel D. Gajski, "System-Level Communication Modeling for Network-On-Chip Synthesis," Proceedings of the Asia and South Pacific Design Automation Conference, Shanghai, China, January 2005.
• Lukai Cai, Andreas Gerstlauer, Daniel D. Gajski, "Multi-Metric and Multi-Entity Characterization of Applications for Early System Design Exploration," Proceedings of the Asia and South Pacific Design Automation Conference, Shanghai, China, January 2005.

Technical Reports

2007:

• Andreas Gerstlauer, Dongwan Shin, Samar Abdi, Pramod Chandraiah and Daniel D. Gajski, "Design of a MP3 Decoder using the System-On-Chip Environment (SCE)," CECS, UC Irvine, Technical Report CECS-TR-07-05, November 2007.

2006:

• Eric James Johnson, Andreas Gerstlauer and Rainer Doemer, "Efficient Debugging and Tracing of System Level Designs," CECS, UC Irvine, Technical Report CECS-TR-06-08, May 2006.
• Gunar Schirner, Gautam Sachdeva, Andreas Gerstlauer and Rainer Doemer, "Modeling, Simulation and Synthesis in an Embedded Software Design Flow for an ARM Processor," CECS, UC Irvine, Technical Report CECS-TR-06-06, May 2006.

2005:

• Daniel Gajski, Andreas Gerstlauer, Rainer Doemer, Samar Abdi, Jerry Peng and Dongwan Shin, "TL Environment," CECS, UC Irvine, Technical Report CECS-TR-05-10, July 2005.

2004:

• Dongwan Shin, Andreas Gerstlauer, Rainer Doemer and Daniel D. Gajski, "System-on-Chip Communication Modeling Style Guide," CECS, UC Irvine, Technical Report CECS-TR-04-25, July 2004.
• Dongwan Shin, Lukai Cai, Andreas Gerstlauer, Rainer Doemer and Daniel D. Gajski, "System-on-Chip Transaction-Level Modeling Style Guide," CECS, UC Irvine, Technical Report CECS-TR-04-24, July 2004.
• Dongwan Shin, Junyu Peng, Andreas Gerstlauer, Rainer Doemer and Daniel D. Gajski, "System-on-Chip Network Modeling Style Guide," CECS, UC Irvine, Technical Report CECS-TR-04-23, July 2004.
• Junyu Peng, Andreas Gerstlauer, Rainer Doemer and Daniel D. Gajski, "System-on-Chip Architecture Modeling Style Guide," CECS, UC Irvine, Technical Report CECS-TR-04-22, July 2004.
• Rainer Doemer, Andreas Gerstlauer, and Dongwan Shin, "Cycle-accurate RTL Modeling with Multi-Cycled and Pipelined Components," CECS, UC Irvine, Technical Report CECS-TR-04-19, July 2004.
• Dongwan Shin, Andreas Gerstlauer and Daniel Gajski, "Communication Link Synthesis for SoC," CECS, UC Irvine, Technical Report CECS-TR-04-16, June 2004.
• Dongwan Shin, Andreas Gerstlauer and Daniel Gajski, "Network Synthesis for SoC," CECS, UC Irvine, Technical Report CECS-TR-04-15, June 2004.
• Lucai Cai, Andreas Gerstlauer, and Daniel Gajski, "Retargetable Profiling for Rapid, Early System-Level Design Space Exploration," CECS, UC Irvine, Technical Report CECS-TR-04-04, October 2003.

2003:

• Dongwan Shin, Andreas Gerstlauer, Rainer Doemer, Daniel Gajski, "C-based Interactive RTL Design Methodology," CECS, UC Irvine, Technical Report CECS-TR-03-42, December 2003.
• Samar Abdi, Junyu Peng, Haobo Yu, Dongwan Shin, Andreas Gerstlauer, Rainer Doemer, Daniel Gajski, "System-on-Chip Environment (SCE Version 2.2.0 Beta): Tutorial," CECS, UC Irvine, Technical Report CECS-TR-03-41, July 2003.
• Dongwan Shin, Samar Abdi, Daniel Gajski, "Automatic Generation of Bus Functional Models from Transaction Level Models," CECS, UC Irvine, Technical Report CECS-TR-03-33, November 2003.
• Daniel Gajski and Samar Abdi, "System Debugging and Verification : A New Challenge," CECS, UC Irvine, Technical Report CECS-TR-03-31, October 2003.
• Andreas Gerstlauer, "Communication Abstractions for System-Level Design and Synthesis," CECS, UC Irvine, Technical Report CECS-TR-03-30, October 2003.
• Samar Abdi and Daniel D. Gajski, "Provably Correct Architecture Refinement," CECS, UC Irvine, Technical Report CECS-TR-03-29, September 2003.
• Daniel D. Gajski, "NISC: The Ultimate Reconfigurable Component," CECS, UC Irvine, Technical Report CECS-TR-03-28, September 2003.
• Andreas Gerstlauer, Kiran Ramineni, Rainer Doemer and Daniel D. Gajski, "System-On-Chip Specification Style Guide," CECS, UC Irvine, Technical Report CECS-TR-03-21, June 2003.
• Kiran Ramineni and Daniel Gajski, "C to SpecC Conversion Style," CECS, UC Irvine, Technical Report CECS-TR-03-13, April 2003.
• Haobo Yu, Andreas Gerstlauer, Daniel Gajski, "RTOS Scheduling in Transaction Level Models," CECS, UC Irvine, Technical Report CECS-TR-03-12, March 2003.
• Lucai Cai, Shireesh Verma, Daniel D. Gajski, "Comparison of SpecC and SystemC Languages for System Design," CECS, UC Irvine, Technical Report CECS-TR-03-11, May 2003.
• Lucai Cai and Daniel Gajski, "Transaction Level Modeling in System Level Design," CECS, UC Irvine, Technical Report CECS-TR-03-10, March 2003.
• Anshuman Tripathi, Shireesh Verma, Daniel D. Gajski, "G.729E Algorithm Optimization for ARM926EJ-S Processor," CECS, UC Irvine, Technical Report CECS-TR-03-09, March 2003.
• Samar Abdi and Daniel Gajski, "Automatic Communication Refinement for System Level Design," CECS, UC Irvine, Technical Report CECS-TR-03-08, March 2003.
• Samar Abdi and Daniel Gajski, "Formal Verification of Specification Partitioning," CECS, UC Irvine, Technical Report CECS-TR-03-06, March 2003.
• Lukai Cai and Daniel Gajski, "Channel Mapping in System Level Design," CECS, UC Irvine, Technical Report CECS-TR-03-03, January 2003.
• Daniel Gajski, Junyu Peng, Andreas Gerstlauer, Haobo Yu, Dongwan Shin, "System Design Methodology and Tools," CECS, UC Irvine, Technical Report CECS-TR-03-02, January 2003.

2002:

• Daniel D. Gajski, "System Level Design Flow: What is needed and what is not," CECS, UC Irvine, Technical Report CECS-TR-02-33, November 2002.
• Lukai Cai, Daniel D. Gajski, "Variable Mapping of System Level Design," CECS, UC Irvine, Technical Report CECS-TR-02-32, October 2002.
• Lukai Cai, Daniel D. Gajski, "Grouping-Based Architecture Exploration of System-Level Design," CECS, UC Irvine, Technical Report CECS-TR-02-31, August 2002.
• Lukai Cai, Daniel D. Gajski, Mike Olivarez, Paul Kritzinger, "C/C++ Based System Design Flow Using SpecC, VCC and SystemC," CECS, UC Irvine, Technical Report CECS-TR-02-30, June 2002.
• S. Abdi, J. Peng, R. Doemer, D. Shin, A. Gerstlauer, A. Gluhak, L.Cai, Q. Xie, H. Yu, P. Zhang, D. Gajski, "System-On-Chip Environment (SCE): Tutorial," CECS, UC Irvine, Technical Report CECS-TR-02-28, September 2002.
• Haobo Yu, Daniel D. Gajski, "RTOS Modeling in System Level Synthesis," CECS, UC Irvine, Technical Report CECS-TR-02-25, August 2002.
• Lukai Cai, Daniel D. Gajski, "Specification Tuning of System-Level Design," CECS, UC Irvine, Technical Report CECS-TR-02-20, June 2002.
• Lukai Cai, Daniel D. Gajski, "Parallelization Optimization of System-Level Specification," CECS, UC Irvine, Technical Report CECS-TR-02-18, June 2002.
• Andreas Gerstlauer, Daniel D. Gajski, "System-Level Abstraction Semantics," CECS, UC Irvine, Technical Report CECS-TR-02-17, July 2002.
• Andreas Gerstlauer, "SpecC Modeling Guidelines," CECS, UC Irvine, Technical Report CECS-TR-02-16, April 2002.
• Junyu Peng, Lukai Cai, Andreas Gerstlauer, Daniel D. Gajski, "Interactive System Design Flow," CECS, UC Irvine, Technical Report CECS-TR-02-15, April 2002.
• Junyu Peng, Samar Abdi, Daniel D. Gajski, "Automatic Model Refinement for Fast Architecture Exploration," CECS, UC Irvine, Technical Report CECS-TR-02-14, April 2002.
• Dongwan Shin, Daniel D. Gajski, "Interface Synthesis from Protocol Specification," CECS, UC Irvine, Technical Report CECS-TR-02-13, April 2002.
• Dongwan Shin, Daniel D. Gajski, "Queue Generation Algorithm for Interface Synthesis," CECS, UC Irvine, Technical Report CECS-TR-02-12, February 2002.
• Dongwan Shin, Daniel D. Gajski, "Scheduling in RTL Design Methodology," CECS, UC Irvine, Technical Report CECS-TR-02-11, April 2002.
• Pei Zhang, Daniel D. Gajski, "RTL Design and Synthesis of Sequential Matrix Multiplication," CECS, UC Irvine, Technical Report CECS-TR-02-09, April 2002.
• Lukai Cai, Daniel D. Gajski, "System Level Design Using SpecC Profiler," CECS, UC Irvine, Technical Report CECS-TR-02-08, April 2002.
• Lukai Cai, Daniel D. Gajski, "Introduction of Design-Oriented Profiler of SpecC Language," CECS, UC Irvine, Technical Report CECS-TR-02-07, March 2002.
• Qiang Xie, Daniel D. Gajski, "Parity Checker Implementations in SpecC," CECS, UC Irvine, Technical Report CECS-TR-02-06, January 2002.
• Haobo Yu, Daniel D. Gajski, "Datapath Synthesis for a 16-bit Microprocessor," CECS, UC Irvine, Technical Report CECS-TR-02-05, January 2002.
• Wolfgang Mueller, Rainer Doemer, Daniel D. Gajski, "The Formal Execution Semantics of SpecC," CECS, UC Irvine, Technical Report CECS-TR-02-04, January 2002.