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    SystemC
    Recoding Infrastructure for SystemC v0.6.0 derived from Accellera SystemC 2.3.1
    
   Accellera SystemC proof-of-concept library 
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#include "sysc/kernel/sc_simcontext.h"

Go to the source code of this file.
Namespaces | |
| sc_core | |
Functions | |
| sc_simcontext * | sc_core::sc_get_curr_simcontext () | 
| void | sc_core::message_test () | 
| void | sc_core::aux_seg_bound (sc_simcontext *simc) | 
| A new parameter segment ID is added for the out-of-order simulation.  More... | |
| void | sc_core::wait (int, sc_simcontext *) | 
| void | sc_core::wait (const sc_event &, int=-1, sc_simcontext *=sc_get_curr_simcontext()) | 
| A new parameter segment ID is added for the out-of-order simulation.  More... | |
| void | sc_core::wait (const sc_event_or_list &, int=-1, sc_simcontext *=sc_get_curr_simcontext()) | 
| A new parameter segment ID is added for the out-of-order simulation.  More... | |
| void | sc_core::wait (const sc_event_and_list &, int=-1, sc_simcontext *=sc_get_curr_simcontext()) | 
| A new parameter segment ID is added for the out-of-order simulation.  More... | |
| void | sc_core::wait (const sc_time &, int=-1, sc_simcontext *=sc_get_curr_simcontext()) | 
| A new parameter segment ID is added for the out-of-order simulation.  More... | |
| void | sc_core::wait (double v, sc_time_unit tu, int seg_id=-1, sc_simcontext *simc=sc_get_curr_simcontext()) | 
| A new parameter segment ID is added for the out-of-order simulation.  More... | |
| void | sc_core::wait (const sc_time &, const sc_event &, int=-1, sc_simcontext *=sc_get_curr_simcontext()) | 
| A new parameter segment ID is added for the out-of-order simulation.  More... | |
| void | sc_core::wait (double v, sc_time_unit tu, const sc_event &e, int seg_id=-1, sc_simcontext *simc=sc_get_curr_simcontext()) | 
| A new parameter segment ID is added for the out-of-order simulation.  More... | |
| void | sc_core::wait (const sc_time &, const sc_event_or_list &, int=-1, sc_simcontext *=sc_get_curr_simcontext()) | 
| A new parameter segment ID is added for the out-of-order simulation.  More... | |
| void | sc_core::wait (double v, sc_time_unit tu, const sc_event_or_list &el, int seg_id=-1, sc_simcontext *simc=sc_get_curr_simcontext()) | 
| A new parameter segment ID is added for the out-of-order simulation.  More... | |
| void | sc_core::wait (const sc_time &, const sc_event_and_list &, int=-1, sc_simcontext *=sc_get_curr_simcontext()) | 
| A new parameter segment ID is added for the out-of-order simulation.  More... | |
| void | sc_core::wait (double v, sc_time_unit tu, const sc_event_and_list &el, int seg_id=-1, sc_simcontext *simc=sc_get_curr_simcontext()) | 
| A new parameter segment ID is added for the out-of-order simulation.  More... | |
| void | sc_core::next_trigger (sc_simcontext *=sc_get_curr_simcontext()) | 
| A new parameter segment ID is added for the out-of-order simulation.  More... | |
| void | sc_core::next_trigger (const sc_event &, sc_simcontext *=sc_get_curr_simcontext()) | 
| A new parameter segment ID is added for the out-of-order simulation.  More... | |
| void | sc_core::next_trigger (const sc_event_or_list &, sc_simcontext *=sc_get_curr_simcontext()) | 
| A new parameter segment ID is added for the out-of-order simulation.  More... | |
| void | sc_core::next_trigger (const sc_event_and_list &, sc_simcontext *=sc_get_curr_simcontext()) | 
| A new parameter segment ID is added for the out-of-order simulation.  More... | |
| void | sc_core::next_trigger (const sc_time &, sc_simcontext *=sc_get_curr_simcontext()) | 
| A new parameter segment ID is added for the out-of-order simulation.  More... | |
| void | sc_core::next_trigger (double v, sc_time_unit tu, sc_simcontext *simc=sc_get_curr_simcontext()) | 
| A new parameter segment ID is added for the out-of-order simulation.  More... | |
| void | sc_core::next_trigger (const sc_time &, const sc_event &, sc_simcontext *=sc_get_curr_simcontext()) | 
| A new parameter segment ID is added for the out-of-order simulation.  More... | |
| void | sc_core::next_trigger (double v, sc_time_unit tu, const sc_event &e, sc_simcontext *simc=sc_get_curr_simcontext()) | 
| A new parameter segment ID is added for the out-of-order simulation.  More... | |
| void | sc_core::next_trigger (const sc_time &, const sc_event_or_list &, sc_simcontext *=sc_get_curr_simcontext()) | 
| A new parameter segment ID is added for the out-of-order simulation.  More... | |
| void | sc_core::next_trigger (double v, sc_time_unit tu, const sc_event_or_list &el, sc_simcontext *simc=sc_get_curr_simcontext()) | 
| A new parameter segment ID is added for the out-of-order simulation.  More... | |
| void | sc_core::next_trigger (const sc_time &, const sc_event_and_list &, sc_simcontext *=sc_get_curr_simcontext()) | 
| A new parameter segment ID is added for the out-of-order simulation.  More... | |
| void | sc_core::next_trigger (double v, sc_time_unit tu, const sc_event_and_list &el, sc_simcontext *simc=sc_get_curr_simcontext()) | 
| A new parameter segment ID is added for the out-of-order simulation.  More... | |
| bool | sc_core::timed_out (sc_simcontext *) | 
| void | sc_core::sc_set_location (const char *, int, sc_simcontext *=sc_get_curr_simcontext()) | 
 1.8.5