Content-type: text/html Manpage of risc

risc

Section: Misc. Reference Manual Pages (l)
Updated: July 6, 2018
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NAME

risc - Recoding Infrastructure for SystemC (RISC) Compiler and Simulator

SYNOPSIS

risc [ options ] design [ options ]

DESCRIPTION

risc is a dedicated compiler for the SystemC language. The purpose of risc is to parse, analyze, instrument, and compile a SystemC source program into an executable program for out-of-order parallel simulation. risc is a frontend source-to-source compiler for SystemC built on top of the ROSE compiler infrastructure with GNU or Intel C++ as backend target compiler. As such, risc relies on and supports also most of the ROSE and GNU compiler options.

Using the command syntax shown in the synopsis above, the specified design is compiled. By default, risc reads the SystemC source file, performs preprocessing and builds an internal representation (abstract syntax tree) and a Segment Graph (SG) of the model. Next, segment conflict analysis is performed and the design model is instrumented for Out-of-Order Parallel Discrete Event Simulation (OoO PDES). Finally, instrumented C++ code is generated, compiled, and linked into an executable file that can be run for fast parallel simulation.

On successful completion, the exit value 0 is returned. In case of errors during processing, an error code with a brief diagnostic message is written to the standard error stream and the compilation is aborted with an exit value greater than zero.

For preprocessing and C++ compilation into an executable file, risc relies on the availability of an external C++ compiler which is used automatically in the background. By default, the GNU C++ compiler g++ is used. Alternatively (see options -risc:icpc and -risc:mic below), the Intel C++ compiler icpc may be used to generate an executable optimized for Intel processors with SIMD capabilities or the Intel Many-Integrated-Core (MIC) architecture.

ARGUMENTS

design: specifies the file name of the input SystemC design model; by default, the base name of design is used as base name for the intermediate and output files;

OPTIONS

-h | --help: print the risc compiler version and a brief usage information message to standard output and quit;
-v | --verbose: increment the verbosity level so that all tasks performed are logged to standard error (default: be silent); at level 1, high-level messages about the tasks performed are displayed; at level 2, additional details such as input and output file names are listed; at level 3, very detailed information about each executed task is printed;
-vv: increment the verbosity level by two counts (same as -v -v );
-vvv: increment the verbosity level by three counts (same as -v -v -v );
-w | --warnings: increment the warning level so that compiler warning messages are enabled (default: warnings are disabled); four levels are supported ranging from only important warnings (level 1) to pedantic warnings (level 4); for most cases, warning level 2 is recommended ( -w -w );
-ww: increment the warning level by two counts (same as -w -w );
-www: increment the warning level by three counts (same as -w -w -w );
-g: add a symbol table suitable for debugging (e.g. using gdb ) to the generated object files and simulation executable (default: no debugging symbols);
-O | -O level: optimize the generated simulation executable for higher execution speed and/or less memory usage (default: no optimization);
-Idir: add the specified dir to the include path (extend the list of directories to be searched for including source files); include directories are searched in the order of their specification; the standard include path ($SYSTEMC_LW_HOME/include or $SYSTEMC_OOP_HOME/include) is automatically appended to this list; by default, only the standard include directories are searched;
-Ldir: add the specified dir to the library path (extend the list of directories to be searched for linker libraries); the library path is searched in the specified order; the standard library path ($SYSTEMC_OOP_HOME/lib) is automatically appended to this list; by default, only the standard library path is searched;
-llib: add the specified lib to the list of libraries for the linker so that the executable is linked against lib; libraries are linked in the specified order; the standard libraries (i.e. -lsystemc) are automatically appended to this list; by default, only standard libraries are used;
-c: perform only the preprocessing, analysis, instrumentation, and compilation tasks; skip the final linking stage so that only an object file is created (default: perform all tasks including linking);
-o output file: specify the name of the final output file explicitly (default: a.out);
-psg: switch to partial segment graph (PSG) generation mode (and do not link); this generates a file with suffix .psg for the current translation unit; PSG files follow the DOT graph description language and can be processed with DOT file tools (e.g. displayed with the xdot.py tool); for 3rd-party IP components, PSG files may be edited with a text editor for further fine-tuning and IP protection;
-psg_input PSG file: specifies the name of a PSG input file; the specified file will be loaded and its PSG will be integrated with the current translation unit to form a complete segment graph;
-psg_output output file: in PSG generation mode (see above), this specifies the name of the PSG output file explicitly; by default, the output PSG file has the same basename as the input SystemC file;
-risc:dump: output the computed segment graph (SG) and conflict tables as HTML files (default: no HTML files are generated); these files may be viewed by a user in a browser in order to inspect the out-of-order execution conditions of the model and improve it accordingly;
-risc:icpc: use the Intel C++ compiler icpc in the backend for generating the executable (default: GNU C++ compiler g++ );
-risc:mic: use the Intel C++ compiler icpc with option -mic in the backend for cross-compiling an executable for the Intel Many Integrated Core (MIC) architecture (default: generate an executable for the same processor the compiler is running on);
-risc:elab filename: import the elaboration result produced by the RISC elaborator elab from file filename and use it for segment conflict analysis based on a dynamic elaboration phase (default: pure static analysis);
-<rose:option>: pass this option through to the underlying ROSE compiler (default: none);
-<GNU option>: pass this option through to the underlying GNU compiler (default: none);

ENVIRONMENT

SYSTEMC_LW_HOME: is used at compile-time to find the RISC light-weight SystemC header files which are expected in directory $SYSTEMC_LW_HOME/include (default: none);
SYSTEMC_OOP_HOME: is used at compile-time to find the RISC out-of-order SystemC header files which are expected in directory $SYSTEMC_OOP_HOME/include, and the RISC out-of-order SystemC library which is expected in directory $SYSTEMC_OOP_HOME/lib (default: none);
SYSTEMC_MIC_HOME: is used at compile-time to find the RISC SystemC header files and library files for the Intel many-integrated-core (MIC) architecture which are expected in directory $SYSTEMC_MIC_HOME/include and and $SYSTEMC_MIC_HOME/lib, respectively (default: none); this is used only when the option -mic is used (see above);
SYSC_PRINT_MODE_MESSAGE: is used by the RISC simulator at run-time to print the mode of simulation and also the actual values of the environment variables listed below; these log lines start with "***" and are only printed when $SYSC_PRINT_MODE_MESSAGE is defined (default: no messages are printed);
SYSC_SYNC_PAR_SIM: is used by the RISC simulator at run-time to force the RISC out-of-order SystemC simulation to fall back to synchronous (in-order) PDES execution; note that this mode is also automatically selected when SystemC primitive channels with update requests are used (default: out-of-order execution);
SYSC_PRINT_VERBOSE_MESSAGE: is used by the RISC simulator at run-time to print debugging information about the simulator queues, event processing, and time advances; such debugging lines are only printed when $SYSC_PRINT_VERBOSE_MESSAGE is defined (default: no debugging infos are printed);
SYSC_DISABLE_PREDICTION: is used by the RISC simulator at run-time to switch back to non-predictive conflict detection; this avoids scheduling overhead at run time, but usually results in slower simulation due to more conflicts; if $SYSC_DISABLE_PREDICTION is defined, thread state prediction is not used during out-of-order scheduling (default: out-of-order execution with prediction);
SYSC_PAR_SIM_CPUS: is used by the RISC simulator at run-time to set the maximum number of concurrent threads allowed in the RISC out-of-order SystemC simulation (default: 64);

VERSION

The RISC compiler and simulator are release version 0.5.0.

AUTHORS

Zhongqi Cheng <zhongqc@uci.edu>, Rainer Doemer <doemer@uci.edu>, Guantao Liu <guantaol@uci.edu>, and Tim Schmidt <schmidtt@uci.edu>.

COPYRIGHT

LICENSE

Open source BSD license terms apply.

BUGS, LIMITATIONS

This is an academic proof-of-concept prototype implementation, not commercial-quality software. See the file BUGS in the software packages for known limitations.

This document was created by man2html, using the manual pages.
Time: 17:32:34 GMT, September 30, 2018