Rainer Dömer: Publications

listed by publication date (list by type)

2024
2023
2022
2021
2020
2019
2018
2017
2016
2015
2014
2013
2012
2011
2010
2009
2008
2007
2006
2005
2004
2003
2002
2001
2000
1999
1998
1997
1996
1995
1994

2024

A. Fong, Y. Wang, R. Dömer: "A Synthetic Graph Toolbox for Benchmarking the Grid of Processing Cells", Center for Embedded and Cyber-Physical Systems, Technical Report 24-03, June 2024.
Y. Li, Y. Wang, R. Dömer: "Generating Synthetic Data Flow Models in SystemC TLM based on TGFF", Center for Embedded and Cyber-Physical Systems, Technical Report 24-02, May 2024.
X. Che, R. Dömer: "Improved Canny Edge Detector for Parallel Color Video Processing", Center for Embedded and Cyber-Physical Systems, Technical Report 24-01, April 2024.
E. Arasteh, V. Govindasamy, R. Dömer: "BusyMap, an Efficient Data Structure to Observe Interconnect Contention in SystemC TLM-2.0", Proceedings of the Design, Automation and Test in Europe (DATE) Conference, Valencia, Spain, March 2024.
L. Luchterhandt, T. Nellius, R. Beck, R. Dömer, P. Kneuper, W. Mueller, and B. Sadiye: "Implementation of Different Communication Structures for a Rocket Chip Based RISC-V Grid of Processing Cells", Proceedings of the MBMV Workshop, Kaiserslautern, Germany, February 2024.

2023

C. Raccomandato, E. Arasteh, R. Dömer: "MapGL: Interactive Application Mapping and Profiling on a Grid of Processing Cells", Proceedings (research track) of the Design and Verification Conference in Europe, Munich, Germany, November 2023.
C. Raccomandato, E. Arasteh, R. Dömer: "Grid-based Mapping and Analysis of a GoogLeNet CNN using MapGL Editor", Proceedings (engineering track) of the Design and Verification Conference in Europe, Munich, Germany, November 2023.
V. Govindasamy, R. Dömer: "Instruction-Level Modeling and Evaluation of a Cache-less Grid of Processing Cells", Proceedings of Forum on Specification and Design Languages, Turin, Italy, September 2023.
E. Arasteh, R. Dömer: "Fast Loosely-Timed Deep Neural Network Models with Accurate Memory Contention", ACM Transactions on Embedded Computing Systems (TECS), vol. 23, no. 5, article 75, 32 pages, June 2023.
Z. Li, R. Dömer: "A Linux-based YUV Video Player", Center for Embedded and Cyber-Physical Systems, Technical Report 23-02, May 2023.
L. Luchterhandt, T. Nellius, R. Beck, R. Dömer, P. Kneuper, W. Mueller, and B. Sadiye: "Towards a Rocket Chip Based Implementation of the RISC-V GPC Architecture", Proceedings of the MBMV Workshop, Freiburg, Germany, March 2023.
C. Raccomandato, R. Dömer: "Modeling and Mapping of a GoogLeNet CNN on a Grid of Processing Cells", Center for Embedded and Cyber-Physical Systems, Technical Report 23-01, March 2023.
E. Arasteh, R. Dömer: "An Untimed SystemC Model of GoogLeNet", chapter in "Analysis, Estimations, and Applications of Embedded Systems" by M. Wehrmeister, M. Kreuz, M. Götz, S. Henkler, A. Pimentel, and A. Rettberg, reprint of best papers at IESS 2019, Springer Nature, Switzerland, January 2023. (ISBN 978-3-031-26499-3)

2022

Y. Wang, A. Daroui, R. Dömer: "Demonstrating Scalability of the Checkerboard GPC with SystemC TLM-2.0", Proceedings of the International Embedded Systems Symposium, "Designing Modern Embedded Systems: Software, Hardware, and Applications" (ed. S. Henkler, M. Kreutz, M. Wehrmeister, M. Götz, A. Rettberg), Springer, Lippstadt, Germany, November 2022.
V. Govindasamy, E. Arasteh, R. Dömer: "Minimizing Memory Contention in an APNG Encoder using a Grid of Processing Cells", Proceedings of the International Embedded Systems Symposium, "Designing Modern Embedded Systems: Software, Hardware, and Applications" (ed. S. Henkler, M. Kreutz, M. Wehrmeister, M. Götz, A. Rettberg), Springer, Lippstadt, Germany, November 2022.
A. Daroui, R. Dömer: "A Loosely-Timed TLM-2.0 Model of a JPEG Encoder on a Checkerboard GPC", Center for Embedded and Cyber-Physical Systems, Technical Report 22-04, October 2022.
Y. Wang, R. Dömer: "A Scalable SystemC Model of a Checkerboard Grid of Processing Cells", Center for Embedded and Cyber-Physical Systems, Technical Report 22-03, September 2022.
V. Govindasamy, R. Dömer: "Mapping of an APNG Encoder to the Grid of Processing Cells Architecture", Center for Embedded and Cyber-Physical Systems, Technical Report 22-02, September 2022.
R. Dömer: "A Grid of Processing Cells (GPC) with Local Memories", Center for Embedded and Cyber-Physical Systems, Technical Report 22-01, April 2022.

2021

E. Arasteh, R. Dömer: "Systematic Evaluation of Six Models of GoogLeNet using PDES", Center for Embedded and Cyber-Physical Systems, Technical Report 21-03, September 2021.
E. Arasteh, R. Dömer: "Improving Parallelism in System Level Models by Assessing PDES Performance", Proceedings of Forum on Specification and Design Languages, Antibes, France, September 2021.
Y. Wang, R. Dömer: "A Tool to Flatten Multi-File SystemC Models for the RISC compiler", Center for Embedded and Cyber-Physical Systems, Technical Report 21-01, March 2021.

2020

V. Govindasamy, R. Dömer: "A SystemC Model of a PNG Encoder", Center for Embedded and Cyber-Physical Systems, Technical Report 20-02, December 2020.
R. Dömer, Z. Cheng, D. Mendoza, E. Arasteh: "Pushing the Limits of Parallel Discrete Event Simulation for SystemC", in "A Journey of Embedded and Cyber-Physical Systems" by Jian-Jia Chen, Springer Nature, Switzerland, August 2020. (ISBN 978-3-030-47487-4)
R. Dömer, Heiko Falk, Michael Engel: "Foreword", in "A Journey of Embedded and Cyber-Physical Systems" by Jian-Jia Chen, Springer Nature, Switzerland, August 2020. (ISBN 978-3-030-47487-4)
Z. Cheng, T. Schmidt, R. Dömer: "Scaled Static Analysis and IP Reuse for Out-of-Order Parallel SystemC Simulation", International Journal of Parallel Programming (IJPP), Springer, June 2020.
D. Mendoza, Z. Cheng, E. Arasteh, R. Dömer: "Lazy Event Prediction using Defining Trees and Schedule Bypass for Out-of-Order PDES", Proceedings of the Design, Automation and Test in Europe (DATE) Conference, Grenoble, France, March 2020.
Z. Cheng, E. Arasteh, R. Dömer: "Event Delivery using Prediction for Faster Parallel SystemC Simulation", Proceedings of the Asia and South Pacific Design Automation Conference, Beijing, China, January 2020.
Z. Cheng, T. Schmidt, R. Dömer: "SystemC Coding Guideline for Faster Out-of-Order Parallel Discrete Event Simulation", chapter 6 in "Languages, Design Methods, and Tools for Electronic System Design" by T. Kazmierski, S. Steinhorst and D. Grosse, reprint of best papers at FDL 2018, Springer Nature, Switzerland, January 2020. (ISBN 978-3-030-31585-6)

2019

D. Mendoza, A. Dingankar, Z. Cheng, R. Dömer: "Integrating Parallel SystemC Simulation into Simics(R) Virtual Platform", Proceedings of the Design and Verification Conference in Europe, Munich, Germany, October 2019.
Z. Cheng, R. Dömer: "Analyzing Variable Entanglement for Parallel Simulation of SystemC TLM-2.0 Models", ACM Transactions on Embedded Computing Systems (TECS), vol. 18, no. 5s, article 79, 20 pages, October 2019.
G. Liu, T. Schmidt, Z. Cheng, D. Mendoza, R. Dömer: "RISC Compiler and Simulator, Release V0.6.0: Out-of-Order Parallel Simulatable SystemC Subset", Center for Embedded and Cyber-Physical Systems, Technical Report 19-04, September 2019.
E. Arasteh, R. Dömer: "An Untimed SystemC Model of GoogLeNet", Proceedings of the International Embedded Systems Symposium, "Embedded Systems: Design, Analysis and Verification" (ed. G. Schirner, M. Götz, A. Rettberg, M. Zanella, F. Rammig), Springer, Friedrichshafen, Germany, September 2019.
Z. Cheng, T. Schmidt, R. Dömer: "Enabling IP Reuse and Protection in Out-of-Order Parallel SystemC Simulation", Proceedings of the International Embedded Systems Symposium, "Embedded Systems: Design, Analysis and Verification" (ed. G. Schirner, M. Götz, A. Rettberg, M. Zanella, F. Rammig), Springer, Friedrichshafen, Germany, September 2019.

2018

R. Dömer, Z. Cheng, D. Mendoza, A. Dingankar: "RISC: Recoding Infrastructure for SystemC, Open Source Framework for Parallel Simulation", Workshop on Open Source EDA Technology at ICCAD, San Diego, California, November 2018.
G. Liu, T. Schmidt, Z. Cheng, D. Mendoza, R. Dömer: "RISC Compiler and Simulator, Release V0.5.0: Out-of-Order Parallel Simulatable SystemC Subset", Center for Embedded and Cyber-Physical Systems, Technical Report 18-03, September 2018.
Z. Cheng, T. Schmidt, R. Dömer: "SystemC Coding Guideline for Faster Out-of-Order Parallel Discrete Event Simulation", Proceedings of Forum on Specification and Design Languages, Munich, Germany, September 2018.
T. Schmidt, Z. Cheng, R. Dömer: "Port Call Path Sensitive Conflict Analysis for Instance-Aware Parallel SystemC Simulation", Proceedings of Design, Automation and Test in Europe, Dresden, Germany, March 2018.

2017

D. Mendoza, R. Dömer: "A Tool for Visualization of SystemC Models", Center for Embedded and Cyber-Physical Systems, Technical Report 17-06, November 2017.
Z. Cheng, T. Schmidt, G. Liu, R. Dömer: "Thread- and Data-Level Parallel Simulation in SystemC, a Bitcoin Miner Case Study", Proceedings of the International High Level Design Validation and Test Workshop 2017, Santa Cruz, California, October 2017.
G. Liu, T. Schmidt, Z. Cheng, R. Dömer: "RISC Compiler and Simulator, Release V0.4.0: Out-of-Order Parallel Simulatable SystemC Subset", Center for Embedded and Cyber-Physical Systems, Technical Report 17-05, July 2017.
T. Schmidt, G. Liu, R. Dömer: "Exploiting Thread and Data Level Parallelism for Ultimate Parallel SystemC Simulation", Proceedings of the Design Automation Conference 2017, Austin, TX, June 2017.
G. Schirner, A. Gerstlauer, R. Dömer: "SCE: System-on-Chip Environment", chapter 31 in "Handbook of Hardware/Software Codesign" by S. Ha and J. Teich, Springer Netherlands, Dordrecht, June 2017. (ISBN 978-94-017-7358-4)
R. Dömer, G. Liu, T. Schmidt: "Parallel Simulation", chapter 17 in "Handbook of Hardware/Software Codesign" by S. Ha and J. Teich, Springer Netherlands, Dordrecht, June 2017. (ISBN 978-94-017-7358-4)
S. Ha, J. Teich, C. Haubelt, M. Glaß, T. Mitra, R. Dömer, P. Eles, A. Shrivastava, A. Gerstlauer, S. Bhattacharyya: "Introduction to Hardware/Software Codesign", chapter 1 in "Handbook of Hardware/Software Codesign" by S. Ha and J. Teich, Springer Netherlands, Dordrecht, June 2017. (ISBN 978-94-017-7358-4)
T. Schmidt, G. Liu, R. Dömer: "Hybrid Analysis of SystemC Models for Fast and Accurate Parallel Simulation", Proceedings of the Asia and South Pacific Design Automation Conference 2017, Tokyo, Japan, January 2017.

2016

R. Dömer: "Seven Obstacles in the Way of Standard-Compliant Parallel SystemC Simulation", IEEE Embedded Systems Letters, vol. 8, no. 4, pp. 81-84, December 2016.
K. Moazzemi, R. Dömer, A. Chandramowlishwaran: "A SystemC Model for N-body Problems and its Parallel Design Space Exploration", Center for Embedded and Cyber-Physical Systems, Technical Report 16-09, November 2016.
F. Arabi, T. Schmidt, R. Dömer: "A Light Weight SystemC Library for Faster Compilation", Center for Embedded and Cyber-Physical Systems, Technical Report 16-07, October 2016.
G. Liu, T. Schmidt, R. Dömer: "RISC Compiler and Simulator, Beta Release V0.3.0: Out-of-Order Parallel Simulatable SystemC Subset", Center for Embedded and Cyber-Physical Systems, Technical Report 16-06, September 2016.
Z. Cheng, R. Dömer: "A SystemC Model of a Bitcoin Miner", Center for Embedded and Cyber-Physical Systems, Technical Report 16-04, September 2016.
G. Liu, T. Schmidt, R. Dömer: "A Segment-Aware Multi-Core Scheduler for SystemC PDES", Proceedings of the International High Level Design Validation and Test Workshop 2016, Santa Cruz, California, October 2016.
T. Schmidt, G. Liu, R. Dömer: "Automatic Generation of Thread Communication Graphs from SystemC Source Code", Proceedings of the 19th International Workshop on Software and Compilers for Embedded Systems, St. Goar, Germany, May 2016.

2015

G. Liu, T. Schmidt, R. Dömer: "RISC Compiler and Simulator, Alpha Release V0.2.1: Out-of-Order Parallel Simulatable SystemC Subset", Center for Embedded and Cyber-Physical Systems, Technical Report 15-02, October 2015.
C. Chang, R. Dömer: "May-Happen-in-Parallel Analysis of ESL Models using UPPAAL Model Checking", Proceedings of the Design, Automation and Test in Europe Conference 2015, Grenoble, France, March 2015.
C. Chang, R. Dömer: "Communication Protocol Analysis of Transaction-Level Models using Satisfiability Modulo Theories", Proceedings of the Asia and South Pacific Design Automation Conference 2015, Tokyo, Japan, January 2015.
G. Liu, T. Schmidt, R. Dömer, A. Dingankar, D. Kirkpatrick: "Optimizing Thread-to-Core Mapping on Manycore Platforms with Distributed Tag Directories", Proceedings of the Asia and South Pacific Design Automation Conference 2015, Tokyo, Japan, January 2015.

2014

Y. Samei, R. Dömer: "Automated Estimation of Power Consumption for Rapid System Level Design", Proceedings of 33rd IEEE International Performance Computing and Communications Conference, Austin, Texas, December 2014.
W. Chen, X. Han, C. Chang, G. Liu, R. Dömer: "Out-of-Order Parallel Discrete Event Simulation for Transaction Level Models", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 33, no. 12, pp. 1859-1872, December 2014.
C. Chang, R. Dömer: "Abstracting ESL Designs to UPPAAL System Models", Center for Embedded and Cyber-Physical Systems, Technical Report 14-13, November 2014.
Y. Samei, R. Dömer: "MAVO: An Automated Framework for ESL Design: Monitor, Analyze, Visualize and Optimize", Center for Embedded and Cyber-Physical Systems, Technical Report 14-12, November 2014.
T. Schmidt, K. Grüttner, , R. Dömer, A. Rettberg: "A Program State Machine Based Virtual Processing Model in SystemC", Proceedings of ACM 4th Embedded Operating Systems Workshop, Lisbon, Portugal, November 2014.
Y. Samei, R. Dömer: "PowerMonitor: a Versatile API for Automated Power-Aware ESL Design", Proceedings of Forum on Specification and Design Languages, Munich, Germany, October 2014.
R. Dömer: "Foreword", in "Out-of-Order Parallel Discrete Event Simulation for Electronic System-Level Design" by Weiwei Chen, Springer International Publishing Switzerland, August 2017. (ISBN 978-3-319-08752-8) EDAA Outstanding Dissertation Award
DATE Best Paper Award 2014: W. Chen, X. Han, R. Dömer: "May-Happen-in-Parallel Analysis based on Segment Graphs for Safe ESL Models", Proceedings of Design, Automation and Test in Europe, Dresden, Germany, March 2014.

2013

G. Liu, R. Dömer: "A Hybrid Thread Library for Efficient Electronic System Level Simulation", Center for Embedded Computer Systems, Technical Report 13-11, October 2013.
X. Han, W. Chen, R. Dömer: "Designer-in-the-Loop Recoding of ESL Models using Static Parallel Access Conflict Analysis", Proceedings of the 16th International Workshop on Software and Compilers for Embedded Systems, St. Goar, Germany, June 2013.
C. Chang, R. Dömer: "Formal Deadlock Analysis of SpecC Models Using Satisfiability Modulo Theories", Proceedings of the International Embedded Systems Symposium, "Embedded Systems: Design, Analysis and Verification" (ed. G. Schirner, M. Götz, A. Rettberg, M. Zanella, F. Rammig), Springer, Paderborn, Germany, June 2013.
T. Azumi, Y. Samei, Y. Hara-Azumi, H. Oyama, R. Dömer: "TECSCE: HW/SW Codesign Framework for Data Parallelism Based on Software Component", Proceedings of the International Embedded Systems Symposium, "Embedded Systems: Design, Analysis and Verification" (ed. G. Schirner, M. Götz, A. Rettberg, M. Zanella, F. Rammig), Springer, Paderborn, Germany, June 2013.
G. Liu, R. Dömer: "A User-level Thread Library Built on Linux Context Functions for Efficient ESL Simulation", Center for Embedded Computer Systems, Technical Report 13-07, June 2013.
X. Han, R. Dömer: "An Extended Eclipse Platform for Recoding System-Level Models", Center for Embedded Computer Systems, Technical Report 13-04, April 2013.
R. Dömer: "RIDE: Recoding Integrated Development Environment", Center for Embedded Computer Systems, Technical Report 13-02, April 2013.
W. Chen, R. Dömer: "Optimized Out-of-Order Parallel Discrete Event Simulation Using Predictions", Proceedings of Design, Automation and Test in Europe, Grenoble, France, March 2013.
W. Chen, X. Han, C. Chang, R. Dömer: "Advances in Parallel Discrete Event Simulation for Electronic System-Level Design", IEEE Design & Test of Computers, vol. 30, no. 1, pp. 45-54, January-February 2013.

2012

H. Peng, R. Dömer: "Towards A Unified Hardware Abstraction Layer Architecture for Embedded Systems", Center for Embedded Computer Systems, Technical Report 12-14, November 2012.
W. Chen, C. Chang, X. Han, R. Dömer: "Eliminating Race Conditions in System-Level Models by using Parallel Simulation Infrastructure", Proceedings of the International High Level Design Validation and Test Workshop 2012, Huntington Beach, California, November 2012.
X. Han, Y. Samei, R. Dömer: "System-Level Modeling and Refinement of a Canny Edge Detector", Center for Embedded Computer Systems, Technical Report 12-13, November 2012.
G. Liu, R. Dömer: "Performance Evaluation and Optimization of A Custom Native Linux Threads Library", Center for Embedded Computer Systems, Technical Report 12-11, October 2012.
P. Chandraiah, R. Dömer: "Computer-Aided Recoding to Create Structured and Analyzable System Models", ACM Transactions on Embedded Computer Systems, vol. 11S, no. 1, article 23, 27 pages, June 2012.
D. Mishra, Y. Samei, N. Dang, R. Dömer, E. Bozorgzadeh: "Multi-layer Configuration Exploration of MPSoCs for Streaming Applications", Electronic System Level Synthesis Conference, San Francisco, California, June 2012.
T. Azumi, Y. Hara-Azumi, R. Dömer: "Virtual Platform Generation Using TECS Software Component and SCE", Poster presentation, "Quo Vadis, Virtual Platforms?" Workshop at Design Automation and Test in Europe, Dresden, Germany, March 2012.
R. Dömer: "Recoding Embedded Applications into Flexible System-Level Models", Invited paper, "Quo Vadis, Virtual Platforms?" Workshop at Design Automation and Test in Europe, Dresden, Germany, March 2012.
W. Chen, X. Han, R. Dömer: "Out-of-Order Parallel Simulation for ESL Design", Proceedings of Design, Automation and Test in Europe, Dresden, Germany, March 2012.
R. Dömer, W. Chen, X. Han: "Parallel Discrete Event Simulation of Transaction Level Models", Proceedings of the Asia and South Pacific Design Automation Conference 2012, Sydney, Australia, February 2012.
W. Chen, R. Dömer: "An Optimizing Compiler for Out-of-Order Parallel ESL Simulation Exploiting Instance Isolation", Proceedings of the Asia and South Pacific Design Automation Conference 2012, Sydney, Australia, February 2012.

2011

T. Mathew, R. Dömer: "A Custom Thread Library Built on Native Linux Threads for Faster Embedded System Simulation", Center for Embedded Computer Systems, Technical Report 11-10, December 2011.
C. Chang, R. Dömer: "System Level Modeling of a H.264 Video Encoder", Center for Embedded Computer Systems, Technical Report 11-04, June 2011.
X. Han, W. Chen, R. Dömer: "A Parallel Transaction-Level Model of H.264 Video Decoder", Center for Embedded Computer Systems, Technical Report 11-03, June 2011.
W. Chen, R. Dömer: "A Distributed Parallel Simulator for Transaction Level Models with Relaxed Timing", Center for Embedded Computer Systems, Technical Report 11-02, May 2011.
W. Chen, X. Han, R. Dömer: "Multicore Simulation of Transaction-Level Models Using the SoC Environment", IEEE Design & Test of Computers, vol. 28, no. 3, pp. 20-31, May-June 2011.
R. Dömer, W. Chen, X. Han, A. Gerstlauer: "Multi-Core Parallel Simulation of System-Level Description Languages", Proceedings of the Asia and South Pacific Design Automation Conference 2011, Yokohama, Japan, January 2011.

2010

W. Chen, X. Han, R. Dömer: "ESL Design and Multi-Core Validation using the System-on-Chip Environment", Proceedings of the International High Level Design Validation and Test Workshop 2010, Anaheim, California, June 2010.
Y. Guo, R. Dömer: "A Hybrid Instruction Set Simulator for System Level Design", Center for Embedded Computer Systems, Technical Report 10-06, June 2010.
G. Schirner, A. Gerstlauer, R. Dömer: "Fast and Accurate Processor Models for Efficient MPSoC Design", ACM Transactions on Design Automation of Electronic Systems, vol. 15, no. 2, article 10, 26 pages, February 2010.
G. Schirner, A. Gerstlauer, R. Dömer: "System-level Development of Embedded Software", Proceedings of the Asia and South Pacific Design Automation Conference 2010, Taipei, Taiwan, January 2010.
R. Dömer: "Computer-Aided Recoding for Multi-Core Systems", Proceedings of the Asia and South Pacific Design Automation Conference 2010, Taipei, Taiwan, January 2010.
W. Chen, R. Dömer: "A Fast Heuristic Scheduling Algorithm for Periodic ConcurrenC Models", Proceedings of the Asia and South Pacific Design Automation Conference 2010, Taipei, Taiwan, January 2010.

2009

R. Dömer: "Efficient Modeling of Embedded Systems using Computer-Aided Recoding", Proceedings of the International Embedded Systems Symposium, "Analysis, Architectures and Modeling of Embedded Systems" (ed. A. Rettberg, M. Zanella, M. Amann, M. Keckeisen, F. Rammig), Springer, Langenargen, Germany, September 2009.
I. Viskic, R. Dömer: "A Configurable TLM of Wireless Sensor Networks for Fast Exploration of System Communication Performance", Proceedings of the International Embedded Systems Symposium, "Analysis, Architectures and Modeling of Embedded Systems" (ed. A. Rettberg, M. Zanella, M. Amann, M. Keckeisen, F. Rammig), Springer, Langenargen, Germany, September 2009.
W. Chen, R. Dömer: "ConcurrenC: A New Approach towards Effective Abstraction of C-based SLDLs", Proceedings of the International Embedded Systems Symposium, "Analysis, Architectures and Modeling of Embedded Systems" (ed. A. Rettberg, M. Zanella, M. Amann, M. Keckeisen, F. Rammig), Springer, Langenargen, Germany, September 2009.
K. P. Kim, R. Dömer: "Design Exploration using Multiple ARM Instruction Set Simulators - A Case Study on a JPEG Encoder", Center for Embedded Computer Systems, Technical Report 09-08, May 2009.
W. Chen, R. Dömer: "ConcurrenC: A Novel Model of Computation for Effective Abstraction of C-based SLDLs", Center for Embedded Computer Systems, Technical Report 09-07, May 2009.
B. Zhang, R. Dömer: "An Eclipse-based Software Platform for the Recoding Integrated Development Environment (RIDE)", Center for Embedded Computer Systems, Technical Report 09-06, May 2009.
R. Leupers, A. Vajda, M. Bekooij, S. Ha, R. Dömer, A. Nohl: "Programming MPSoC Platforms: Road Works Ahead!", Proceedings of Design, Automation and Test in Europe, Nice, France, April 2009.
W. Ecker, W. Müller, R. Dömer: "Hardware-dependent Software - Principles and Practice", Springer, Boston, January 2009. (ISBN 978-1-4020-9435-4)
G. Schirner, R. Dömer, A. Gerstlauer: "High-Level Development, Modeling and Automatic Generation of Hardware-dependent Software", Chapter 8 in "Hardware-dependent Software: Principles and Practice" (ed. W. Ecker, W. Müller, R. Dömer), Springer, Boston, January 2009. (ISBN 978-1-4020-9435-4)
W. Ecker, W. Müller, R. Dömer: "Hardware-dependent Software - Introduction and Overview", Chapter 1 in "Hardware-dependent Software: Principles and Practice" (ed. W. Ecker, W. Müller, R. Dömer), Springer, Boston, January 2009. (ISBN 978-1-4020-9435-4)
R. Dömer, A. Gerstlauer, W. Müller: "Introduction to Hardware-dependent Software Design", Proceedings of the Asia and South Pacific Design Automation Conference 2009, Yokohama, Japan, January 2009.

2008

G. Schirner, R. Dömer: "Quantitative Analysis of the Speed/Accuracy Trade-Off in Transaction Level Modeling", ACM Transactions on Embedded Computing Systems, vol. 8, no. 1, article 4, December 2008.
T. Bohr, R. Dömer: "A Flexible Video Stream Converter", Center for Embedded Computer Systems, Technical Report 08-13, October 2008.
W. Chen, S. Sun, B. Zhang, R. Dömer: "System Level Modeling of a H.264 Decoder", Center for Embedded Computer Systems, Technical Report 08-10, August 2008.
R. Dömer, A. Gerstlauer, J. Peng, D. Shin, L. Cai, H. Yu, S. Abdi, D. Gajski: "System-on-Chip Environment: A SpecC-Based Framework for Heterogeneous MPSoC Design", EURASIP Journal on Embedded Systems, vol. 2008, article ID 647953, 13 pages, July 2008.
P. Chandraiah, R. Dömer: "Code and Data Structure Partitioning for Parallel and Flexible MPSoC Specification Using Designer-Controlled Recoding", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 27, no. 6, pp. 1078-1090, June 2008.
D. Shin, A. Gerstlauer, R. Dömer, D. Gajski: "An Interactive Design Environment for C-based High-level Synthesis of RTL Processors", IEEE Transactions on Very Large Scale Integration Systems, vol. 16, no. 4, pp. 466-475, April 2008.
G. Schirner, R. Dömer: "Introducing Preemptive Scheduling in Abstract RTOS Models using Result Oriented Modeling", Proceedings of Design Automation and Test in Europe, Munich, Germany, March 2008.
S. Sun, R. Dömer: "A Convolutional Encoder and Decoder Model in SpecC", Center for Embedded Computer Systems, Technical Report 08-03, February 2008.
P. Chandraiah, R. Dömer: "Assessment of Productivity Gains Achieved through Automated Source Re-Coding", Center for Embedded Computer Systems, Technical Report 08-02, February 2008.
W. Chen, R. Dömer: "System Specification of a DES Cipher Chip", Center for Embedded Computer Systems, Technical Report 08-01, January 2008.
G. Schirner, A. Gerstlauer, R. Dömer: "Automatic Generation of Hardware dependent Software for MPSoCs from Abstract System Specifications", Proceedings of the Asia and South Pacific Design Automation Conference 2008, Seoul, Korea, January 2008.
P. Chandraiah, R. Dömer: "Automatic Re-coding of Reference Code into Structured and Analyzable SoC Models", Proceedings of the Asia and South Pacific Design Automation Conference 2008, Seoul, Korea, January 2008.

2007

P. Chandraiah, R. Dömer: "Pointer Re-coding for Creating Definitive MPSoC Models", Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis, Salzburg, Austria, September 2007.
EECS Best Student Paper Award: G. Schirner, R. Dömer: "Result Oriented Modeling - A Novel Technique for Fast and Accurate TLM", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 26, no. 9, pp. 1688-1699, Sept. 2007.
A. Gerstlauer, D. Shin, J. Peng, R. Dömer, D. Gajski: "Automatic Layer-Based Generation of System-On-Chip Bus Communication Models", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 26, no. 9, pp. 1676-1687, Sept. 2007.
D. Castellanos, R. Dömer: "System-Level Modeling and Simulation of an Elevator Control System", Center for Embedded Computer Systems, Technical Report 07-04, June 2007.
P. Chandraiah, R. Dömer: "Designer-Controlled Generation of Parallel and Flexible Heterogeneous MPSoC Specification", Proceedings of the Design Automation Conference 2007, San Diego, California, June 2007.
A. Rettberg, M. Zanella, R. Dömer, A. Gerstlauer, F. Rammig: "Embedded System Design: Topics, Techniques and Trends", Springer, Boston, June 2007. (ISBN 978-0-387-72257-3)
G. Schirner, G. Sachdeva, A. Gerstlauer, R. Dömer: "Embedded Software Development in a System-level Design Flow", Proceedings of the International Embedded Systems Symposium, "Embedded System Design: Topics, Techniques and Trends" (ed. A. Rettberg, M. Zanella, R. Dömer, A. Gerstlauer, F. Rammig), Springer, Irvine, California, May 2007.
P. Chandraiah, R. Dömer: "An Interactive Model Re-Coder for Efficient SoC Specification", Proceedings of the International Embedded Systems Symposium, "Embedded System Design: Topics, Techniques and Trends" (ed. A. Rettberg, M. Zanella, R. Dömer, A. Gerstlauer, F. Rammig), Springer, Irvine, California, May 2007.
D. Shin, A. Gerstlauer, R. Dömer, D. Gajski: "An Interactive Design Environment For C-Based High-Level Synthesis", Proceedings of the International Embedded Systems Symposium, "Embedded System Design: Topics, Techniques and Trends" (ed. A. Rettberg, M. Zanella, R. Dömer, A. Gerstlauer, F. Rammig), Springer, Irvine, California, May 2007.
R. Dömer, D. Gajski: "System-level Synthesis from Transaction-level Models: Algorithms and Tools", Proceedings of the Design and Verification Conference 2007, San Jose, California, February 2007.
G. Schirner, A. Gerstlauer, R. Dömer: "Abstract, Multifaceted Modeling of Embedded Processors for System-Level Design", Proceedings of the Asia and South Pacific Design Automation Conference 2007, Yokohama, Japan, January 2007.
P. Chandraiah, J. Peng, R. Dömer: "Creating Explicit Communication in SoC Models Using Interactive Re-Coding", Proceedings of the Asia and South Pacific Design Automation Conference 2007, Yokohama, Japan, January 2007.

2006

G. Schirner, R. Dömer: "Fast and Accurate Transaction Level Models using Result Oriented Modeling", Proceedings of the International Conference on Computer Aided Design, San Jose, California, November 2006.
R. Dömer, A. Gerstlauer, D. Shin: "Cycle-accurate RTL Modeling with Multi-Cycled and Pipelined Components", Proceedings of the International System-on-Chip Design Conference, Seoul, Korea, October 2006.
G. Schirner, R. Dömer: "Accurate yet Fast Modeling of Real-Time Communication", Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis, Seoul, Korea, October 2006.
D. Shin, A. Gerstlauer, J. Peng, R. Dömer, D. Gajski: "Automatic Generation of Transaction-Level Models for Rapid Design Space Exploration", Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis, Seoul, Korea, October 2006.
I. Viskic, R. Dömer: "A Flexible, Syntax Independent Representation (SIR) for System Level Design Models", Proceedings of EuroMicro Conference on Digital System Design, Dubrovnik, Croatia, August 2006.
R. Dömer: "Transaction Level Modeling of Computation", Center for Embedded Computer Systems, Technical Report 06-11, August 2006.
T. Schattkowsky, A. Rettberg, R. Dömer: "Design Space Exploration through Interactive Model Mappings for UML-based Specifications", Proceedings of DAC 2006 Workshop UML for SoC Design, San Francisco, California, July 2006.
A. Gerstlauer, G. Schirner, D. Shin, J. Peng, R. Dömer, D. Gajski: "System-on-Chip Component Models", Center for Embedded Computer Systems, Technical Report 06-10, May 2006.
E. Johnson, A. Gerstlauer, R. Dömer: "Efficient Debugging and Tracing of System Level Designs", Center for Embedded Computer Systems, Technical Report 06-08, May 2006.
G. Schirner, G. Sachdeva, A. Gerstlauer, R. Dömer: "Modeling, Simulation and Synthesis in an Embedded Software Design Flow for an ARM Processor", Center for Embedded Computer Systems, Technical Report 06-06, May 2006.
G. Schirner, R. Dömer: "Quantitative Analysis of Transaction Level Models for the AMBA Bus", Proceedings of Design Automation and Test in Europe, Munich, Germany, March 2006.

2005

D. Shin, A. Gerstlauer, R. Dömer, D. Gajski: "Automatic Network Generation for System-on-Chip Communication Design", Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis, Jersey City, New Jersey, September 2005.
IESS Best Paper Award: G. Schirner, R. Dömer: "Abstract Communication Modeling: A Case Study Using the CAN Automotive Bus", Proceedings of the International Embedded Systems Symposium, "From Specification to Embedded Systems Application" (ed. A. Rettberg, M. Zanella, F. Rammig), Springer, Manaus, Brazil, August 2005.
H. Yu, R. Dömer, D. Gajski: "Software and Driver Synthesis from Transaction Level Models", Proceedings of the International Embedded Systems Symposium, "From Specification to Embedded Systems Application" (ed. A. Rettberg, M. Zanella, F. Rammig), Springer, Manaus, Brazil, August 2005.
D. Shin, A. Gerstlauer, R. Dömer, D. Gajski: "Automatic Generation of Communication Architectures", Proceedings of the International Embedded Systems Symposium, "From Specification to Embedded Systems Application" (ed. A. Rettberg, M. Zanella, F. Rammig), Springer, Manaus, Brazil, August 2005.
G. Sachdeva, R. Dömer, P. Chou: "System Modeling: A Case Study on a Wireless Sensor Network", Center for Embedded Computer Systems, Technical Report 05-12, June 2005.
D. Gajski, A. Gerstlauer, R. Dömer, S. Abdi, J. Peng, D. Shin: "TL Environment", Center for Embedded Computer Systems, Technical Report 05-10, July 2005.
G. Schirner, R. Dömer: "Using Result Oriented Modeling for Fast Yet Accurate TLMs", Center for Embedded Computer Systems, Technical Report 05-05, May 2005.
P. Chandraiah, R. Dömer: "Specification and Design of a MP3 Audio Decoder", Center for Embedded Computer Systems, Technical Report 05-04, May 2005.
G. Schirner, R. Dömer: "System Level Modeling of an AMBA Bus", Center for Embedded Computer Systems, Technical Report 05-03, April 2005.
A. Gerstlauer, D. Shin, R. Dömer, D. Gajski: "System-Level Communication Modeling for Network-on-Chip Synthesis", Proceedings of the Asia and South Pacific Design Automation Conference 2005, Shanghai, China, January 2005.
R. Dömer: "The SpecC Internal Representation (V2.2.0)", Center for Embedded Computer Systems, Internal Technical Report, January 2005.

2004

A. Gupta, R. Dömer: "System Design of Digital Camera Using SpecC", Center for Embedded Computer Systems, Technical Report 04-32, December 2004.
D. Shin, A. Gerstlauer, R. Dömer, D. Gajski: "System-on-Chip Communication Modeling Style Guide", Center for Embedded Computer Systems, Technical Report 04-25, July 2004.
D. Shin, L. Cai, A. Gerstlauer, R. Dömer, D. Gajski: "System-on-Chip Transaction-Level Modeling Style Guide", Center for Embedded Computer Systems, Technical Report 04-24, July 2004.
D. Shin, J. Peng, A. Gerstlauer, R. Dömer, D. Gajski: "System-on-Chip Network Modeling Style Guide", Center for Embedded Computer Systems, Technical Report 04-23, July 2004.
J. Peng, A. Gerstlauer, R. Dömer, D. Gajski: "System-on-Chip Architecture Modeling Style Guide", Center for Embedded Computer Systems, Technical Report 04-22, July 2004.
R. Dömer, A. Gerstlauer, D. Shin: "Cycle-accurate RTL Modeling with Multi-cycled and Pipelined Components", Center for Embedded Computer Systems, Technical Report 04-19, July 2004.
P. Chandraiah, H. Schirner, N. Srinivas, R. Dömer: "System-On Chip Modeling and Design: A Case Study on MP3 Decoder", Center for Embedded Computer Systems, Technical Report 04-17, June 2004.
H. Yu, R. Dömer, D. Gajski: "Embedded Software Generation from System Level Design Languages", Proceedings of the Asia and South Pacific Design Automation Conference 2004, Yokohama, Japan, January 2004.

2003

L. Cai, A. Gerstlauer, S. Abdi, J. Peng, D. Shin, H. Yu, R. Dömer, D. Gajski: "System-On-Chip Environment (SCE Version 2.2.0 Beta): Manual", Center for Embedded Computer Systems, Technical Report 03-45, December 2003.
D. Shin, A. Gerstlauer, R. Dömer, D. Gajski: "C-based Interactive RTL Design Methodology", Center for Embedded Computer Systems, Technical Report 03-42, December 2003.
S. Abdi, J. Peng, H. Yu, D. Shin, A. Gerstlauer, R. Dömer, D. Gajski: "System-On-Chip Environment, SCE Version 2.2.0 Beta, Tutorial", Center for Embedded Computer Systems, Technical Report 03-41, July 2003.
A. Gerstlauer, L. Cai, D. Shin, R. Dömer, D. Gajski: "System-On-Chip Component Models", Center for Embedded Computer Systems, Technical Report 03-26, August 2003.
A. Gerstlauer, K. Ramineni, R. Dömer, D. Gajski: "System-On-Chip Specification Style Guide", Center for Embedded Computer Systems, Technical Report 03-21, June 2003.
H. Yu, R. Dömer, D. Gajski: "Automatic Software Generation for System Level Design", Center for Embedded Computer Systems, Technical Report 03-18, May 2003.

2002

R. Dömer, A. Gerstlauer, D. Gajski: "SpecC Language Reference Manual, Version 2.0", SpecC Technology Open Consortium, Japan, December 2002.
W. Mueller, R. Dömer, A. Gerstlauer: "The Formal Execution Semantics of SpecC", Proceedings of the International Symposium on System Synthesis, Kyoto, Japan, October 2002.
S. Abdi, J. Peng, R. Dömer, D. Shin, A. Gerstlauer, A. Gluhak, L. Cai, Q. Xie, H. Yu, P. Zhang, D. Gajski: "System-on-Chip Environment (SCE) Tutorial", Center for Embedded Computer Systems, Technical Report 02-28, September 2002.
R. Dömer, D. Gajski, A. Gerstlauer: "SpecC Methodology for High-Level Modeling", 9th IEEE/DATC Electronic Design Processes Workshop, Monterey, California, April 2002.
R. Dömer: "The SpecC System-Level Design Language and Methodology, Part 1", Embedded Systems Conference 2002, San Francisco, California, March 2002.
R. Dömer, A. Gerstlauer, P. Kritzinger, M. Olivarez: "The SpecC System-Level Design Language and Methodology, Part 2", Embedded Systems Conference 2002, San Francisco, California, March 2002.
W. Mueller, R. Dömer, A. Gerstlauer: "The Formal Execution Semantics of SpecC", Center for Embedded Computer Systems, Technical Report 02-04, January 2002.

2001

R. Dömer: "SpecC Reference Compiler SCRC 1.1, Software Architecture and Implementation", Center for Embedded Computer Systems, Internal Technical Report, September 2001.
A. Gerstlauer, R. Dömer, J. Peng, D. Gajski: "System Design: A Practical Guide with SpecC", Kluwer Academic Publishers, Boston, June 2001. (ISBN 0-7923-7387-1)
Japanese translation by T. Kinoshita: SpecC Technology Open Consortium, Japan, June 2001.
Chinese translation by J. Bian, H. Xue: Tsinghua University Press, China, January 2008. (ISBN 978-7-302-13289-9)
R. Dömer, A. Gerstlauer, D. Gajski: "SpecC Language Reference Manual, Version 1.0", SpecC Technology Open Consortium, Japan, March 2001.

2000

R. Dömer: "System-level Modeling and Design with the SpecC Language", Dissertation, University of Dortmund, Germany, April 2000.
D. Gajski, J. Zhu, R. Dömer, A. Gerstlauer, S. Zhao: "SpecC: Specification Language and Methodology", Kluwer Academic Publishers, Boston, March 2000. (ISBN 0-7923-7822-9)
Japanese translation by T. Kinoshita: CQ Publishing, Japan, December 2000. (ISBN 4-7898-3353-4)
R. Dömer, D. Gajski: "Reuse and Protection of Intellectual Property in the SpecC System", Proceedings of the Asia and South Pacific Design Automation Conference 2000, Yokohama, Japan, January 2000.

1999

D. Gajski, J. Zhu, R. Dömer, A. Gerstlauer, S. Zhao: "The SpecC Methodology", University of California, Irvine, Technical Report ICS-TR-99-56, December 1999.
D. Gajski, R. Dömer, J. Zhu: "IP-centric Methodology and Specification Language", Chapter in "Distributed and Parallel Embedded Systems" (ed. F. Rammig), Kluwer Academic Publishers, Boston, September 1999. (ISBN 0-7923-8614-0)
D. Gajski, R. Dömer, J. Zhu: "IP-Centric Methodology and Design with the SpecC Language", Chapter 10 in "System-Level Synthesis" (ed. A. Jerraya, J. Mermet), Kluwer Academic Publishers, Dordrecht, May 1999. (ISBN 0-7923-5748-5)
R. Dömer: "The SpecC Internal Representation (V2.0.3)", University of California, Irvine, Internal Technical Report, January 1999.

1998

D. Gajski, R. Dömer, J. Zhu: "IP-centric Methodology and Design with the SpecC Language", NATO-ASI Workshop on System Level Synthesis for Electronic Design, Il Ciocco, Lucca, Italy, August 1998.
R. Dömer: "The SpecC Internal Representation (V2.0.1)", University of California, Irvine, Internal Technical Report, July 1998.
R. Dömer, D. Gajski, J. Zhu: "Specification and Design of Embedded Systems", In it+ti Magazine 3/98, Oldenbourg Verlag GmbH, Munich, Germany, June 1998.
D. Gajski, G. Aggarwal, E. Chang, R. Dömer, T. Ishii, J. Kleinsmith, J. Zhu: "IP-Centric Methodology", Proceedings of the 1st International Workshop on Design, Test and Applications, Dubrovnik, Croatia, June 1998.
R. Dömer, D. Gajski: "Comparison of the Scenic Design Environment and the SpecC System", University of California, Irvine, Internal Technical Report, May 1998.
R. Dömer, J. Zhu, D. Gajski: "The SpecC Language Reference Manual", University of California, Irvine, Technical Report ICS-TR-98-13, March 1998.
D. Gajski, G. Aggarwal, E. Chang, R. Dömer, T. Ishii, J. Kleinsmith, J. Zhu: "Methodology for Design of Embedded Systems", University of California, Irvine, Technical Report ICS-TR-98-07, March 1998.

1997

J. Zhu, R. Dömer, D. Gajski: "Syntax and Semantics of the SpecC Language", Proceedings of the Workshop on Synthesis and System Integration of Mixed Technologies 1997, Osaka, Japan, December 1997.
D. Gajski, J. Zhu, R. Dömer: "Essential Issues in Codesign", Chapter 1 in "Hardware/Software Co-Design: Principles and Practice" (ed. J. Staunstrup, W. Wolf), Kluwer Academic Publishers, Boston, October 1997. (ISBN 0-7923-8013-4)
D. Gajski, J. Zhu, R. Dömer: "Essential Issues in Codesign", University of California, Irvine, Technical Report ICS-TR-97-26, June 1997.
J. Zhu, R. Dömer, D. Gajski: "Syntax and Semantics of the SpecC+ Language", University of California, Irvine, Technical Report ICS-TR-97-16, April 1997.
D. Gajski, J. Zhu, R. Dömer: "The SpecC+ Language", University of California, Irvine, Technical Report ICS-TR-97-15, April 1997.
B. Landwehr, P. Marwedel, I. Markhof, R. Dömer: "Exploiting Isomorphism for Speeding-Up Instance-Binding in an Integrated Scheduling, Allocation and Assignment Approach to Architectural Synthesis", Proceedings of the Conference on Computer Hardware Description Languages and their Applications, Toledo, Spain, April 1997.
P. Marwedel, B. Landwehr, R. Dömer: "Built-in Chaining: Introducing Complex Components into Architectural Synthesis", Proceedings of the Asia South Pacific Design Automation Conference 1997, Chiba, Japan, January 1997.

1996

P. Marwedel, Birger Landwehr, R. Dömer: "Introducing Complex Components into Architectural Synthesis", University of Dortmund, Technical Report No. 611, April 1996.
P. Marwedel, S. Bashford, R. Dömer, B. Landwehr, I. Markhof: "A Technique for Avoiding Isomorphic Netlists in Architectural Synthesis", Proceedings of the European Design and Test Conference 1996, Paris, France, March 1996.

1995

P. Marwedel, S. Bashford, R. Dömer, B. Landwehr, I. Markhof:
"A Technique for Avoiding Isomorphic Netlists in Architectural Synthesis",
University of California, Irvine, Technical Report ICS-TR-95-28, August 1995.

1994

R. Dömer: "Optimale Mikroarchitektursynthese mittels Ganzzahliger Programmierung", Diploma Thesis, University of Dortmund, Germany, November 1994.
B. Landwehr, P. Marwedel, R. Dömer: "OSCAR: Optimum Simultaneous Scheduling, Allocation and Resource Binding Based on Integer Programming", Proceedings of the European Design Automation Conference 1994, Grenoble, France, September 1994.
B. Landwehr, P. Marwedel, R. Dömer: "OSCAR: Optimum Simultaneous Scheduling, Allocation and Resource Binding Based on Integer Programming", University of Dortmund, Technical Report No. 484, April 1994.

09/06/24 R. Doemer (doemer@uci.edu).