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- Daniel D. Gajski,
"System Level Design Flow: What is needed and what is not,"
CECS, UC Irvine, Technical Report CECS-TR-02-33, November 2002.
- Lukai Cai, Daniel D. Gajski,
"Variable Mapping of System Level Design,"
CECS, UC Irvine, Technical Report CECS-TR-02-32, October 2002.
- Lukai Cai, Daniel D. Gajski,
"Grouping-Based Architecture Exploration of
System-Level Design,"
CECS, UC Irvine, Technical Report CECS-TR-02-31, August 2002.
- Lukai Cai, Daniel D. Gajski, Mike Olivarez, Paul Kritzinger,
"C/C++ Based System Design Flow Using SpecC, VCC and SystemC,"
CECS, UC Irvine, Technical Report CECS-TR-02-30, June 2002.
- S. Abdi, J. Peng, R. Dömer, D. Shin, A. Gerstlauer, A. Gluhak,
L.Cai, Q. Xie, H. Yu, P. Zhang, D. Gajski,
"System-On-Chip Environment (SCE): Tutorial,"
CECS, UC Irvine, Technical Report CECS-TR-02-28, September 2002.
- Haobo Yu, Daniel D. Gajski,
"RTOS Modeling in System Level Synthesis,"
CECS, UC Irvine, Technical Report CECS-TR-02-25, August 2002.
- Lukai Cai, Daniel D. Gajski,
"Specification Tuning of System-Level Design,"
CECS, UC Irvine, Technical Report CECS-TR-02-20, June 2002.
- Lukai Cai, Daniel D. Gajski,
"Parallelization Optimization of System-Level Specification,"
CECS, UC Irvine, Technical Report CECS-TR-02-18, June 2002.
- Andreas Gerstlauer, Daniel D. Gajski,
"System-Level Abstraction Semantics,"
CECS, UC Irvine, Technical Report CECS-TR-02-17, July 2002.
- Andreas Gerstlauer,
"SpecC Modeling Guidelines,"
CECS, UC Irvine, Technical Report CECS-TR-02-16, April 2002.
- Junyu Peng, Lukai Cai, Andreas Gerstlauer, Daniel D. Gajski,
"Interactive System Design Flow,"
CECS, UC Irvine, Technical Report CECS-TR-02-15, April 2002.
- Junyu Peng, Samar Abdi, Daniel D. Gajski,
"Automatic Model Refinement for Fast Architecture Exploration,"
CECS, UC Irvine, Technical Report CECS-TR-02-14, April 2002.
- Dongwan Shin, Daniel D. Gajski,
"Interface Synthesis from Protocol Specification,"
CECS, UC Irvine, Technical Report CECS-TR-02-13, April 2002.
- Dongwan Shin, Daniel D. Gajski,
"Queue Generation Algorithm for Interface Synthesis,"
CECS, UC Irvine, Technical Report CECS-TR-02-12, February 2002.
- Dongwan Shin, Daniel D. Gajski,
"Scheduling in RTL Design Methodology,"
CECS, UC Irvine, Technical Report CECS-TR-02-11, April 2002.
- Pei Zhang, Daniel D. Gajski,
"RTL Design and Synthesis of Sequential Matrix Multiplication,"
CECS, UC Irvine, Technical Report CECS-TR-02-09, April 2002.
- Lukai Cai, Daniel D. Gajski,
"System Level Design Using SpecC Profiler,"
CECS, UC Irvine, Technical Report CECS-TR-02-08, April 2002.
- Lukai Cai, Daniel D. Gajski,
"Introduction of Design-Oriented Profiler of SpecC Language,"
CECS, UC Irvine, Technical Report CECS-TR-02-07, March 2002.
- Qiang Xie, Daniel D. Gajski,
"Parity Checker Implementations in SpecC,"
CECS, UC Irvine, Technical Report CECS-TR-02-06, January 2002.
- Haobo Yu, Daniel D. Gajski,
"Datapath Synthesis for a 16-bit Microprocessor,"
CECS, UC Irvine, Technical Report CECS-TR-02-05, January 2002.
- Wolfgang Mueller, Rainer Dömer, Daniel D. Gajski,
"The Formal Execution Semantics of SpecC,"
CECS, UC Irvine, Technical Report CECS-TR-02-04, January 2002.
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