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In this paper, we establish a theoretical framework for a new concept of scheduling called soft scheduling. In contrasts to the traditional schedulers referred as hard schedulers, soft schedulers make soft decisions at a time, or decisions that can be adjusted later. Soft scheduling has a potential to alleviate the phase coupling problem that has plagued traditional high level synthesis (HLS), HLS for deep submicron design and VLIW code generation. We then develop a specific soft scheduling formulation, called threaded schedule, under which a linear, optimal (in the sense of online optimality) algorithm is guaranteed.

In this paper, we develop a formal framework to widen the scope of retargetable compilation. The goal is achieved by the unification of architectural models for both the processor architecture and the ASIC architecture. This framework enables the unified treatment of code generation and behavioral synthesis, and is being used in our experimental codesign environment to drive system-on-a-chip synthesis from an object oriented language.

In this paper, we present new techniques which further improve the static compiled instruction set architecture (ISA) simulation by the aggressive utilization of the host machine resources. Such utilization is achieved by defining a low level code generation interface specialized for ISA simulation, rather than the traditional approaches which use C as a code generation interface. We are able to perform the simulation at a speed up to 100 millions of simulated instructions per second (MIPS). This result is only 1.1-2.5 times slower than the native execution on the host machine, the fastest to the best of our knowledge. Furthermore, the code generation interface is organized to implement a RISC like virtual machine, which makes our tool easily retargetable to many host platforms.

There is an increasing research interest in system level design languages which can carry designers from specification to implementation of system-on-a-chip. Unfortunately, two of the most important goals in designing such a language, are at odds with each other: Heterogeneity requires components of the system to be captured precisely by domain specific models to simplify analysis and synthesis; simplicity requires a consistent notation to avoid confusion. In this paper, we focus on our effort in resolving this dilemma in an extensible language called OpenJ. In contrast to the conventional monolithic languages, OpenJ has a layered structure consisting of the kernel layer, which is essentially an object oriented language designed to be simple, modular and polymorphic; and the open layer, which exports parameterizable language constructs; and the domain layer which precisely captures the computational models essential for embedded systems. The domain layer can be provided by vendors via a common protocol defined by open layer which enables the supersetting or/and subsetting of the kernel. A compiler has been built for this language and experiments are conducted for popular models such as synchronous, discrete event and dataflow.

In this paper, we describe an executable modeling language in the context of a homogeneous codesign methodology featuring synthesis, reuse and validation. A C based language called SpecC is proposed as an attempt to achieve these goals. The syntax and semantics of the language is presented and compared with existing HDLs. In conclusion, SpecC is conceptually more abstract, syntactically simpler, and semantically richer.

Elevating power estimation to architectural and behavioral level is essential for design exploration beyond logic level. In contrast with purely statistical approach, an analytical model is presented to estimate the power consumption in datapath and controller for a given RT level design. Experimental result shows that order of magnitude speed-up over low level tools as well as satisfactory accuracy can be achieved. This work can also serve as the basis for behavioral level estimation tool.